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GET /api/patches/816958/?format=api
{ "id": 816958, "url": "http://patchwork.ozlabs.org/api/patches/816958/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-6-git-send-email-jjhiblot@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506007346-10037-6-git-send-email-jjhiblot@ti.com>", "list_archive_url": null, "date": "2017-09-21T15:22:08", "name": "[U-Boot,05/23] mmc: omap_hsmmc: Enable DDR mode support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "d499e0b891934b996a891fd0e929d01c1b054741", "submitter": { "id": 70508, "url": "http://patchwork.ozlabs.org/api/people/70508/?format=api", "name": "Jean-Jacques Hiblot", "email": "jjhiblot@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-6-git-send-email-jjhiblot@ti.com/mbox/", "series": [ { "id": 4414, "url": "http://patchwork.ozlabs.org/api/series/4414/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4414", "date": "2017-09-21T15:22:03", "name": "mmc: omap5: Add support for UHS and HS200 modes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4414/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816958/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816958/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"qb9hZQH7\";\n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xygRz1sGgz9t4B\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 01:26:07 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid A38FEC22029; Thu, 21 Sep 2017 15:25:19 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 131DCC22056;\n\tThu, 21 Sep 2017 15:23:47 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 43915C22040; Thu, 21 Sep 2017 15:22:52 +0000 (UTC)", "from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80])\n\tby lists.denx.de (Postfix) with ESMTPS id A6D74C21FED\n\tfor <u-boot@lists.denx.de>; Thu, 21 Sep 2017 15:22:48 +0000 (UTC)", "from dflxv15.itg.ti.com ([128.247.5.124])\n\tby lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMk9n013915; \n\tThu, 21 Sep 2017 10:22:46 -0500", "from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMkCw009379;\n\tThu, 21 Sep 2017 10:22:46 -0500", "from DLEE114.ent.ti.com (157.170.170.25) by DLEE101.ent.ti.com\n\t(157.170.170.31) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 10:22:46 -0500", "from dflp32.itg.ti.com (10.64.6.15) by DLEE114.ent.ti.com\n\t(157.170.170.25) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 10:22:45 -0500", "from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMjuG014761;\n\tThu, 21 Sep 2017 10:22:45 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506007366;\n\tbh=5v5c15tPRrU81oWyaSXPjtcgCPbqr+t3OGMnNmK3mNw=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=qb9hZQH7fx0Q/zi9lditwriB1ZU1rHwAU8l49UKXgOsKQ7qy1xmZ6AobAQjH7ZeaS\n\tEKmo9Z5P2SSWMqitOmHsWTnegKwYRNQsbWB7afYrtpYNArkyNDEW+EdcmPm50lEYZh\n\t5TN3Jq4W3mWK4BTy404QHHhWclr4Y4prv5Vd2SA4=", "From": "Jean-Jacques Hiblot <jjhiblot@ti.com>", "To": "<jh80.chung@samsung.com>, <trini@konsulko.com>, <kishon@ti.com>,\n\t<sjg@chromium.org>, <lokeshvutla@ti.com>", "Date": "Thu, 21 Sep 2017 17:22:08 +0200", "Message-ID": "<1506007346-10037-6-git-send-email-jjhiblot@ti.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1506007346-10037-1-git-send-email-jjhiblot@ti.com>", "References": "<1506007346-10037-1-git-send-email-jjhiblot@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Cc": "u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH 05/23] mmc: omap_hsmmc: Enable DDR mode support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Kishon Vijay Abraham I <kishon@ti.com>\n\nIn order to enable DDR mode, Dual Data Rate mode bit has to be set in\nMMCHS_CON register. Set it here.\n\nSigned-off-by: Kishon Vijay Abraham I <kishon@ti.com>\nSigned-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>\n---\n arch/arm/include/asm/omap_mmc.h | 1 +\n drivers/mmc/omap_hsmmc.c | 5 +++++\n 2 files changed, 6 insertions(+)", "diff": "diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h\nindex 3f94f2e..341a2e2 100644\n--- a/arch/arm/include/asm/omap_mmc.h\n+++ b/arch/arm/include/asm/omap_mmc.h\n@@ -89,6 +89,7 @@ struct omap_hsmmc_plat {\n #define WPP_ACTIVEHIGH\t\t\t(0x0 << 8)\n #define RESERVED_MASK\t\t\t(0x3 << 9)\n #define CTPL_MMC_SD\t\t\t(0x0 << 11)\n+#define DDR\t\t\t\t(0x1 << 19)\n #define DMA_MASTER\t\t\t(0x1 << 20)\n #define BLEN_512BYTESLEN\t\t(0x200 << 0)\n #define NBLK_STPCNT\t\t\t(0x0 << 16)\ndiff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c\nindex 4a65a46..d5cd826 100644\n--- a/drivers/mmc/omap_hsmmc.c\n+++ b/drivers/mmc/omap_hsmmc.c\n@@ -271,6 +271,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc)\n \tval &= ~AC12_UHSMC_MASK;\n \tpriv->mode = mmc->selected_mode;\n \n+\tif (mmc_is_mode_ddr(priv->mode))\n+\t\twritel(readl(&mmc_base->con) | DDR, &mmc_base->con);\n+\telse\n+\t\twritel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);\n+\n \tswitch (priv->mode) {\n \tcase MMC_HS_200:\n \tcase UHS_SDR104:\n", "prefixes": [ "U-Boot", "05/23" ] }