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GET /api/patches/816956/?format=api
{ "id": 816956, "url": "http://patchwork.ozlabs.org/api/patches/816956/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-14-git-send-email-jjhiblot@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506007346-10037-14-git-send-email-jjhiblot@ti.com>", "list_archive_url": null, "date": "2017-09-21T15:22:16", "name": "[U-Boot,13/23] mmc: omap_hsmmc: allow the simple HS modes to use the default pinctrl", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "0c5702125a50a9de513752437809e77d8e9dcf63", "submitter": { "id": 70508, "url": "http://patchwork.ozlabs.org/api/people/70508/?format=api", "name": "Jean-Jacques Hiblot", "email": "jjhiblot@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-14-git-send-email-jjhiblot@ti.com/mbox/", "series": [ { "id": 4414, "url": "http://patchwork.ozlabs.org/api/series/4414/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4414", "date": "2017-09-21T15:22:03", "name": "mmc: omap5: Add support for UHS and HS200 modes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4414/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816956/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816956/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"nk4qSwlh\";\n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xygQX1QDcz9t4B\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 01:24:51 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid C779CC220A3; Thu, 21 Sep 2017 15:23:38 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4D77FC22020;\n\tThu, 21 Sep 2017 15:23:18 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid EA69DC21EAB; Thu, 21 Sep 2017 15:23:02 +0000 (UTC)", "from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17])\n\tby lists.denx.de (Postfix) with ESMTPS id 4E22CC22040\n\tfor <u-boot@lists.denx.de>; Thu, 21 Sep 2017 15:22:58 +0000 (UTC)", "from dflxv15.itg.ti.com ([128.247.5.124])\n\tby fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMu8U010609; \n\tThu, 21 Sep 2017 10:22:56 -0500", "from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMuZT009551;\n\tThu, 21 Sep 2017 10:22:56 -0500", "from DFLE113.ent.ti.com (10.64.6.34) by DFLE103.ent.ti.com\n\t(10.64.6.24) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 10:22:56 -0500", "from dflp32.itg.ti.com (10.64.6.15) by DFLE113.ent.ti.com\n\t(10.64.6.34) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 10:22:56 -0500", "from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMtDQ014890;\n\tThu, 21 Sep 2017 10:22:55 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506007376;\n\tbh=NgRR880NWDwV7hXlBT5hRtxnGSFNlpadSgGWRdW5nCA=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=nk4qSwlhTXTGNaVEP56VAM+l62PNOucSLlglpUiDrVuNxHcPzujed8f/b5Uoq6xWo\n\tRQ4tYxWc1yT0osqzUO5ZmS310zcMjKX9e2BipO6ZpRMnG4Eh0ikdCAWfb6L37wUW7d\n\t5/8uLYOmet4dr6bHcONt1WwGJom5s4885zpch/+k=", "From": "Jean-Jacques Hiblot <jjhiblot@ti.com>", "To": "<jh80.chung@samsung.com>, <trini@konsulko.com>, <kishon@ti.com>,\n\t<sjg@chromium.org>, <lokeshvutla@ti.com>", "Date": "Thu, 21 Sep 2017 17:22:16 +0200", "Message-ID": "<1506007346-10037-14-git-send-email-jjhiblot@ti.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1506007346-10037-1-git-send-email-jjhiblot@ti.com>", "References": "<1506007346-10037-1-git-send-email-jjhiblot@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Cc": "u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH 13/23] mmc: omap_hsmmc: allow the simple HS modes\n\tto use the default pinctrl", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "The default configuration is usually working fine for the the HS modes.\nDon't enforce the presence of a dedicated pinmux for the HS modes.\n\nSigned-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>\n---\n drivers/mmc/omap_hsmmc.c | 23 +++++++++++++----------\n 1 file changed, 13 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c\nindex a83c589..615eb4c 100644\n--- a/drivers/mmc/omap_hsmmc.c\n+++ b/drivers/mmc/omap_hsmmc.c\n@@ -328,6 +328,9 @@ static void omap_hsmmc_io_recalibrate(struct mmc *mmc)\n \t\tbreak;\n \t}\n \n+\tif (!pinctrl_state)\n+\t\tpinctrl_state = priv->default_pinctrl_state;\n+\n \tif (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {\n \t\tif (pinctrl_state->iodelay)\n \t\t\tlate_recalibrate_iodelay(pinctrl_state->padconf,\n@@ -1583,7 +1586,7 @@ err_pinctrl_state:\n \treturn 0;\n }\n \n-#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode)\t\t\t\t\\\n+#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tstruct omap_hsmmc_pinctrl_state *s = NULL;\t\t\\\n \t\tchar str[20];\t\t\t\t\t\t\\\n@@ -1598,7 +1601,7 @@ err_pinctrl_state:\n \t\tif (!s)\t\t\t\t\t\t\t\\\n \t\t\ts = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode);\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\t\tif (!s) {\t\t\t\t\t\t\\\n+\t\tif (!s && !optional) {\t\t\t\t\t\\\n \t\t\tdebug(\"%s: no pinctrl for %s\\n\",\t\t\\\n \t\t\t mmc->dev->name, #mode);\t\t\t\\\n \t\t\tcfg->host_caps &= ~(capmask);\t\t\t\\\n@@ -1624,15 +1627,15 @@ static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)\n \n \tpriv->default_pinctrl_state = default_pinctrl;\n \n-\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104);\n-\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50);\n-\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50);\n-\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25);\n-\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12);\n+\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);\n+\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);\n+\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);\n+\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);\n+\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);\n \n-\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v);\n-\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v);\n-\tOMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs);\n+\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);\n+\tOMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);\n+\tOMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);\n \n \treturn 0;\n }\n", "prefixes": [ "U-Boot", "13/23" ] }