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GET /api/patches/816955/?format=api
{ "id": 816955, "url": "http://patchwork.ozlabs.org/api/patches/816955/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-2-git-send-email-jjhiblot@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506007346-10037-2-git-send-email-jjhiblot@ti.com>", "list_archive_url": null, "date": "2017-09-21T15:22:04", "name": "[U-Boot,01/23] mmc: omap_hsmmc: cleanup clock configuration", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "55f7192abce9e563b32087fcfdf8fce1188af6f0", "submitter": { "id": 70508, "url": "http://patchwork.ozlabs.org/api/people/70508/?format=api", "name": "Jean-Jacques Hiblot", "email": "jjhiblot@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-2-git-send-email-jjhiblot@ti.com/mbox/", "series": [ { "id": 4414, "url": "http://patchwork.ozlabs.org/api/series/4414/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4414", "date": "2017-09-21T15:22:03", "name": "mmc: omap5: Add support for UHS and HS200 modes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4414/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816955/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816955/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"jBfoq82p\";\n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xygNx2n2tz9s0Z\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 01:23:29 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 0218BC21FEE; Thu, 21 Sep 2017 15:23:03 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id B4FCFC21FCF;\n\tThu, 21 Sep 2017 15:22:45 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 9938BC21C54; Thu, 21 Sep 2017 15:22:43 +0000 (UTC)", "from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80])\n\tby lists.denx.de (Postfix) with ESMTPS id 008E2C21C4E\n\tfor <u-boot@lists.denx.de>; Thu, 21 Sep 2017 15:22:42 +0000 (UTC)", "from dflxv15.itg.ti.com ([128.247.5.124])\n\tby lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMefZ013899; \n\tThu, 21 Sep 2017 10:22:40 -0500", "from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMet5009283;\n\tThu, 21 Sep 2017 10:22:40 -0500", "from DFLE102.ent.ti.com (10.64.6.23) by DFLE100.ent.ti.com\n\t(10.64.6.21) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 10:22:40 -0500", "from dflp33.itg.ti.com (10.64.6.16) by DFLE102.ent.ti.com\n\t(10.64.6.23) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 10:22:40 -0500", "from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMdGh022746;\n\tThu, 21 Sep 2017 10:22:40 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506007360;\n\tbh=JIe6eYjyfUNRSu3kAUH5M/tkknd8EjmUZQpZkC1CMhE=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=jBfoq82p6UubcrdnEa0PW6T2zhtgxFv6ctD+L+UyCE4L5i+oTg4LiRHjW3V8mpni9\n\tIHOzTvNm5glC3qv2L6t86hePEccPgipYgENZRt4Ineslw2+q13B65/PlJtWtCfP3hy\n\tw5mve2cPew5G3GQHHU2k5fLuVG0Yb8bo88zeFoOM=", "From": "Jean-Jacques Hiblot <jjhiblot@ti.com>", "To": "<jh80.chung@samsung.com>, <trini@konsulko.com>, <kishon@ti.com>,\n\t<sjg@chromium.org>, <lokeshvutla@ti.com>", "Date": "Thu, 21 Sep 2017 17:22:04 +0200", "Message-ID": "<1506007346-10037-2-git-send-email-jjhiblot@ti.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1506007346-10037-1-git-send-email-jjhiblot@ti.com>", "References": "<1506007346-10037-1-git-send-email-jjhiblot@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Cc": "u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH 01/23] mmc: omap_hsmmc: cleanup clock configuration", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Kishon Vijay Abraham I <kishon@ti.com>\n\nAdd a separate function for starting the clock, stopping the clock and\nsetting the clock. Starting the clock and stopping the clock can\nbe used irrespective of setting the clock (For example during iodelay\nrecalibration).\nAlso set the clock only if there is a change in frequency.\n\nSigned-off-by: Kishon Vijay Abraham I <kishon@ti.com>\nSigned-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>\n---\n arch/arm/include/asm/omap_mmc.h | 2 ++\n drivers/mmc/omap_hsmmc.c | 74 ++++++++++++++++++++++++++++-------------\n 2 files changed, 52 insertions(+), 24 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h\nindex bf9de9b..102aec2 100644\n--- a/arch/arm/include/asm/omap_mmc.h\n+++ b/arch/arm/include/asm/omap_mmc.h\n@@ -172,6 +172,8 @@ struct omap_hsmmc_plat {\n #define CLK_400KHZ\t\t\t1\n #define CLK_MISC\t\t\t2\n \n+#define CLKD_MAX\t\t\t0x3FF\t/* max clock divisor: 1023 */\n+\n #define RSP_TYPE_NONE\t(RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)\n #define MMC_CMD0\t(INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)\n \ndiff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c\nindex 1c3d1a5..6ef8295 100644\n--- a/drivers/mmc/omap_hsmmc.c\n+++ b/drivers/mmc/omap_hsmmc.c\n@@ -62,6 +62,7 @@ struct omap_hsmmc_data {\n #if !CONFIG_IS_ENABLED(DM_MMC)\n \tstruct mmc_config cfg;\n #endif\n+\tuint clock;\n #ifdef OMAP_HSMMC_USE_GPIO\n #if CONFIG_IS_ENABLED(DM_MMC)\n \tstruct gpio_desc cd_gpio;\t/* Change Detect GPIO */\n@@ -114,6 +115,8 @@ struct omap_hsmmc_adma_desc {\n static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);\n static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,\n \t\t\tunsigned int siz);\n+static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);\n+static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);\n \n static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)\n {\n@@ -762,6 +765,51 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,\n \treturn 0;\n }\n \n+static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)\n+{\n+\twritel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);\n+}\n+\n+static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)\n+{\n+\twritel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);\n+}\n+\n+static void omap_hsmmc_set_clock(struct mmc *mmc)\n+{\n+\tstruct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);\n+\tstruct hsmmc *mmc_base;\n+\tunsigned int dsor = 0;\n+\tulong start;\n+\n+\tmmc_base = priv->base_addr;\n+\tomap_hsmmc_stop_clock(mmc_base);\n+\n+\t/* TODO: Is setting DTO required here? */\n+\tmmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),\n+\t\t (ICE_STOP | DTO_15THDTO));\n+\n+\tif (mmc->clock != 0) {\n+\t\tdsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);\n+\t\tif (dsor > CLKD_MAX)\n+\t\t\tdsor = CLKD_MAX;\n+\t}\n+\n+\tmmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,\n+\t\t (dsor << CLKD_OFFSET) | ICE_OSCILLATE);\n+\n+\tstart = get_timer(0);\n+\twhile ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {\n+\t\tif (get_timer(0) - start > MAX_RETRY_MS) {\n+\t\t\tprintf(\"%s: timedout waiting for ics!\\n\", __func__);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tpriv->clock = mmc->clock;\n+\tomap_hsmmc_start_clock(mmc_base);\n+}\n+\n #if !CONFIG_IS_ENABLED(DM_MMC)\n static int omap_hsmmc_set_ios(struct mmc *mmc)\n {\n@@ -774,8 +822,6 @@ static int omap_hsmmc_set_ios(struct udevice *dev)\n \tstruct mmc *mmc = upriv->mmc;\n #endif\n \tstruct hsmmc *mmc_base;\n-\tunsigned int dsor = 0;\n-\tulong start;\n \n \tmmc_base = priv->base_addr;\n \t/* configue bus width */\n@@ -801,28 +847,8 @@ static int omap_hsmmc_set_ios(struct udevice *dev)\n \t\tbreak;\n \t}\n \n-\t/* configure clock with 96Mhz system clock.\n-\t */\n-\tif (mmc->clock != 0) {\n-\t\tdsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);\n-\t\tif ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)\n-\t\t\tdsor++;\n-\t}\n-\n-\tmmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),\n-\t\t\t\t(ICE_STOP | DTO_15THDTO));\n-\n-\tmmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,\n-\t\t\t\t(dsor << CLKD_OFFSET) | ICE_OSCILLATE);\n-\n-\tstart = get_timer(0);\n-\twhile ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {\n-\t\tif (get_timer(0) - start > MAX_RETRY_MS) {\n-\t\t\tprintf(\"%s: timedout waiting for ics!\\n\", __func__);\n-\t\t\treturn -ETIMEDOUT;\n-\t\t}\n-\t}\n-\twritel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);\n+\tif (priv->clock != mmc->clock)\n+\t\tomap_hsmmc_set_clock(mmc);\n \n \treturn 0;\n }\n", "prefixes": [ "U-Boot", "01/23" ] }