Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/816918/?format=api
{ "id": 816918, "url": "http://patchwork.ozlabs.org/api/patches/816918/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506004213-22620-20-git-send-email-jjhiblot@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506004213-22620-20-git-send-email-jjhiblot@ti.com>", "list_archive_url": null, "date": "2017-09-21T14:30:06", "name": "[U-Boot,v2,19/26] mmc: add HS200 support in MMC core", "commit_ref": "634d48494011fafc615ce613ab9aeeee77a9434d", "pull_url": null, "state": "accepted", "archived": false, "hash": "83f75479d446794dab3d424d7f055e57de4216dd", "submitter": { "id": 70508, "url": "http://patchwork.ozlabs.org/api/people/70508/?format=api", "name": "Jean-Jacques Hiblot", "email": "jjhiblot@ti.com" }, "delegate": { "id": 12423, "url": "http://patchwork.ozlabs.org/api/users/12423/?format=api", "username": "Jaehoon", "first_name": "Jaehoon", "last_name": "Chung", "email": "jh80.chung@samsung.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506004213-22620-20-git-send-email-jjhiblot@ti.com/mbox/", "series": [ { "id": 4400, "url": "http://patchwork.ozlabs.org/api/series/4400/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4400", "date": "2017-09-21T14:29:47", "name": "mmc: Add support for HS200 and UHS modes", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/4400/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816918/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816918/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"moimMoV5\";\n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyfZ85y4rz9t3v\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 00:46:24 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 6DC0DC22069; Thu, 21 Sep 2017 14:35:26 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 2D20BC22031;\n\tThu, 21 Sep 2017 14:32:41 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 6225EC22029; Thu, 21 Sep 2017 14:31:09 +0000 (UTC)", "from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77])\n\tby lists.denx.de (Postfix) with ESMTPS id B417DC21FD8\n\tfor <u-boot@lists.denx.de>; Thu, 21 Sep 2017 14:31:02 +0000 (UTC)", "from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LEV0kj029513; \n\tThu, 21 Sep 2017 09:31:00 -0500", "from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEV0jx020046; \n\tThu, 21 Sep 2017 09:31:00 -0500", "from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com\n\t(10.64.6.24) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 09:31:00 -0500", "from dflp32.itg.ti.com (10.64.6.15) by DFLE105.ent.ti.com\n\t(10.64.6.26) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 09:31:00 -0500", "from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEUwRg016550;\n\tThu, 21 Sep 2017 09:30:59 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506004260;\n\tbh=bCpPxlrUmLWlMAnUe4EuTZWkrc9NTR7RynAwbDW1bgA=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=moimMoV5WDlor+ELfmWlYMvKjNgYlVSsg5r4gj82fytBonfJBJxFb9miX/Y+6CZ5E\n\thhkiy/nqt197XtIniErEBd+2lBoV4dwDTqvzhOHhmpdeI4Aoww8/wRcZO6DbrVklOJ\n\tSNmmSkXG5q/F3e7tGnA9R3JoeZC6Ywt+/Tscbti8=", "From": "Jean-Jacques Hiblot <jjhiblot@ti.com>", "To": "<jh80.chung@samsung.com>, <trini@konsulko.com>, <kishon@ti.com>,\n\t<sjg@chromium.org>", "Date": "Thu, 21 Sep 2017 16:30:06 +0200", "Message-ID": "<1506004213-22620-20-git-send-email-jjhiblot@ti.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1506004213-22620-1-git-send-email-jjhiblot@ti.com>", "References": "<1506004213-22620-1-git-send-email-jjhiblot@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Cc": "u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 19/26] mmc: add HS200 support in MMC core", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Kishon Vijay Abraham I <kishon@ti.com>\n\nAdd HS200 to the list of supported modes and introduce tuning in the MMC\nstartup process.\n\nSigned-off-by: Kishon Vijay Abraham I <kishon@ti.com>\nSigned-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>\nReviewed-by: Simon Glass <sjg@chromium.org>\n---\n drivers/mmc/mmc.c | 22 ++++++++++++++++++++--\n include/mmc.h | 18 ++++++++++++++++++\n 2 files changed, 38 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c\nindex 3e2e549..c663709 100644\n--- a/drivers/mmc/mmc.c\n+++ b/drivers/mmc/mmc.c\n@@ -621,6 +621,10 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)\n \tcase MMC_HS_52:\n \tcase MMC_DDR_52:\n \t\tspeed_bits = EXT_CSD_TIMING_HS;\n+\t\tbreak;\n+\tcase MMC_HS_200:\n+\t\tspeed_bits = EXT_CSD_TIMING_HS200;\n+\t\tbreak;\n \tcase MMC_LEGACY:\n \t\tspeed_bits = EXT_CSD_TIMING_LEGACY;\n \t\tbreak;\n@@ -667,9 +671,12 @@ static int mmc_get_capabilities(struct mmc *mmc)\n \n \tmmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;\n \n-\tcardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;\n+\tcardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;\n \n-\t/* High Speed is set, there are two types: 52MHz and 26MHz */\n+\tif (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |\n+\t\t\tEXT_CSD_CARD_TYPE_HS200_1_8V)) {\n+\t\tmmc->card_caps |= MMC_MODE_HS200;\n+\t}\n \tif (cardtype & EXT_CSD_CARD_TYPE_52) {\n \t\tif (cardtype & EXT_CSD_CARD_TYPE_DDR_52)\n \t\t\tmmc->card_caps |= MMC_MODE_DDR_52MHz;\n@@ -1268,6 +1275,7 @@ void mmc_dump_capabilities(const char *text, uint caps)\n struct mode_width_tuning {\n \tenum bus_mode mode;\n \tuint widths;\n+\tuint tuning;\n };\n \n static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)\n@@ -1383,6 +1391,7 @@ static const struct mode_width_tuning mmc_modes_by_pref[] = {\n \t{\n \t\t.mode = MMC_HS_200,\n \t\t.widths = MMC_MODE_8BIT | MMC_MODE_4BIT,\n+\t\t.tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200\n \t},\n \t{\n \t\t.mode = MMC_DDR_52,\n@@ -1484,6 +1493,15 @@ static int mmc_select_mode_and_width(struct mmc *mmc)\n \t\t\tmmc_select_mode(mmc, mwt->mode);\n \t\t\tmmc_set_clock(mmc, mmc->tran_speed, false);\n \n+\t\t\t/* execute tuning if needed */\n+\t\t\tif (mwt->tuning) {\n+\t\t\t\terr = mmc_execute_tuning(mmc, mwt->tuning);\n+\t\t\t\tif (err) {\n+\t\t\t\t\tdebug(\"tuning failed\\n\");\n+\t\t\t\t\tgoto error;\n+\t\t\t\t}\n+\t\t\t}\n+\n \t\t\t/* do a transfer to check the configuration */\n \t\t\terr = mmc_read_and_compare_ext_csd(mmc);\n \t\t\tif (!err)\ndiff --git a/include/mmc.h b/include/mmc.h\nindex 56fa869..407fddf 100644\n--- a/include/mmc.h\n+++ b/include/mmc.h\n@@ -56,6 +56,7 @@\n #define MMC_MODE_HS\t\t(MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))\n #define MMC_MODE_HS_52MHz\tMMC_CAP(MMC_HS_52)\n #define MMC_MODE_DDR_52MHz\tMMC_CAP(MMC_DDR_52)\n+#define MMC_MODE_HS200\t\tMMC_CAP(MMC_HS_200)\n \n #define MMC_MODE_8BIT\t\tBIT(30)\n #define MMC_MODE_4BIT\t\tBIT(29)\n@@ -86,6 +87,7 @@\n #define MMC_CMD_SET_BLOCKLEN\t\t16\n #define MMC_CMD_READ_SINGLE_BLOCK\t17\n #define MMC_CMD_READ_MULTIPLE_BLOCK\t18\n+#define MMC_CMD_SEND_TUNING_BLOCK_HS200\t21\n #define MMC_CMD_SET_BLOCK_COUNT 23\n #define MMC_CMD_WRITE_SINGLE_BLOCK\t24\n #define MMC_CMD_WRITE_MULTIPLE_BLOCK\t25\n@@ -113,6 +115,13 @@\n #define SD_CMD_APP_SEND_OP_COND\t\t41\n #define SD_CMD_APP_SEND_SCR\t\t51\n \n+static inline bool mmc_is_tuning_cmd(uint cmdidx)\n+{\n+\tif (cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)\n+\t\treturn true;\n+\treturn false;\n+}\n+\n /* SCR definitions in different words */\n #define SD_HIGHSPEED_BUSY\t0x00020000\n #define SD_HIGHSPEED_SUPPORTED\t0x00020000\n@@ -210,6 +219,13 @@\n #define EXT_CSD_CARD_TYPE_DDR_52\t(EXT_CSD_CARD_TYPE_DDR_1_8V \\\n \t\t\t\t\t| EXT_CSD_CARD_TYPE_DDR_1_2V)\n \n+#define EXT_CSD_CARD_TYPE_HS200_1_8V\tBIT(4)\t/* Card can run at 200MHz */\n+\t\t\t\t\t\t/* SDR mode @1.8V I/O */\n+#define EXT_CSD_CARD_TYPE_HS200_1_2V\tBIT(5)\t/* Card can run at 200MHz */\n+\t\t\t\t\t\t/* SDR mode @1.2V I/O */\n+#define EXT_CSD_CARD_TYPE_HS200\t\t(EXT_CSD_CARD_TYPE_HS200_1_8V | \\\n+\t\t\t\t\t EXT_CSD_CARD_TYPE_HS200_1_2V)\n+\n #define EXT_CSD_BUS_WIDTH_1\t0\t/* Card is in 1 bit mode */\n #define EXT_CSD_BUS_WIDTH_4\t1\t/* Card is in 4 bit mode */\n #define EXT_CSD_BUS_WIDTH_8\t2\t/* Card is in 8 bit mode */\n@@ -219,6 +235,8 @@\n \n #define EXT_CSD_TIMING_LEGACY\t0\t/* no high speed */\n #define EXT_CSD_TIMING_HS\t1\t/* HS */\n+#define EXT_CSD_TIMING_HS200\t2\t/* HS200 */\n+\n #define EXT_CSD_BOOT_ACK_ENABLE\t\t\t(1 << 6)\n #define EXT_CSD_BOOT_PARTITION_ENABLE\t\t(1 << 3)\n #define EXT_CSD_PARTITION_ACCESS_ENABLE\t\t(1 << 0)\n", "prefixes": [ "U-Boot", "v2", "19/26" ] }