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GET /api/patches/816896/?format=api
{ "id": 816896, "url": "http://patchwork.ozlabs.org/api/patches/816896/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506004213-22620-4-git-send-email-jjhiblot@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506004213-22620-4-git-send-email-jjhiblot@ti.com>", "list_archive_url": null, "date": "2017-09-21T14:29:50", "name": "[U-Boot,v2,03/26] mmc: move the MMC startup for version above v4.0 in a separate function", "commit_ref": "c744b6f6dcf6054f4eb8ff2428edb6ba408c4a46", "pull_url": null, "state": "accepted", "archived": false, "hash": "5805a9ec0e02c156707258f36c97db18963e8812", "submitter": { "id": 70508, "url": "http://patchwork.ozlabs.org/api/people/70508/?format=api", "name": "Jean-Jacques Hiblot", "email": "jjhiblot@ti.com" }, "delegate": { "id": 12423, "url": "http://patchwork.ozlabs.org/api/users/12423/?format=api", "username": "Jaehoon", "first_name": "Jaehoon", "last_name": "Chung", "email": "jh80.chung@samsung.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506004213-22620-4-git-send-email-jjhiblot@ti.com/mbox/", "series": [ { "id": 4400, "url": "http://patchwork.ozlabs.org/api/series/4400/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4400", "date": "2017-09-21T14:29:47", "name": "mmc: Add support for HS200 and UHS modes", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/4400/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816896/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816896/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"YpnVF+Hj\";\n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyfHB3SfFz9sBZ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 00:33:26 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 00563C21D8C; Thu, 21 Sep 2017 14:31:21 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 23995C21E57;\n\tThu, 21 Sep 2017 14:30:44 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 2FE40C21F7D; Thu, 21 Sep 2017 14:30:34 +0000 (UTC)", "from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77])\n\tby lists.denx.de (Postfix) with ESMTPS id 75933C21E48\n\tfor <u-boot@lists.denx.de>; Thu, 21 Sep 2017 14:30:30 +0000 (UTC)", "from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LEUPhn029417; \n\tThu, 21 Sep 2017 09:30:25 -0500", "from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEUPHI019492; \n\tThu, 21 Sep 2017 09:30:25 -0500", "from DLEE100.ent.ti.com (157.170.170.30) by DLEE101.ent.ti.com\n\t(157.170.170.31) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 09:30:26 -0500", "from dlep33.itg.ti.com (157.170.170.75) by DLEE100.ent.ti.com\n\t(157.170.170.30) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 09:30:25 -0500", "from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEUOBZ011161;\n\tThu, 21 Sep 2017 09:30:24 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506004225;\n\tbh=eLNT1+6A+vsxlJeg1avWn+AeHCc6uqkswzcjnGEwIWU=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=YpnVF+HjKOAT+gTl0Jpyi9UfDcK/MeBijwAa2Jy9aY4Bx9bqMAssC8cAyRckqfp8S\n\tuXJBFBWdJdmQV8nXf2sjy35JkSwooRoonot7mRBxcMW+KQaCcPlhpYhmK+9wFsyWoh\n\tPD2ttXeBcYyG3ORnyXdLpaYtDb4XK/EwC025aBw0=", "From": "Jean-Jacques Hiblot <jjhiblot@ti.com>", "To": "<jh80.chung@samsung.com>, <trini@konsulko.com>, <kishon@ti.com>,\n\t<sjg@chromium.org>", "Date": "Thu, 21 Sep 2017 16:29:50 +0200", "Message-ID": "<1506004213-22620-4-git-send-email-jjhiblot@ti.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1506004213-22620-1-git-send-email-jjhiblot@ti.com>", "References": "<1506004213-22620-1-git-send-email-jjhiblot@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Cc": "u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 03/26] mmc: move the MMC startup for version\n\tabove v4.0 in a separate function", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "no functionnal change. This is only to further reduce the size o\nmmc_startup().\n\nSigned-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>\nReviewed-by: Simon Glass <sjg@chromium.org>\n---\n drivers/mmc/mmc.c | 318 ++++++++++++++++++++++++++++--------------------------\n 1 file changed, 167 insertions(+), 151 deletions(-)", "diff": "diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c\nindex 1946875..7c100a4 100644\n--- a/drivers/mmc/mmc.c\n+++ b/drivers/mmc/mmc.c\n@@ -1249,15 +1249,176 @@ static int mmc_select_bus_freq_width(struct mmc *mmc, const u8 *ext_csd)\n \treturn err;\n }\n \n+static int mmc_startup_v4(struct mmc *mmc, u8 *ext_csd)\n+{\n+\tint err, i;\n+\tu64 capacity;\n+\tbool has_parts = false;\n+\tbool part_completed;\n+\n+\tif (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))\n+\t\treturn 0;\n+\n+\t/* check ext_csd version and capacity */\n+\terr = mmc_send_ext_csd(mmc, ext_csd);\n+\tif (err)\n+\t\treturn err;\n+\tif (ext_csd[EXT_CSD_REV] >= 2) {\n+\t\t/*\n+\t\t * According to the JEDEC Standard, the value of\n+\t\t * ext_csd's capacity is valid if the value is more\n+\t\t * than 2GB\n+\t\t */\n+\t\tcapacity = ext_csd[EXT_CSD_SEC_CNT] << 0\n+\t\t\t\t| ext_csd[EXT_CSD_SEC_CNT + 1] << 8\n+\t\t\t\t| ext_csd[EXT_CSD_SEC_CNT + 2] << 16\n+\t\t\t\t| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;\n+\t\tcapacity *= MMC_MAX_BLOCK_LEN;\n+\t\tif ((capacity >> 20) > 2 * 1024)\n+\t\t\tmmc->capacity_user = capacity;\n+\t}\n+\n+\tswitch (ext_csd[EXT_CSD_REV]) {\n+\tcase 1:\n+\t\tmmc->version = MMC_VERSION_4_1;\n+\t\tbreak;\n+\tcase 2:\n+\t\tmmc->version = MMC_VERSION_4_2;\n+\t\tbreak;\n+\tcase 3:\n+\t\tmmc->version = MMC_VERSION_4_3;\n+\t\tbreak;\n+\tcase 5:\n+\t\tmmc->version = MMC_VERSION_4_41;\n+\t\tbreak;\n+\tcase 6:\n+\t\tmmc->version = MMC_VERSION_4_5;\n+\t\tbreak;\n+\tcase 7:\n+\t\tmmc->version = MMC_VERSION_5_0;\n+\t\tbreak;\n+\tcase 8:\n+\t\tmmc->version = MMC_VERSION_5_1;\n+\t\tbreak;\n+\t}\n+\n+\t/* The partition data may be non-zero but it is only\n+\t * effective if PARTITION_SETTING_COMPLETED is set in\n+\t * EXT_CSD, so ignore any data if this bit is not set,\n+\t * except for enabling the high-capacity group size\n+\t * definition (see below).\n+\t */\n+\tpart_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &\n+\t\t\t EXT_CSD_PARTITION_SETTING_COMPLETED);\n+\n+\t/* store the partition info of emmc */\n+\tmmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];\n+\tif ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||\n+\t ext_csd[EXT_CSD_BOOT_MULT])\n+\t\tmmc->part_config = ext_csd[EXT_CSD_PART_CONF];\n+\tif (part_completed &&\n+\t (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))\n+\t\tmmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];\n+\n+\tmmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;\n+\n+\tmmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\tint idx = EXT_CSD_GP_SIZE_MULT + i * 3;\n+\t\tuint mult = (ext_csd[idx + 2] << 16) +\n+\t\t\t(ext_csd[idx + 1] << 8) + ext_csd[idx];\n+\t\tif (mult)\n+\t\t\thas_parts = true;\n+\t\tif (!part_completed)\n+\t\t\tcontinue;\n+\t\tmmc->capacity_gp[i] = mult;\n+\t\tmmc->capacity_gp[i] *=\n+\t\t\text_csd[EXT_CSD_HC_ERASE_GRP_SIZE];\n+\t\tmmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];\n+\t\tmmc->capacity_gp[i] <<= 19;\n+\t}\n+\n+\tif (part_completed) {\n+\t\tmmc->enh_user_size =\n+\t\t\t(ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +\n+\t\t\t(ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +\n+\t\t\text_csd[EXT_CSD_ENH_SIZE_MULT];\n+\t\tmmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];\n+\t\tmmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];\n+\t\tmmc->enh_user_size <<= 19;\n+\t\tmmc->enh_user_start =\n+\t\t\t(ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +\n+\t\t\t(ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +\n+\t\t\t(ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +\n+\t\t\text_csd[EXT_CSD_ENH_START_ADDR];\n+\t\tif (mmc->high_capacity)\n+\t\t\tmmc->enh_user_start <<= 9;\n+\t}\n+\n+\t/*\n+\t * Host needs to enable ERASE_GRP_DEF bit if device is\n+\t * partitioned. This bit will be lost every time after a reset\n+\t * or power off. This will affect erase size.\n+\t */\n+\tif (part_completed)\n+\t\thas_parts = true;\n+\tif ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&\n+\t (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))\n+\t\thas_parts = true;\n+\tif (has_parts) {\n+\t\terr = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,\n+\t\t\t\t EXT_CSD_ERASE_GROUP_DEF, 1);\n+\n+\t\tif (err)\n+\t\t\treturn err;\n+\n+\t\text_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;\n+\t}\n+\n+\tif (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {\n+\t\t/* Read out group size from ext_csd */\n+\t\tmmc->erase_grp_size =\n+\t\t\text_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;\n+\t\t/*\n+\t\t * if high capacity and partition setting completed\n+\t\t * SEC_COUNT is valid even if it is smaller than 2 GiB\n+\t\t * JEDEC Standard JESD84-B45, 6.2.4\n+\t\t */\n+\t\tif (mmc->high_capacity && part_completed) {\n+\t\t\tcapacity = (ext_csd[EXT_CSD_SEC_CNT]) |\n+\t\t\t\t(ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |\n+\t\t\t\t(ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |\n+\t\t\t\t(ext_csd[EXT_CSD_SEC_CNT + 3] << 24);\n+\t\t\tcapacity *= MMC_MAX_BLOCK_LEN;\n+\t\t\tmmc->capacity_user = capacity;\n+\t\t}\n+\t} else {\n+\t\t/* Calculate the group size from the csd value. */\n+\t\tint erase_gsz, erase_gmul;\n+\n+\t\terase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;\n+\t\terase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;\n+\t\tmmc->erase_grp_size = (erase_gsz + 1)\n+\t\t\t* (erase_gmul + 1);\n+\t}\n+\n+\tmmc->hc_wp_grp_size = 1024\n+\t\t* ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]\n+\t\t* ext_csd[EXT_CSD_HC_WP_GRP_SIZE];\n+\n+\tmmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];\n+\n+\treturn 0;\n+}\n+\n static int mmc_startup(struct mmc *mmc)\n {\n \tint err, i;\n \tuint mult, freq;\n-\tu64 cmult, csize, capacity;\n+\tu64 cmult, csize;\n \tstruct mmc_cmd cmd;\n \tALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);\n-\tbool has_parts = false;\n-\tbool part_completed;\n \tstruct blk_desc *bdesc;\n \n #ifdef CONFIG_MMC_SPI_CRC_ON\n@@ -1405,155 +1566,10 @@ static int mmc_startup(struct mmc *mmc)\n \t */\n \tmmc->erase_grp_size = 1;\n \tmmc->part_config = MMCPART_NOAVAILABLE;\n-\tif (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {\n-\t\t/* check ext_csd version and capacity */\n-\t\terr = mmc_send_ext_csd(mmc, ext_csd);\n-\t\tif (err)\n-\t\t\treturn err;\n-\t\tif (ext_csd[EXT_CSD_REV] >= 2) {\n-\t\t\t/*\n-\t\t\t * According to the JEDEC Standard, the value of\n-\t\t\t * ext_csd's capacity is valid if the value is more\n-\t\t\t * than 2GB\n-\t\t\t */\n-\t\t\tcapacity = ext_csd[EXT_CSD_SEC_CNT] << 0\n-\t\t\t\t\t| ext_csd[EXT_CSD_SEC_CNT + 1] << 8\n-\t\t\t\t\t| ext_csd[EXT_CSD_SEC_CNT + 2] << 16\n-\t\t\t\t\t| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;\n-\t\t\tcapacity *= MMC_MAX_BLOCK_LEN;\n-\t\t\tif ((capacity >> 20) > 2 * 1024)\n-\t\t\t\tmmc->capacity_user = capacity;\n-\t\t}\n-\n-\t\tswitch (ext_csd[EXT_CSD_REV]) {\n-\t\tcase 1:\n-\t\t\tmmc->version = MMC_VERSION_4_1;\n-\t\t\tbreak;\n-\t\tcase 2:\n-\t\t\tmmc->version = MMC_VERSION_4_2;\n-\t\t\tbreak;\n-\t\tcase 3:\n-\t\t\tmmc->version = MMC_VERSION_4_3;\n-\t\t\tbreak;\n-\t\tcase 5:\n-\t\t\tmmc->version = MMC_VERSION_4_41;\n-\t\t\tbreak;\n-\t\tcase 6:\n-\t\t\tmmc->version = MMC_VERSION_4_5;\n-\t\t\tbreak;\n-\t\tcase 7:\n-\t\t\tmmc->version = MMC_VERSION_5_0;\n-\t\t\tbreak;\n-\t\tcase 8:\n-\t\t\tmmc->version = MMC_VERSION_5_1;\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\t/* The partition data may be non-zero but it is only\n-\t\t * effective if PARTITION_SETTING_COMPLETED is set in\n-\t\t * EXT_CSD, so ignore any data if this bit is not set,\n-\t\t * except for enabling the high-capacity group size\n-\t\t * definition (see below). */\n-\t\tpart_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &\n-\t\t\t\t EXT_CSD_PARTITION_SETTING_COMPLETED);\n-\n-\t\t/* store the partition info of emmc */\n-\t\tmmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];\n-\t\tif ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||\n-\t\t ext_csd[EXT_CSD_BOOT_MULT])\n-\t\t\tmmc->part_config = ext_csd[EXT_CSD_PART_CONF];\n-\t\tif (part_completed &&\n-\t\t (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))\n-\t\t\tmmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];\n-\n-\t\tmmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;\n-\n-\t\tmmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;\n-\n-\t\tfor (i = 0; i < 4; i++) {\n-\t\t\tint idx = EXT_CSD_GP_SIZE_MULT + i * 3;\n-\t\t\tuint mult = (ext_csd[idx + 2] << 16) +\n-\t\t\t\t(ext_csd[idx + 1] << 8) + ext_csd[idx];\n-\t\t\tif (mult)\n-\t\t\t\thas_parts = true;\n-\t\t\tif (!part_completed)\n-\t\t\t\tcontinue;\n-\t\t\tmmc->capacity_gp[i] = mult;\n-\t\t\tmmc->capacity_gp[i] *=\n-\t\t\t\text_csd[EXT_CSD_HC_ERASE_GRP_SIZE];\n-\t\t\tmmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];\n-\t\t\tmmc->capacity_gp[i] <<= 19;\n-\t\t}\n-\n-\t\tif (part_completed) {\n-\t\t\tmmc->enh_user_size =\n-\t\t\t\t(ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +\n-\t\t\t\t(ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +\n-\t\t\t\text_csd[EXT_CSD_ENH_SIZE_MULT];\n-\t\t\tmmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];\n-\t\t\tmmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];\n-\t\t\tmmc->enh_user_size <<= 19;\n-\t\t\tmmc->enh_user_start =\n-\t\t\t\t(ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +\n-\t\t\t\t(ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +\n-\t\t\t\t(ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +\n-\t\t\t\text_csd[EXT_CSD_ENH_START_ADDR];\n-\t\t\tif (mmc->high_capacity)\n-\t\t\t\tmmc->enh_user_start <<= 9;\n-\t\t}\n-\n-\t\t/*\n-\t\t * Host needs to enable ERASE_GRP_DEF bit if device is\n-\t\t * partitioned. This bit will be lost every time after a reset\n-\t\t * or power off. This will affect erase size.\n-\t\t */\n-\t\tif (part_completed)\n-\t\t\thas_parts = true;\n-\t\tif ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&\n-\t\t (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))\n-\t\t\thas_parts = true;\n-\t\tif (has_parts) {\n-\t\t\terr = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,\n-\t\t\t\tEXT_CSD_ERASE_GROUP_DEF, 1);\n \n-\t\t\tif (err)\n-\t\t\t\treturn err;\n-\t\t\telse\n-\t\t\t\text_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;\n-\t\t}\n-\n-\t\tif (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {\n-\t\t\t/* Read out group size from ext_csd */\n-\t\t\tmmc->erase_grp_size =\n-\t\t\t\text_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;\n-\t\t\t/*\n-\t\t\t * if high capacity and partition setting completed\n-\t\t\t * SEC_COUNT is valid even if it is smaller than 2 GiB\n-\t\t\t * JEDEC Standard JESD84-B45, 6.2.4\n-\t\t\t */\n-\t\t\tif (mmc->high_capacity && part_completed) {\n-\t\t\t\tcapacity = (ext_csd[EXT_CSD_SEC_CNT]) |\n-\t\t\t\t\t(ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |\n-\t\t\t\t\t(ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |\n-\t\t\t\t\t(ext_csd[EXT_CSD_SEC_CNT + 3] << 24);\n-\t\t\t\tcapacity *= MMC_MAX_BLOCK_LEN;\n-\t\t\t\tmmc->capacity_user = capacity;\n-\t\t\t}\n-\t\t} else {\n-\t\t\t/* Calculate the group size from the csd value. */\n-\t\t\tint erase_gsz, erase_gmul;\n-\t\t\terase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;\n-\t\t\terase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;\n-\t\t\tmmc->erase_grp_size = (erase_gsz + 1)\n-\t\t\t\t* (erase_gmul + 1);\n-\t\t}\n-\n-\t\tmmc->hc_wp_grp_size = 1024\n-\t\t\t* ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]\n-\t\t\t* ext_csd[EXT_CSD_HC_WP_GRP_SIZE];\n-\n-\t\tmmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];\n-\t}\n+\terr = mmc_startup_v4(mmc, ext_csd);\n+\tif (err)\n+\t\treturn err;\n \n \terr = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);\n \tif (err)\n", "prefixes": [ "U-Boot", "v2", "03/26" ] }