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GET /api/patches/816884/?format=api
{ "id": 816884, "url": "http://patchwork.ozlabs.org/api/patches/816884/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506003471-34551-2-git-send-email-david.wu@rock-chips.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506003471-34551-2-git-send-email-david.wu@rock-chips.com>", "list_archive_url": null, "date": "2017-09-21T14:17:46", "name": "[U-Boot,1/6] rockchip: clk: Add mac clock set for rk3399", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "b0cff4a5258655a7298638f7e4af57cb998b8066", "submitter": { "id": 68083, "url": "http://patchwork.ozlabs.org/api/people/68083/?format=api", "name": "David Wu", "email": "david.wu@rock-chips.com" }, "delegate": { "id": 69486, "url": "http://patchwork.ozlabs.org/api/users/69486/?format=api", "username": "ptomsich", "first_name": "Philipp", "last_name": "Tomsich", "email": "philipp.tomsich@theobroma-systems.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506003471-34551-2-git-send-email-david.wu@rock-chips.com/mbox/", "series": [ { "id": 4397, "url": "http://patchwork.ozlabs.org/api/series/4397/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4397", "date": "2017-09-21T14:17:45", "name": "Add gmac support for rk3399-evb and rv1108-evb", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4397/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816884/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816884/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xydzH63Ctz9s06\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 00:19:39 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 8F052C21E40; Thu, 21 Sep 2017 14:19:13 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 9310DC21ED3;\n\tThu, 21 Sep 2017 14:19:02 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 3F689C21DE7; Thu, 21 Sep 2017 14:18:58 +0000 (UTC)", "from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.135])\n\tby lists.denx.de (Postfix) with ESMTPS id C02E7C21E48\n\tfor <u-boot@lists.denx.de>; Thu, 21 Sep 2017 14:18:54 +0000 (UTC)", "from david.wu?rock-chips.com (unknown [192.168.167.78])\n\tby lucky1.263xmail.com (Postfix) with ESMTP id 3FD331010;\n\tThu, 21 Sep 2017 22:18:51 +0800 (CST)", "from localhost.localdomain (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 0B1E03DA;\n\tThu, 21 Sep 2017 22:18:50 +0800 (CST)", "from unknown (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith SMTP id 13122TND0V8;\n\tThu, 21 Sep 2017 22:18:52 +0800 (CST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "**", "X-Spam-Status": "No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL,\n\tRCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no\n\tversion=3.4.0", "X-263anti-spam": "KSV:0;", "X-MAIL-GRAY": "1", "X-MAIL-DELIVERY": "0", "X-KSVirus-check": "0", "X-ABS-CHECKED": "4", "X-RL-SENDER": "david.wu@rock-chips.com", "X-FST-TO": "philipp.tomsich@theobroma-systems.com", "X-SENDER-IP": "58.22.7.114", "X-LOGIN-NAME": "david.wu@rock-chips.com", "X-UNIQUE-TAG": "<d521493bd4724be59d1ac89713681a9c>", "X-ATTACHMENT-NUM": "0", "X-SENDER": "wdc@rock-chips.com", "X-DNS-TYPE": "0", "From": "David Wu <david.wu@rock-chips.com>", "To": "philipp.tomsich@theobroma-systems.com,\n\tsjg@chromium.org", "Date": "Thu, 21 Sep 2017 22:17:46 +0800", "Message-Id": "<1506003471-34551-2-git-send-email-david.wu@rock-chips.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506003471-34551-1-git-send-email-david.wu@rock-chips.com>", "References": "<1506003471-34551-1-git-send-email-david.wu@rock-chips.com>", "Cc": "huangtao@rock-chips.com, u-boot@lists.denx.de,\n\tDavid Wu <david.wu@rock-chips.com>, andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com", "Subject": "[U-Boot] [PATCH 1/6] rockchip: clk: Add mac clock set for rk3399", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Assuming mac_clk is fed by an external clock, set clk_rmii_src\nclock select control register from IO for rgmii interface.\n\nSigned-off-by: David Wu <david.wu@rock-chips.com>\n---\n\n drivers/clk/rockchip/clk_rk3399.c | 21 +++++++++++++++++++--\n 1 file changed, 19 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c\nindex 105c499..03d7518 100644\n--- a/drivers/clk/rockchip/clk_rk3399.c\n+++ b/drivers/clk/rockchip/clk_rk3399.c\n@@ -143,6 +143,14 @@ enum {\n \tACLK_PERIHP_DIV_CON_SHIFT\t= 0,\n \tACLK_PERIHP_DIV_CON_MASK\t= 0x1f,\n \n+\t/* CLKSEL_CON19 */\n+\tMAC_DIV_CON_SHIFT\t\t= 8,\n+\tMAC_DIV_CON_MASK\t\t= GENMASK(10, 8),\n+\tRMII_EXTCLK_SHIFT\t\t= 4,\n+\tRMII_EXTCLK_MASK\t\t= BIT(4),\n+\tRMII_EXTCLK_SELECT_INT_DIV_CLK\t= 0,\n+\tRMII_EXTCLK_SELECT_EXT_CLK\t= BIT(4),\n+\n \t/* CLKSEL_CON21 */\n \tACLK_EMMC_PLL_SEL_SHIFT = 7,\n \tACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,\n@@ -863,6 +871,16 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,\n \treturn set_rate;\n }\n \n+static int rockchip_mac_set_clk(struct rk3399_cru *cru,\n+\t\t\t\tint periph, uint freq)\n+{\n+\t/* Assuming mac_clk is fed by an external clock */\n+\trk_clrsetreg(&cru->clksel_con[19], RMII_EXTCLK_MASK,\n+\t\t RMII_EXTCLK_SELECT_EXT_CLK);\n+\n+\treturn 0;\n+}\n+\n static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)\n {\n \tu32 div, val;\n@@ -947,8 +965,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)\n \t\tret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);\n \t\tbreak;\n \tcase SCLK_MAC:\n-\t\t/* nothing to do, as this is an external clock */\n-\t\tret = rate;\n+\t\tret = rockchip_mac_set_clk(priv->cru, clk->id, rate);\n \t\tbreak;\n \tcase SCLK_I2C1:\n \tcase SCLK_I2C2:\n", "prefixes": [ "U-Boot", "1/6" ] }