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GET /api/patches/816817/?format=api
{ "id": 816817, "url": "http://patchwork.ozlabs.org/api/patches/816817/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/1505992913-107256-8-git-send-email-linyunsheng@huawei.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505992913-107256-8-git-send-email-linyunsheng@huawei.com>", "list_archive_url": null, "date": "2017-09-21T11:21:50", "name": "[net-next,07/10] net: hns3: Add hclge_dcb module for the support of DCB feature", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "514c54654f058df2950e13c63c5d6a1036876192", "submitter": { "id": 71804, "url": "http://patchwork.ozlabs.org/api/people/71804/?format=api", "name": "Yunsheng Lin", "email": "linyunsheng@huawei.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/1505992913-107256-8-git-send-email-linyunsheng@huawei.com/mbox/", "series": [ { "id": 4360, "url": "http://patchwork.ozlabs.org/api/series/4360/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=4360", "date": "2017-09-21T11:21:52", "name": "Add support for DCB feature in hns3 driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4360/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816817/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816817/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyZ6C2Yk7z9t3w\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 21 Sep 2017 21:25:23 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752022AbdIULZH (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tThu, 21 Sep 2017 07:25:07 -0400", "from szxga04-in.huawei.com ([45.249.212.190]:6954 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751786AbdIULWV (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Thu, 21 Sep 2017 07:22:21 -0400", "from 172.30.72.60 (EHLO DGGEMS408-HUB.china.huawei.com)\n\t([172.30.72.60])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DHR44635; Thu, 21 Sep 2017 19:22:19 +0800 (CST)", "from localhost.localdomain (10.67.212.75) by\n\tDGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP\n\tServer id 14.3.301.0; Thu, 21 Sep 2017 19:22:10 +0800" ], "From": "Yunsheng Lin <linyunsheng@huawei.com>", "To": "<davem@davemloft.net>", "CC": "<huangdaode@hisilicon.com>, <xuwei5@hisilicon.com>,\n\t<liguozhu@hisilicon.com>, <Yisen.Zhuang@huawei.com>,\n\t<gabriele.paoloni@huawei.com>, <john.garry@huawei.com>,\n\t<linuxarm@huawei.com>, <yisen.zhuang@huawei.com>,\n\t<salil.mehta@huawei.com>, <lipeng321@huawei.com>,\n\t<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>", "Subject": "[PATCH net-next 07/10] net: hns3: Add hclge_dcb module for the\n\tsupport of DCB feature", "Date": "Thu, 21 Sep 2017 19:21:50 +0800", "Message-ID": "<1505992913-107256-8-git-send-email-linyunsheng@huawei.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1505992913-107256-1-git-send-email-linyunsheng@huawei.com>", "References": "<1505992913-107256-1-git-send-email-linyunsheng@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.212.75]", "X-CFilter-Loop": "Reflected", "X-Mirapoint-Virus-RAPID-Raw": "score=unknown(0),\n\trefid=str=0001.0A090205.59C3A0EB.0183, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32", "X-Mirapoint-Loop-Id": "7173570510d10a87e22776e6c1ffc523", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "The hclge_dcb module calls the interface from hclge_main/tm\nand provide interface for the dcb netlink interface.\n\nThis patch also update Makefiles required to build the DCB\nsupported code in HNS3 Ethernet driver and update the existing\nKconfig file in the hisilicon folder.\n\nSigned-off-by: Yunsheng Lin <linyunsheng@huawei.com>\n---\n drivers/net/ethernet/hisilicon/Kconfig | 9 +\n drivers/net/ethernet/hisilicon/hns3/hnae3.h | 20 ++\n .../net/ethernet/hisilicon/hns3/hns3pf/Makefile | 2 +\n .../net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c | 327 +++++++++++++++++++++\n .../net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h | 21 ++\n .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 25 +-\n .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 3 +\n 7 files changed, 401 insertions(+), 6 deletions(-)\n create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c\n create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h", "diff": "diff --git a/drivers/net/ethernet/hisilicon/Kconfig b/drivers/net/ethernet/hisilicon/Kconfig\nindex 91c7bdb..9d7cb03 100644\n--- a/drivers/net/ethernet/hisilicon/Kconfig\n+++ b/drivers/net/ethernet/hisilicon/Kconfig\n@@ -103,4 +103,13 @@ config HNS3_ENET\n \t family of SoCs. This module depends upon HNAE3 driver to access the HNAE3\n \t devices and their associated operations.\n \n+config HNS3_DCB\n+\tbool \"Hisilicon HNS3 Data Center Bridge Support\"\n+\tdefault n\n+\tdepends on HNS3 && HNS3_HCLGE && DCB\n+\t---help---\n+\t Say Y here if you want to use Data Center Bridging (DCB) in the HNS3 driver.\n+\n+\t If unsure, say N.\n+\n endif # NET_VENDOR_HISILICON\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h\nindex 1a01cad..5a6fa53 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h\n@@ -28,6 +28,7 @@\n */\n \n #include <linux/acpi.h>\n+#include <linux/dcbnl.h>\n #include <linux/delay.h>\n #include <linux/device.h>\n #include <linux/module.h>\n@@ -131,6 +132,7 @@ struct hnae3_client_ops {\n \tint (*init_instance)(struct hnae3_handle *handle);\n \tvoid (*uninit_instance)(struct hnae3_handle *handle, bool reset);\n \tvoid (*link_status_change)(struct hnae3_handle *handle, bool state);\n+\tint (*setup_tc)(struct hnae3_handle *handle, u8 tc);\n };\n \n #define HNAE3_CLIENT_NAME_LENGTH 16\n@@ -363,6 +365,23 @@ struct hnae3_ae_ops {\n \t\t\t\t u16 vlan, u8 qos, __be16 proto);\n };\n \n+struct hnae3_dcb_ops {\n+\t/* IEEE 802.1Qaz std */\n+\tint (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);\n+\tint (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);\n+\tint (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);\n+\tint (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);\n+\n+\t/* DCBX configuration */\n+\tu8 (*getdcbx)(struct hnae3_handle *);\n+\tu8 (*setdcbx)(struct hnae3_handle *, u8);\n+\n+\t/* TC setup */\n+\tint (*setup_tc)(struct hnae3_handle *, u8, u8 *);\n+\n+\tint (*map_update)(struct hnae3_handle *);\n+};\n+\n struct hnae3_ae_algo {\n \tconst struct hnae3_ae_ops *ops;\n \tstruct list_head node;\n@@ -394,6 +413,7 @@ struct hnae3_knic_private_info {\n \n \tu16 num_tqps;\t\t /* total number of TQPs in this handle */\n \tstruct hnae3_queue **tqp; /* array base of all TQPs in this instance */\n+\tconst struct hnae3_dcb_ops *dcb_ops;\n };\n \n struct hnae3_roce_private_info {\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile b/drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile\nindex 162e8a42..7023dc87 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile\n@@ -7,5 +7,7 @@ ccflags-y := -Idrivers/net/ethernet/hisilicon/hns3\n obj-$(CONFIG_HNS3_HCLGE) += hclge.o\n hclge-objs = hclge_main.o hclge_cmd.o hclge_mdio.o hclge_tm.o\n \n+hclge-$(CONFIG_HNS3_DCB) += hclge_dcb.o\n+\n obj-$(CONFIG_HNS3_ENET) += hns3.o\n hns3-objs = hns3_enet.o hns3_ethtool.o\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c\nnew file mode 100644\nindex 0000000..178333b\n--- /dev/null\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c\n@@ -0,0 +1,327 @@\n+/*\n+ * Copyright (c) 2016-2017 Hisilicon Limited.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#include \"hclge_main.h\"\n+#include \"hclge_tm.h\"\n+#include \"hnae3.h\"\n+\n+#define BW_PERCENT\t100\n+\n+static int hclge_ieee_ets_to_tm_info(struct hclge_dev *hdev,\n+\t\t\t\t struct ieee_ets *ets)\n+{\n+\tu8 i;\n+\n+\tfor (i = 0; i < HNAE3_MAX_TC; i++) {\n+\t\tswitch (ets->tc_tsa[i]) {\n+\t\tcase IEEE_8021QAZ_TSA_STRICT:\n+\t\t\thdev->tm_info.tc_info[i].tc_sch_mode =\n+\t\t\t\tHCLGE_SCH_MODE_SP;\n+\t\t\thdev->tm_info.pg_info[0].tc_dwrr[i] = 0;\n+\t\t\tbreak;\n+\t\tcase IEEE_8021QAZ_TSA_ETS:\n+\t\t\thdev->tm_info.tc_info[i].tc_sch_mode =\n+\t\t\t\tHCLGE_SCH_MODE_DWRR;\n+\t\t\thdev->tm_info.pg_info[0].tc_dwrr[i] =\n+\t\t\t\tets->tc_tx_bw[i];\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Hardware only supports SP (strict priority)\n+\t\t\t * or ETS (enhanced transmission selection)\n+\t\t\t * algorithms, if we receive some other value\n+\t\t\t * from dcbnl, then throw an error.\n+\t\t\t */\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn hclge_tm_prio_tc_info_update(hdev, ets->prio_tc);\n+}\n+\n+static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev,\n+\t\t\t\t struct ieee_ets *ets)\n+{\n+\tu32 i;\n+\n+\tmemset(ets, 0, sizeof(*ets));\n+\tets->willing = 1;\n+\tets->ets_cap = hdev->tc_max;\n+\n+\tfor (i = 0; i < HNAE3_MAX_TC; i++) {\n+\t\tets->prio_tc[i] = hdev->tm_info.prio_tc[i];\n+\t\tets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i];\n+\n+\t\tif (hdev->tm_info.tc_info[i].tc_sch_mode ==\n+\t\t HCLGE_SCH_MODE_SP)\n+\t\t\tets->tc_tsa[i] = IEEE_8021QAZ_TSA_STRICT;\n+\t\telse\n+\t\t\tets->tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;\n+\t}\n+}\n+\n+/* IEEE std */\n+static int hclge_ieee_getets(struct hnae3_handle *h, struct ieee_ets *ets)\n+{\n+\tstruct hclge_vport *vport = hclge_get_vport(h);\n+\tstruct hclge_dev *hdev = vport->back;\n+\n+\thclge_tm_info_to_ieee_ets(hdev, ets);\n+\n+\treturn 0;\n+}\n+\n+static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,\n+\t\t\t u8 *tc, bool *changed)\n+{\n+\tu32 total_ets_bw = 0;\n+\tu8 max_tc = 0;\n+\tu8 i;\n+\n+\tfor (i = 0; i < HNAE3_MAX_TC; i++) {\n+\t\tif (ets->prio_tc[i] >= hdev->tc_max ||\n+\t\t i >= hdev->tc_max)\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (ets->prio_tc[i] != hdev->tm_info.prio_tc[i])\n+\t\t\t*changed = true;\n+\n+\t\tif (ets->prio_tc[i] > max_tc)\n+\t\t\tmax_tc = ets->prio_tc[i];\n+\n+\t\tswitch (ets->tc_tsa[i]) {\n+\t\tcase IEEE_8021QAZ_TSA_STRICT:\n+\t\t\tif (hdev->tm_info.tc_info[i].tc_sch_mode !=\n+\t\t\t\tHCLGE_SCH_MODE_SP)\n+\t\t\t\t*changed = true;\n+\t\t\tbreak;\n+\t\tcase IEEE_8021QAZ_TSA_ETS:\n+\t\t\tif (hdev->tm_info.tc_info[i].tc_sch_mode !=\n+\t\t\t\tHCLGE_SCH_MODE_DWRR)\n+\t\t\t\t*changed = true;\n+\n+\t\t\ttotal_ets_bw += ets->tc_tx_bw[i];\n+\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (total_ets_bw != BW_PERCENT)\n+\t\treturn -EINVAL;\n+\n+\t*tc = max_tc + 1;\n+\tif (*tc != hdev->tm_info.num_tc)\n+\t\t*changed = true;\n+\n+\treturn 0;\n+}\n+\n+static int hclge_map_update(struct hnae3_handle *h)\n+{\n+\tstruct hclge_vport *vport = hclge_get_vport(h);\n+\tstruct hclge_dev *hdev = vport->back;\n+\tint ret;\n+\n+\tret = hclge_tm_map_cfg(hdev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = hclge_tm_schd_mode_hw(hdev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = hclge_pause_setup_hw(hdev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = hclge_buffer_alloc(hdev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn hclge_rss_init_hw(hdev);\n+}\n+\n+static int hclge_client_setup_tc(struct hclge_dev *hdev)\n+{\n+\tstruct hclge_vport *vport = hdev->vport;\n+\tstruct hnae3_client *client;\n+\tstruct hnae3_handle *handle;\n+\tint ret;\n+\tu32 i;\n+\n+\tfor (i = 0; i < hdev->num_vmdq_vport + 1; i++) {\n+\t\thandle = &vport[i].nic;\n+\t\tclient = handle->client;\n+\n+\t\tif (!client || !client->ops || !client->ops->setup_tc)\n+\t\t\tcontinue;\n+\n+\t\tret = client->ops->setup_tc(handle, hdev->tm_info.num_tc);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets)\n+{\n+\tstruct hclge_vport *vport = hclge_get_vport(h);\n+\tstruct hclge_dev *hdev = vport->back;\n+\tbool map_changed = false;\n+\tu8 num_tc = 0;\n+\tint ret;\n+\n+\tif (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE))\n+\t\treturn -EINVAL;\n+\n+\tret = hclge_ets_validate(hdev, ets, &num_tc, &map_changed);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\thclge_tm_schd_info_update(hdev, num_tc);\n+\n+\tret = hclge_ieee_ets_to_tm_info(hdev, ets);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (map_changed) {\n+\t\tret = hclge_client_setup_tc(hdev);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn hclge_tm_dwrr_cfg(hdev);\n+}\n+\n+static int hclge_ieee_getpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)\n+{\n+\tstruct hclge_vport *vport = hclge_get_vport(h);\n+\tstruct hclge_dev *hdev = vport->back;\n+\tu8 i, j, pfc_map, *prio_tc;\n+\n+\tmemset(pfc, 0, sizeof(*pfc));\n+\tpfc->pfc_cap = hdev->pfc_max;\n+\tprio_tc = hdev->tm_info.prio_tc;\n+\tpfc_map = hdev->tm_info.hw_pfc_map;\n+\n+\t/* Pfc setting is based on TC */\n+\tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n+\t\tfor (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {\n+\t\t\tif ((prio_tc[j] == i) && (pfc_map & BIT(i)))\n+\t\t\t\tpfc->pfc_en |= BIT(j);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)\n+{\n+\tstruct hclge_vport *vport = hclge_get_vport(h);\n+\tstruct hclge_dev *hdev = vport->back;\n+\tu8 i, j, pfc_map, *prio_tc;\n+\n+\tif (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE))\n+\t\treturn -EINVAL;\n+\n+\tprio_tc = hdev->tm_info.prio_tc;\n+\tpfc_map = 0;\n+\n+\tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n+\t\tfor (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {\n+\t\t\tif ((prio_tc[j] == i) && (pfc->pfc_en & BIT(j))) {\n+\t\t\t\tpfc_map |= BIT(i);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (pfc_map == hdev->tm_info.hw_pfc_map)\n+\t\treturn 0;\n+\n+\thdev->tm_info.hw_pfc_map = pfc_map;\n+\n+\treturn hclge_pause_setup_hw(hdev);\n+}\n+\n+/* DCBX configuration */\n+static u8 hclge_getdcbx(struct hnae3_handle *h)\n+{\n+\tstruct hclge_vport *vport = hclge_get_vport(h);\n+\tstruct hclge_dev *hdev = vport->back;\n+\n+\treturn hdev->dcbx_cap;\n+}\n+\n+static u8 hclge_setdcbx(struct hnae3_handle *h, u8 mode)\n+{\n+\tstruct hclge_vport *vport = hclge_get_vport(h);\n+\tstruct hclge_dev *hdev = vport->back;\n+\n+\t/* No support for LLD_MANAGED modes or CEE */\n+\tif ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||\n+\t (mode & DCB_CAP_DCBX_VER_CEE) ||\n+\t !(mode & DCB_CAP_DCBX_HOST))\n+\t\treturn 1;\n+\n+\thdev->dcbx_cap = mode;\n+\n+\treturn 0;\n+}\n+\n+static int hclge_setup_tc(struct hnae3_handle *h, u8 tc, u8 *prio_tc)\n+{\n+\tstruct hclge_vport *vport = hclge_get_vport(h);\n+\tstruct hclge_dev *hdev = vport->back;\n+\tint ret;\n+\n+\tif (tc > hdev->tc_max) {\n+\t\tdev_err(&hdev->pdev->dev,\n+\t\t\t\"setup tc failed, tc(%u) > tc_max(%u)\\n\",\n+\t\t\ttc, hdev->tc_max);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thclge_tm_schd_info_update(hdev, tc);\n+\n+\tret = hclge_tm_prio_tc_info_update(hdev, prio_tc);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn hclge_tm_init_hw(hdev);\n+}\n+\n+static const struct hnae3_dcb_ops hns3_dcb_ops = {\n+\t.ieee_getets\t= hclge_ieee_getets,\n+\t.ieee_setets\t= hclge_ieee_setets,\n+\t.ieee_getpfc\t= hclge_ieee_getpfc,\n+\t.ieee_setpfc\t= hclge_ieee_setpfc,\n+\t.getdcbx\t= hclge_getdcbx,\n+\t.setdcbx\t= hclge_setdcbx,\n+\t.setup_tc\t= hclge_setup_tc,\n+\t.map_update\t= hclge_map_update,\n+};\n+\n+void hclge_dcb_ops_set(struct hclge_dev *hdev)\n+{\n+\tstruct hclge_vport *vport = hdev->vport;\n+\tstruct hnae3_knic_private_info *kinfo;\n+\n+\t/* Hdev does not support DCB or vport is\n+\t * not a pf, then dcb_ops is not set.\n+\t */\n+\tif (!hnae3_dev_dcb_supported(hdev) ||\n+\t vport->vport_id != 0)\n+\t\treturn;\n+\n+\tkinfo = &vport->nic.kinfo;\n+\tkinfo->dcb_ops = &hns3_dcb_ops;\n+\thdev->dcbx_cap = DCB_CAP_DCBX_VER_IEEE | DCB_CAP_DCBX_HOST;\n+}\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h\nnew file mode 100644\nindex 0000000..7d808ee\n--- /dev/null\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h\n@@ -0,0 +1,21 @@\n+/*\n+ * Copyright (c) 2016~2017 Hisilicon Limited.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#ifndef __HCLGE_DCB_H__\n+#define __HCLGE_DCB_H__\n+\n+#include \"hclge_main.h\"\n+\n+#ifdef CONFIG_HNS3_DCB\n+void hclge_dcb_ops_set(struct hclge_dev *hdev);\n+#else\n+static inline void hclge_dcb_ops_set(struct hclge_dev *hdev) {}\n+#endif\n+\n+#endif /* __HCLGE_DCB_H__ */\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\nindex 49a11d5..28bd118 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\n@@ -19,6 +19,7 @@\n #include <linux/platform_device.h>\n \n #include \"hclge_cmd.h\"\n+#include \"hclge_dcb.h\"\n #include \"hclge_main.h\"\n #include \"hclge_mdio.h\"\n #include \"hclge_tm.h\"\n@@ -1057,7 +1058,7 @@ static int hclge_configure(struct hclge_dev *hdev)\n \thdev->hw.mac.phy_addr = cfg.phy_addr;\n \thdev->num_desc = cfg.tqp_desc_num;\n \thdev->tm_info.num_pg = 1;\n-\thdev->tm_info.num_tc = cfg.tc_num;\n+\thdev->tc_max = cfg.tc_num;\n \thdev->tm_info.hw_pfc_map = 0;\n \n \tret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);\n@@ -1066,15 +1067,25 @@ static int hclge_configure(struct hclge_dev *hdev)\n \t\treturn ret;\n \t}\n \n-\tif ((hdev->tm_info.num_tc > HNAE3_MAX_TC) ||\n-\t (hdev->tm_info.num_tc < 1)) {\n+\tif ((hdev->tc_max > HNAE3_MAX_TC) ||\n+\t (hdev->tc_max < 1)) {\n \t\tdev_warn(&hdev->pdev->dev, \"TC num = %d.\\n\",\n-\t\t\t hdev->tm_info.num_tc);\n-\t\thdev->tm_info.num_tc = 1;\n+\t\t\t hdev->tc_max);\n+\t\thdev->tc_max = 1;\n \t}\n \n+\t/* Dev does not support DCB */\n+\tif (!hnae3_dev_dcb_supported(hdev)) {\n+\t\thdev->tc_max = 1;\n+\t\thdev->pfc_max = 0;\n+\t} else {\n+\t\thdev->pfc_max = hdev->tc_max;\n+\t}\n+\n+\thdev->tm_info.num_tc = hdev->tc_max;\n+\n \t/* Currently not support uncontiuous tc */\n-\tfor (i = 0; i < cfg.tc_num; i++)\n+\tfor (i = 0; i < hdev->tm_info.num_tc; i++)\n \t\thnae_set_bit(hdev->hw_tc_map, i, 1);\n \n \tif (!hdev->num_vmdq_vport && !hdev->num_req_vfs)\n@@ -4242,6 +4253,8 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)\n \t\treturn ret;\n \t}\n \n+\thclge_dcb_ops_set(hdev);\n+\n \tsetup_timer(&hdev->service_timer, hclge_service_timer,\n \t\t (unsigned long)hdev);\n \tINIT_WORK(&hdev->service_task, hclge_service_task);\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h\nindex 394b587..7c66c00 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h\n@@ -421,8 +421,11 @@ struct hclge_dev {\n #define HCLGE_FLAG_TC_BASE_SCH_MODE\t\t1\n #define HCLGE_FLAG_VNET_BASE_SCH_MODE\t\t2\n \tu8 tx_sch_mode;\n+\tu8 tc_max;\n+\tu8 pfc_max;\n \n \tu8 default_up;\n+\tu8 dcbx_cap;\n \tstruct hclge_tm_info tm_info;\n \n \tu16 num_msi;\n", "prefixes": [ "net-next", "07/10" ] }