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GET /api/patches/816686/?format=api
{ "id": 816686, "url": "http://patchwork.ozlabs.org/api/patches/816686/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170921062911.26724-6-anarsoul@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170921062911.26724-6-anarsoul@gmail.com>", "list_archive_url": null, "date": "2017-09-21T06:29:11", "name": "[U-Boot,v2,5/5] sunxi: video: add LCD support to DE2 driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "bdf72e614b21021fff39212f123e95f6c7cf28af", "submitter": { "id": 6930, "url": "http://patchwork.ozlabs.org/api/people/6930/?format=api", "name": "Vasily Khoruzhick", "email": "anarsoul@gmail.com" }, "delegate": { "id": 1700, "url": "http://patchwork.ozlabs.org/api/users/1700/?format=api", "username": "ag", "first_name": "Anatolij", "last_name": "Gustschin", "email": "agust@denx.de" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170921062911.26724-6-anarsoul@gmail.com/mbox/", "series": [ { "id": 4307, "url": "http://patchwork.ozlabs.org/api/series/4307/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4307", "date": "2017-09-21T06:29:06", "name": "sunxi: video: add DE2 LCD and ANX6345 drivers", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/4307/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816686/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816686/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"U0BkC3GR\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyRbn4QqDz9t3m\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 21 Sep 2017 16:32:05 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 68088C21EB4; Thu, 21 Sep 2017 06:31:16 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 51D06C21E23;\n\tThu, 21 Sep 2017 06:29:34 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 1F060C21F14; Thu, 21 Sep 2017 06:29:25 +0000 (UTC)", "from mail-pg0-f65.google.com (mail-pg0-f65.google.com\n\t[74.125.83.65])\n\tby lists.denx.de (Postfix) with ESMTPS id 2892CC21EB4\n\tfor <u-boot@lists.denx.de>; Thu, 21 Sep 2017 06:29:22 +0000 (UTC)", "by mail-pg0-f65.google.com with SMTP id d8so2931506pgt.3\n\tfor <u-boot@lists.denx.de>; Wed, 20 Sep 2017 23:29:22 -0700 (PDT)", "from anarsoul-thinkpad.lan (216-71-193-140.dyn.novuscom.net.\n\t[216.71.193.140]) by smtp.gmail.com with ESMTPSA id\n\tf24sm1157511pfk.137.2017.09.20.23.29.19\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 20 Sep 2017 23:29:20 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=1N3gcRHAEwyCtM6C4Kx8ts4FWADdCkmPL4vcIvQEmNI=;\n\tb=U0BkC3GRWmNlJhEQrNpQ7qh4oItjeWZZgbRGuUOmy+7PgYyaNN0vNt2BMjbj+7TQIO\n\to7g8AywcT7/4OPciZ9qSi62vi9VbXaVIrO2dwyCQGrWmP4bsR8U3mq2dhDd/iZbIob/O\n\t5EV6jKyZVrvRFjsClUbtXUqgQbr5fUkkwFOx1CgH/CUAPax9VXfVg1k58fz3xjhd/SXG\n\tvRmYrEJOtiGcUIzxe8L4z6W86yONfRkZH+uZpi0J3DMyJEbQsHxN+tZ7clLmjJc6wFtf\n\txezzKzrzZCRWlYvR3edTmVrdp6sZxfpVj0ZygJbjTi/gUwM3pifo7wtOGSmJah+Se3hy\n\tXKhg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=1N3gcRHAEwyCtM6C4Kx8ts4FWADdCkmPL4vcIvQEmNI=;\n\tb=KBYyGegQDRkFNOnccnKrnwCwBz0lD92fiA7t8JE2xD9jBnFKVdvZ3u6cV2b2MJH55W\n\twMQZDmt8xZ5fqpzswu/Mcqi96IHDfnPJHvM4i5n60ei3HeUZ/gmoKB0L+hdaipsHUJoi\n\tNXZ4Yosa6sJ06u7KGaiM1J2SZsos9k3awhyaODbSu04zbgbslvMWo/AEqdcXze1D1wtV\n\tnDVo0W1FmzVa3pnm9ip0xqO02Hel0IXi6FPp4isMcdr71XUjVwUIr86+N+7rIPONkWmh\n\t8fgH7IfyNpG/kVXs0MwkbbDVGQ1GB2qUmjJ79b6pL95OsQkqgraK+JIAiVSgRapX/h/w\n\tzp3g==", "X-Gm-Message-State": "AHPjjUjTBDSmB/Dm/Jyrf9f82Rl62pN7Tey/IYPE79bDj8Tmo2ULLFTj\n\tvMH80BVwkzXECB1VEd8hwuM=", "X-Google-Smtp-Source": "AOwi7QAg1+0zrUEuVpHBxfbCff92jG3MP51C2xey6lzDs0jMdE+2zImr9yOYgYNvYiqPnj+9DB8PWQ==", "X-Received": "by 10.99.121.135 with SMTP id u129mr4744132pgc.260.1505975360780;\n\tWed, 20 Sep 2017 23:29:20 -0700 (PDT)", "From": "Vasily Khoruzhick <anarsoul@gmail.com>", "To": "Jagan Teki <jagan@openedev.com>,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>,\n\tAnatolij Gustschin <agust@denx.de>,\n\tJernej Skrabec <jernej.skrabec@siol.net>, icenowy@aosc.io,\n\tu-boot@lists.denx.de", "Date": "Wed, 20 Sep 2017 23:29:11 -0700", "Message-Id": "<20170921062911.26724-6-anarsoul@gmail.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170921062911.26724-1-anarsoul@gmail.com>", "References": "<20170921062911.26724-1-anarsoul@gmail.com>", "Subject": "[U-Boot] [PATCH v2 5/5] sunxi: video: add LCD support to DE2 driver", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Extend DE2 driver with LCD support. Tested on Pinebook which is based\non A64 and has ANX6345 eDP bridge with eDP panel connected to it.\n\nSigned-off-by: Vasily Khoruzhick <anarsoul@gmail.com>\n---\nv2: - drop redundant clock_set_pll10() call\n - fallback to timings from DT if reading EDID from bridge failed\n - read panel_bpp from DT\n\n arch/arm/mach-sunxi/Kconfig | 2 +-\n drivers/video/sunxi/Makefile | 2 +-\n drivers/video/sunxi/sunxi_de2.c | 17 +++++\n drivers/video/sunxi/sunxi_lcd.c | 149 ++++++++++++++++++++++++++++++++++++++++\n 4 files changed, 168 insertions(+), 2 deletions(-)\n create mode 100644 drivers/video/sunxi/sunxi_lcd.c", "diff": "diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig\nindex 2309f59999..06d697e3a7 100644\n--- a/arch/arm/mach-sunxi/Kconfig\n+++ b/arch/arm/mach-sunxi/Kconfig\n@@ -680,7 +680,7 @@ config VIDEO_LCD_MODE\n \n config VIDEO_LCD_DCLK_PHASE\n \tint \"LCD panel display clock phase\"\n-\tdepends on VIDEO\n+\tdepends on VIDEO || DM_VIDEO\n \tdefault 1\n \t---help---\n \tSelect LCD panel display clock phase shift, range 0-3.\ndiff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile\nindex 0d64c2021f..8c91766c24 100644\n--- a/drivers/video/sunxi/Makefile\n+++ b/drivers/video/sunxi/Makefile\n@@ -6,4 +6,4 @@\n #\n \n obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o ../videomodes.o\n-obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o\n+obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o sunxi_lcd.o\ndiff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c\nindex ee67764ac5..a838bbacd1 100644\n--- a/drivers/video/sunxi/sunxi_de2.c\n+++ b/drivers/video/sunxi/sunxi_de2.c\n@@ -232,6 +232,23 @@ static int sunxi_de2_probe(struct udevice *dev)\n \tif (!(gd->flags & GD_FLG_RELOC))\n \t\treturn 0;\n \n+\tret = uclass_find_device_by_name(UCLASS_DISPLAY,\n+\t\t\t\t\t \"sunxi_lcd\", &disp);\n+\tif (!ret) {\n+\t\tint mux;\n+\n+\t\tmux = 0;\n+\n+\t\tret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,\n+\t\t false);\n+\t\tif (!ret) {\n+\t\t\tvideo_set_flush_dcache(dev, 1);\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\tdebug(\"%s: lcd display not found (ret=%d)\\n\", __func__, ret);\n+\n \tret = uclass_find_device_by_name(UCLASS_DISPLAY,\n \t\t\t\t\t \"sunxi_dw_hdmi\", &disp);\n \tif (!ret) {\ndiff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c\nnew file mode 100644\nindex 0000000000..b8e4b0e344\n--- /dev/null\n+++ b/drivers/video/sunxi/sunxi_lcd.c\n@@ -0,0 +1,149 @@\n+/*\n+ * Allwinner LCD driver\n+ *\n+ * (C) Copyright 2017 Vasily Khoruzhick <anarsoul@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <display.h>\n+#include <video_bridge.h>\n+#include <backlight.h>\n+#include <dm.h>\n+#include <edid.h>\n+#include <asm/io.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/lcdc.h>\n+#include <asm/arch/gpio.h>\n+#include <asm/gpio.h>\n+\n+struct sunxi_lcd_priv {\n+\tstruct display_timing timing;\n+\tint panel_bpp;\n+};\n+\n+static void sunxi_lcdc_config_pinmux(void)\n+{\n+#ifdef CONFIG_MACH_SUN50I\n+\tint pin;\n+\tfor (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {\n+\t\tsunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);\n+\t\tsunxi_gpio_set_drv(pin, 3);\n+\t}\n+#endif\n+}\n+\n+static int sunxi_lcd_enable(struct udevice *dev, int bpp,\n+ const struct display_timing *edid)\n+{\n+\tstruct sunxi_ccm_reg * const ccm =\n+\t (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;\n+\tstruct sunxi_lcdc_reg * const lcdc =\n+\t (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;\n+\tstruct sunxi_lcd_priv *priv = dev_get_priv(dev);\n+\tstruct udevice *backlight;\n+\tint clk_div, clk_double, ret;\n+\n+\t/* Reset off */\n+\tsetbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);\n+\t/* Clock on */\n+\tsetbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);\n+\n+\tlcdc_init(lcdc);\n+\tsunxi_lcdc_config_pinmux();\n+\tlcdc_pll_set(ccm, 0, edid->pixelclock.typ / 1000,\n+\t &clk_div, &clk_double);\n+\tlcdc_tcon0_mode_set(lcdc, edid, clk_div, false,\n+\t priv->panel_bpp, CONFIG_VIDEO_LCD_DCLK_PHASE);\n+\tlcdc_enable(lcdc, priv->panel_bpp);\n+\n+\tret = uclass_get_device(UCLASS_PANEL_BACKLIGHT, 0, &backlight);\n+\tif (!ret)\n+\t\tbacklight_enable(backlight);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_lcd_read_timing(struct udevice *dev,\n+ struct display_timing *timing)\n+{\n+\tstruct sunxi_lcd_priv *priv = dev_get_priv(dev);\n+\tmemcpy(timing, &priv->timing, sizeof(struct display_timing));\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_lcd_probe(struct udevice *dev)\n+{\n+\tstruct udevice *cdev;\n+\tstruct sunxi_lcd_priv *priv = dev_get_priv(dev);\n+\tint ret;\n+\tint node, timing_node, val;\n+\n+#ifdef CONFIG_VIDEO_BRIDGE\n+\t/* Try to get timings from bridge first */\n+\tret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &cdev);\n+\tif (!ret) {\n+\t\tu8 edid[EDID_SIZE];\n+\t\tint channel_bpp;\n+\n+\t\tret = video_bridge_attach(cdev);\n+\t\tif (ret) {\n+\t\t\tdebug(\"video bridge attach failed: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tret = video_bridge_read_edid(cdev, edid, EDID_SIZE);\n+\t\tif (ret > 0) {\n+\t\t\tret = edid_get_timing(edid, ret, &priv->timing, &channel_bpp);\n+\t\t\tpriv->panel_bpp = channel_bpp * 3;\n+\t\t\tif (!ret)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t}\n+#endif\n+\n+\t/* Fallback to timings from DT if there's no bridge or\n+\t * if reading EDID failed\n+\t */\n+\tret = uclass_get_device(UCLASS_PANEL, 0, &cdev);\n+\tif (ret) {\n+\t\tdebug(\"video panel not found: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(cdev),\n+\t\t\t\t\t 0, &priv->timing)) {\n+\t\tdebug(\"%s: Failed to decode display timing\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\ttiming_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(cdev),\n+\t\t\t\t\t \"display-timings\");\n+\tnode = fdt_first_subnode(gd->fdt_blob, timing_node);\n+\tval = fdtdec_get_int(gd->fdt_blob, node, \"bits-per-pixel\", -1);\n+\tif (val != -1)\n+\t\tpriv->panel_bpp = val;\n+\telse\n+\t\tpriv->panel_bpp = 18;\n+\n+\treturn 0;\n+}\n+\n+static const struct dm_display_ops sunxi_lcd_ops = {\n+ .read_timing = sunxi_lcd_read_timing,\n+ .enable = sunxi_lcd_enable,\n+};\n+\n+U_BOOT_DRIVER(sunxi_lcd) = {\n+\t.name = \"sunxi_lcd\",\n+\t.id = UCLASS_DISPLAY,\n+\t.ops = &sunxi_lcd_ops,\n+\t.probe = sunxi_lcd_probe,\n+\t.priv_auto_alloc_size = sizeof(struct sunxi_lcd_priv),\n+};\n+\n+#ifdef CONFIG_MACH_SUN50I\n+U_BOOT_DEVICE(sunxi_lcd) = {\n+\t.name = \"sunxi_lcd\"\n+};\n+#endif\n", "prefixes": [ "U-Boot", "v2", "5/5" ] }