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GET /api/patches/816669/?format=api
{ "id": 816669, "url": "http://patchwork.ozlabs.org/api/patches/816669/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170921060704.19153-2-anarsoul@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170921060704.19153-2-anarsoul@gmail.com>", "list_archive_url": null, "date": "2017-09-21T06:07:02", "name": "[U-Boot,v2,1/3] pwm: sunxi: add support for PWM found on Allwinner A64 and H3", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "8cef1295f4530f14925d258707a797bd4ecb30f4", "submitter": { "id": 6930, "url": "http://patchwork.ozlabs.org/api/people/6930/?format=api", "name": "Vasily Khoruzhick", "email": "anarsoul@gmail.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170921060704.19153-2-anarsoul@gmail.com/mbox/", "series": [ { "id": 4301, "url": "http://patchwork.ozlabs.org/api/series/4301/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4301", "date": "2017-09-21T06:07:01", "name": "sunxi: add PWM driver for H3 and A64", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/4301/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816669/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816669/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"mwkho1qV\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyR462Hdvz9sNw\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 21 Sep 2017 16:08:06 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid BB20DC21F0C; Thu, 21 Sep 2017 06:07:36 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 8B263C21EE6;\n\tThu, 21 Sep 2017 06:07:18 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid EEFF3C21C93; Thu, 21 Sep 2017 06:07:16 +0000 (UTC)", "from mail-pg0-f65.google.com (mail-pg0-f65.google.com\n\t[74.125.83.65])\n\tby lists.denx.de (Postfix) with ESMTPS id 366FEC21DA9\n\tfor <u-boot@lists.denx.de>; Thu, 21 Sep 2017 06:07:16 +0000 (UTC)", "by mail-pg0-f65.google.com with SMTP id m30so2901922pgn.5\n\tfor <u-boot@lists.denx.de>; Wed, 20 Sep 2017 23:07:16 -0700 (PDT)", "from anarsoul-thinkpad.lan (216-71-193-140.dyn.novuscom.net.\n\t[216.71.193.140]) by smtp.gmail.com with ESMTPSA id\n\tc82sm1172404pfe.172.2017.09.20.23.07.14\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 20 Sep 2017 23:07:14 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=xfXPyaxkKpgWA/RCu6Yciu09zcJbAxSlj3AjqWCYrgA=;\n\tb=mwkho1qVto65lob5nRZK9kfO6jH7gTjGr8R4P1MFXsYL+ohIX6mTgYvtKSDm6qxMoC\n\tfvooUyf9iZrTcwo4lJvHE2ShSc90FcllGpprHnJIvOAM60zaPlKC/lXLtG+0ji9d8isD\n\t52YCnzlU9x3q10mr65mBlrW4DBEiqRAsEr0nZYMMnlHNlHRbpjpPp+lSv0NgZfNItktI\n\thg1AdB4kHW8tVL9aowAwtKBXuQvJkgv41qRdfDlM1evlW81Q/y/hu6IlwcJ80HgJ2TkU\n\t+7IUp17S2gO24b9+SInMvRdcYH/VDZba/LLl/KuKGSzIzsMp/+CJyy6aXmuCRqF0ScJN\n\trnPg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=xfXPyaxkKpgWA/RCu6Yciu09zcJbAxSlj3AjqWCYrgA=;\n\tb=gZlrrVRsc89zVWzQ7ExI9YlgO7ZiiEUiIXH2nTSUstrH/vJyV9G3bm4szS7+qJWMxP\n\tj62rDcNv2HFz4UE+NMOZKdDbmszBqC8+73SUw5HjdInfJXt6eTR7htgDIlUn8xb+TCgz\n\tViLoG1Wcy2P6Al4uHSHgeLgB+E027PBOvzKeG8EqLjx4O25MRti0JNZgouSH6AJxueJn\n\tMOf7gT4hZY83gOYSAOtL1lDTfJwrCwpt5N4zZ2IFBQ8rE96zeFPVwRUJUvmLBUSWt+8k\n\trK8iBr5Niub/RXtyomi3k3/nsFOztwKLGmIihJJbfFr6R71xiuYsmuYpA0aDli+iwcBX\n\t2bFw==", "X-Gm-Message-State": "AHPjjUjC+WrvwQ+pKirrXZCKIjhPJzRfvF0rqcdsdADqqL3GpU6prntS\n\tZXfKyGHvbLpwg+daJeMbKIY=", "X-Google-Smtp-Source": "AOwi7QBrY20tLB1NmQY6mR/fNQvRmp0t5RlHN6MuisSH3H36bwH3mvl9R04YJvy2A5Mtz8xuPYJQbg==", "X-Received": "by 10.98.102.142 with SMTP id s14mr4516274pfj.174.1505974034790; \n\tWed, 20 Sep 2017 23:07:14 -0700 (PDT)", "From": "Vasily Khoruzhick <anarsoul@gmail.com>", "To": "Jagan Teki <jagan@openedev.com>,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>,\n\tAnatolij Gustschin <agust@denx.de>,\n\tAndre Przywara <andre.przywara@arm.com>, u-boot@lists.denx.de,\n\ticenowy@aosc.io", "Date": "Wed, 20 Sep 2017 23:07:02 -0700", "Message-Id": "<20170921060704.19153-2-anarsoul@gmail.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170921060704.19153-1-anarsoul@gmail.com>", "References": "<20170921060704.19153-1-anarsoul@gmail.com>", "Subject": "[U-Boot] [PATCH v2 1/3] pwm: sunxi: add support for PWM found on\n\tAllwinner A64 and H3", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "This commit adds basic support for PWM found on Allwinner A64 and H3\nIt can be used for pwm_backlight driver (e.g. for Pinebook)\n\nSigned-off-by: Vasily Khoruzhick <anarsoul@gmail.com>\n---\nv2: - move pinmux config into enable function to make driver more friendly\n to the boards with ethernet\n - drop 'sun50i-a64-pwm' compatible string and use 'sun8i-h3-pwm' instead,\n since A64 PWM is compatible with one on H3\n\n arch/arm/include/asm/arch-sunxi/gpio.h | 1 +\n arch/arm/include/asm/arch-sunxi/pwm.h | 12 +++\n drivers/pwm/Kconfig | 7 ++\n drivers/pwm/Makefile | 1 +\n drivers/pwm/sunxi_pwm.c | 184 +++++++++++++++++++++++++++++++++\n 5 files changed, 205 insertions(+)\n create mode 100644 drivers/pwm/sunxi_pwm.c", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h\nindex 24f85206c8..7265d18099 100644\n--- a/arch/arm/include/asm/arch-sunxi/gpio.h\n+++ b/arch/arm/include/asm/arch-sunxi/gpio.h\n@@ -173,6 +173,7 @@ enum sunxi_gpio_number {\n #define SUN8I_GPD_SDC1\t\t3\n #define SUNXI_GPD_LCD0\t\t2\n #define SUNXI_GPD_LVDS0\t\t3\n+#define SUNXI_GPD_PWM\t\t2\n \n #define SUN5I_GPE_SDC2\t\t3\n #define SUN8I_GPE_TWI2\t\t3\ndiff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h\nindex 5884b5dbe7..673e0eb7b5 100644\n--- a/arch/arm/include/asm/arch-sunxi/pwm.h\n+++ b/arch/arm/include/asm/arch-sunxi/pwm.h\n@@ -11,8 +11,15 @@\n #define SUNXI_PWM_CH0_PERIOD\t\t(SUNXI_PWM_BASE + 4)\n \n #define SUNXI_PWM_CTRL_PRESCALE0(x)\t((x) & 0xf)\n+#define SUNXI_PWM_CTRL_PRESCALE0_MASK\t(0xf)\n #define SUNXI_PWM_CTRL_ENABLE0\t\t(0x5 << 4)\n #define SUNXI_PWM_CTRL_POLARITY0(x)\t((x) << 5)\n+#define SUNXI_PWM_CTRL_POLARITY0_MASK\t(1 << 5)\n+#define SUNXI_PWM_CTRL_CLK_GATE\t\t(1 << 6)\n+\n+#define SUNXI_PWM_CH0_PERIOD_MAX\t(0xffff)\n+#define SUNXI_PWM_CH0_PERIOD_PRD(x)\t((x & 0xffff) << 16)\n+#define SUNXI_PWM_CH0_PERIOD_DUTY(x)\t((x) & 0xffff)\n \n #define SUNXI_PWM_PERIOD_80PCT\t\t0x04af03c0\n \n@@ -31,4 +38,9 @@\n #define SUNXI_PWM_MUX\t\t\tSUN8I_GPH_PWM\n #endif\n \n+struct sunxi_pwm {\n+\tu32 ctrl;\n+\tu32 ch0_period;\n+};\n+\n #endif\ndiff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig\nindex e827558052..2984b79766 100644\n--- a/drivers/pwm/Kconfig\n+++ b/drivers/pwm/Kconfig\n@@ -43,3 +43,10 @@ config PWM_TEGRA\n \t four channels with a programmable period and duty cycle. Only a\n \t 32KHz clock is supported by the driver but the duty cycle is\n \t configurable.\n+\n+config PWM_SUNXI\n+\tbool \"Enable support for the Allwinner Sunxi PWM\"\n+\tdepends on DM_PWM\n+\thelp\n+\t This PWM is found on H3, A64 and other Allwinner SoCs. It supports a\n+\t programmable period and duty cycle. A 16-bit counter is used.\ndiff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile\nindex 29d59916cb..1a8f8a58bc 100644\n--- a/drivers/pwm/Makefile\n+++ b/drivers/pwm/Makefile\n@@ -17,3 +17,4 @@ obj-$(CONFIG_PWM_IMX)\t\t+= pwm-imx.o pwm-imx-util.o\n obj-$(CONFIG_PWM_ROCKCHIP)\t+= rk_pwm.o\n obj-$(CONFIG_PWM_SANDBOX)\t+= sandbox_pwm.o\n obj-$(CONFIG_PWM_TEGRA)\t\t+= tegra_pwm.o\n+obj-$(CONFIG_PWM_SUNXI)\t\t+= sunxi_pwm.o\ndiff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c\nnew file mode 100644\nindex 0000000000..cfea7d69f3\n--- /dev/null\n+++ b/drivers/pwm/sunxi_pwm.c\n@@ -0,0 +1,184 @@\n+/*\n+ * Copyright (c) 2017 Vasily Khoruzhick <anarsoul@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <div64.h>\n+#include <dm.h>\n+#include <pwm.h>\n+#include <regmap.h>\n+#include <syscon.h>\n+#include <asm/io.h>\n+#include <asm/arch/pwm.h>\n+#include <asm/arch/gpio.h>\n+#include <power/regulator.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+struct sunxi_pwm_priv {\n+\tstruct sunxi_pwm *regs;\n+\tulong freq;\n+\tbool invert;\n+\tuint32_t prescaler;\n+};\n+\n+static const uint32_t prescaler_table[] = {\n+\t120,\t/* 0000 */\n+\t180,\t/* 0001 */\n+\t240,\t/* 0010 */\n+\t360,\t/* 0011 */\n+\t480,\t/* 0100 */\n+\t0,\t/* 0101 */\n+\t0,\t/* 0110 */\n+\t0,\t/* 0111 */\n+\t12000,\t/* 1000 */\n+\t24000,\t/* 1001 */\n+\t36000,\t/* 1010 */\n+\t48000,\t/* 1011 */\n+\t72000,\t/* 1100 */\n+\t0,\t/* 1101 */\n+\t0,\t/* 1110 */\n+\t1,\t/* 1111 */\n+};\n+\n+static const uint64_t nsecs_per_sec = 1000000000L;\n+\n+static int sunxi_pwm_config_pinmux(void)\n+{\n+#ifdef CONFIG_MACH_SUN50I\n+\tsunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);\n+#endif\n+\treturn 0;\n+}\n+\n+static int sunxi_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)\n+{\n+\tstruct sunxi_pwm_priv *priv = dev_get_priv(dev);\n+\n+\tdebug(\"%s: polarity=%u\\n\", __func__, polarity);\n+\tpriv->invert = polarity;\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,\n+\t\t\t uint duty_ns)\n+{\n+\tstruct sunxi_pwm_priv *priv = dev_get_priv(dev);\n+\tstruct sunxi_pwm *regs = priv->regs;\n+\tint prescaler;\n+\tu32 v, period, duty;\n+\tuint64_t div = 0, pval = 0, scaled_freq = 0;\n+\n+\tdebug(\"%s: period_ns=%u, duty_ns=%u\\n\", __func__, period_ns, duty_ns);\n+\n+\tfor (prescaler = 0; prescaler < SUNXI_PWM_CTRL_PRESCALE0_MASK; prescaler++) {\n+\t\tif (!prescaler_table[prescaler])\n+\t\t\tcontinue;\n+\t\tdiv = priv->freq;\n+\t\tpval = prescaler_table[prescaler];\n+\t\tscaled_freq = lldiv(div, pval);\n+\t\tdiv = scaled_freq * period_ns;\n+\t\tdiv = lldiv(div, nsecs_per_sec);\n+\t\tif (div - 1 <= SUNXI_PWM_CH0_PERIOD_MAX)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (div - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {\n+\t\tdebug(\"%s: failed to find prescaler value\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tperiod = div;\n+\tdiv = scaled_freq * duty_ns;\n+\tdiv = lldiv(div, nsecs_per_sec);\n+\tduty = div;\n+\n+\tif (priv->prescaler != prescaler) {\n+\t\t/* Mask clock to update prescaler */\n+\t\tv = readl(®s->ctrl);\n+\t\tv &= ~SUNXI_PWM_CTRL_CLK_GATE;\n+\t\twritel(v, ®s->ctrl);\n+\t\tv &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;\n+\t\tv |= (priv->prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);\n+\t\twritel(v, ®s->ctrl);\n+\t\tv |= SUNXI_PWM_CTRL_CLK_GATE;\n+\t\twritel(v, ®s->ctrl);\n+\t\tpriv->prescaler = prescaler;\n+\t}\n+\n+\twritel(SUNXI_PWM_CH0_PERIOD_PRD(period) |\n+\t SUNXI_PWM_CH0_PERIOD_DUTY(duty), ®s->ch0_period);\n+\n+\tdebug(\"%s: prescaler: %d, period: %d, duty: %d\\n\", __func__, priv->prescaler,\n+\t period, duty);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)\n+{\n+\tstruct sunxi_pwm_priv *priv = dev_get_priv(dev);\n+\tstruct sunxi_pwm *regs = priv->regs;\n+\tuint32_t v;\n+\n+\tdebug(\"%s: Enable '%s'\\n\", __func__, dev->name);\n+\n+\tv = readl(®s->ctrl);\n+\tif (!enable) {\n+\t\tv &= ~SUNXI_PWM_CTRL_ENABLE0;\n+\t\twritel(v, ®s->ctrl);\n+\t\treturn 0;\n+\t}\n+\n+\tsunxi_pwm_config_pinmux();\n+\n+\tv &= ~SUNXI_PWM_CTRL_POLARITY0_MASK;\n+\tv |= priv->invert ? SUNXI_PWM_CTRL_POLARITY0(0) :\n+\t\t SUNXI_PWM_CTRL_POLARITY0(1);\n+\tv |= SUNXI_PWM_CTRL_ENABLE0;\n+\twritel(v, ®s->ctrl);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)\n+{\n+\tstruct sunxi_pwm_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->regs = (struct sunxi_pwm *)devfdt_get_addr(dev);\n+\n+\treturn 0;\n+}\n+\n+static int sunxi_pwm_probe(struct udevice *dev)\n+{\n+\tstruct sunxi_pwm_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->freq = 24000000;\n+\n+\treturn 0;\n+}\n+\n+static const struct pwm_ops sunxi_pwm_ops = {\n+\t.set_invert\t= sunxi_pwm_set_invert,\n+\t.set_config\t= sunxi_pwm_set_config,\n+\t.set_enable\t= sunxi_pwm_set_enable,\n+};\n+\n+static const struct udevice_id sunxi_pwm_ids[] = {\n+\t{ .compatible = \"allwinner,sun8i-h3-pwm\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(sunxi_pwm) = {\n+\t.name\t= \"sunxi_pwm\",\n+\t.id\t= UCLASS_PWM,\n+\t.of_match = sunxi_pwm_ids,\n+\t.ops\t= &sunxi_pwm_ops,\n+\t.ofdata_to_platdata\t= sunxi_pwm_ofdata_to_platdata,\n+\t.probe\t\t= sunxi_pwm_probe,\n+\t.priv_auto_alloc_size\t= sizeof(struct sunxi_pwm_priv),\n+};\n", "prefixes": [ "U-Boot", "v2", "1/3" ] }