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{
    "id": 816543,
    "url": "http://patchwork.ozlabs.org/api/patches/816543/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170920224621.16236-2-tony@atomide.com/",
    "project": {
        "id": 37,
        "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api",
        "name": "Devicetree Bindings",
        "link_name": "devicetree-bindings",
        "list_id": "devicetree.vger.kernel.org",
        "list_email": "devicetree@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
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    },
    "msgid": "<20170920224621.16236-2-tony@atomide.com>",
    "list_archive_url": null,
    "date": "2017-09-20T22:46:12",
    "name": "[01/10] dt-bindings: bus: Minimal TI sysc interconnect target module binding",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "51bb181c996db35f4900ddfbc33dc70eaaac85f9",
    "submitter": {
        "id": 365,
        "url": "http://patchwork.ozlabs.org/api/people/365/?format=api",
        "name": "Tony Lindgren",
        "email": "tony@atomide.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170920224621.16236-2-tony@atomide.com/mbox/",
    "series": [
        {
            "id": 4248,
            "url": "http://patchwork.ozlabs.org/api/series/4248/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4248",
            "date": "2017-09-20T22:46:11",
            "name": "Fix remaining issues to drop more omap platform data",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/4248/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/816543/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/816543/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<devicetree-owner@vger.kernel.org>",
        "X-Original-To": "incoming-dt@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org",
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        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyFH85C8pz9sPk\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 21 Sep 2017 08:47:00 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751875AbdITWq5 (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tWed, 20 Sep 2017 18:46:57 -0400",
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        ],
        "From": "Tony Lindgren <tony@atomide.com>",
        "To": "linux-omap@vger.kernel.org",
        "Cc": "linux-arm-kernel@lists.infradead.org, =?utf-8?q?Beno=C3=AEt_Cousson?=\n\t<bcousson@baylibre.com>,  devicetree@vger.kernel.org, Laurent Pinchart\n\t<laurent.pinchart@ideasonboard.com>, \n\tLiam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>, \n\tMark Rutland <mark.rutland@arm.com>, Mauro Carvalho Chehab\n\t<mchehab@kernel.org>, Nishanth Menon <nm@ti.com>, Matthijs van Duin\n\t<matthijsvanduin@gmail.com>, Paul Walmsley <paul@pwsan.com>,\n\tPeter Ujfalusi <peter.ujfalusi@ti.com>, \n\tRob Herring <robh+dt@kernel.org>, Sakari Ailus <sakari.ailus@iki.fi>, \n\tTero Kristo <t-kristo@ti.com>, Tomi Valkeinen <tomi.valkeinen@ti.com>",
        "Subject": "[PATCH 01/10] dt-bindings: bus: Minimal TI sysc interconnect target\n\tmodule binding",
        "Date": "Wed, 20 Sep 2017 15:46:12 -0700",
        "Message-Id": "<20170920224621.16236-2-tony@atomide.com>",
        "X-Mailer": "git-send-email 2.14.1",
        "In-Reply-To": "<20170920224621.16236-1-tony@atomide.com>",
        "References": "<20170920224621.16236-1-tony@atomide.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=UTF-8",
        "Content-Transfer-Encoding": "8bit",
        "Sender": "devicetree-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<devicetree.vger.kernel.org>",
        "X-Mailing-List": "devicetree@vger.kernel.org"
    },
    "content": "With the recently introduced omap clkctrl module binding, we can start\nmoving omap hwmod data to device tree and drivers from arch/arm/mach-omap2.\n\nTo start doing this, let's introduce a device tree binding for TI\nsysc interconnect target module hardware. The sysc manages module clocks,\nidlemodes and interconnect level resets. Each interconnect target module\ncan have one or more child devices connected to it.\n\nTI sysc interconnect target module hardware is independent of the\ninterconnect. It is used at least with TI L3 interconnect (Arteris NoC)\nand TI L4 interconnect (Sonics s3220).\n\nAs all the features may not be supported for a given sysc module, we\nneed to use device tree configuration for the revision of the interconnect\ntarget module.\n\nNote that the interconnect target module control registers are always\nsprinked at varying locations in the unused address space of the first\nchild device IP block. To avoid device tree reg conflicts, the sysc device\nprovides ranges for it's children.\n\nFor a non-intrusive transition from static hwmod data to using device\ntree defined TI interconnect target module binding, we can keep things\nworking with static hwmod data if device tree property \"ti,hwmods\" is\nspecified for the the interconnect target module.\n\nNote that additional properties for sysc capabilities will be added\nlater on. For now, we can already use this binding for interconnect\ntarget modules that do not have any child device drivers available.\nThis allows us to idle the unused interconnect target modules during\ninit without the need for legacy hwmod platform data for doing it.\n\nCc: Benoît Cousson <bcousson@baylibre.com>\nCc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nCc: Liam Girdwood <lgirdwood@gmail.com>\nCc: Mark Brown <broonie@kernel.org>\nCc: Mark Rutland <mark.rutland@arm.com>\nCc: Mauro Carvalho Chehab <mchehab@kernel.org>\nCc: Nishanth Menon <nm@ti.com>\nCc: Matthijs van Duin <matthijsvanduin@gmail.com>\nCc: Paul Walmsley <paul@pwsan.com>\nCc: Peter Ujfalusi <peter.ujfalusi@ti.com>\nCc: Rob Herring <robh+dt@kernel.org>\nCc: Sakari Ailus <sakari.ailus@iki.fi>\nCc: Tero Kristo <t-kristo@ti.com>\nCc: Tomi Valkeinen <tomi.valkeinen@ti.com>\nSigned-off-by: Tony Lindgren <tony@atomide.com>\n---\n Documentation/devicetree/bindings/bus/ti-sysc.txt | 88 +++++++++++++++++++++++\n 1 file changed, 88 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/bus/ti-sysc.txt",
    "diff": "diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt\nnew file mode 100644\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt\n@@ -0,0 +1,88 @@\n+Texas Instruments sysc interconnect target module wrapper binding\n+\n+Texas Instruments SoCs can have a generic interconnect target module\n+hardware for devices connected to various interconnects such as L3\n+interconnect (Arteris NoC) and L4 interconnect (Sonics s3220).\n+\n+Each interconnect target module can have one or more devices connected to\n+it. There is a set of control registers for managing interconnect target\n+module clocks, idle modes and interconnect level resets for the module.\n+\n+These control registers are sprinkled into the unused register address\n+space of the first child device IP block managed by the interconnect\n+target module and typically are named REVISION, SYSCONFIG and SYSSTATUS.\n+\n+Required standard properties:\n+\n+- compatible\tshall be one of the following generic types:\n+\n+\t\t\"ti,sysc-type1\"\n+\t\t\"ti,sysc-type2\"\n+\t\t\"ti,sysc-type3\"\n+\n+\t\tor one of the following derivative types for hardware\n+\t\tneeding special workarounds:\n+\n+\t\t\"ti,sysc-omap3430-sr\"\n+\t\t\"ti,sysc-omap3630-sr\"\n+\t\t\"ti,sysc-omap4-sr\"\n+\t\t\"ti,sysc-omap3-sham\"\n+\t\t\"ti,sysc-omap-aes\"\n+\t\t\"ti,sysc-mcasp\"\n+\t\t\"ti,sysc-usb-host-fs\"\n+\n+- reg\t\tshall have register areas implemented for the interconnect\n+\t\ttarget module in question such as revision, sysc and syss\n+\n+- reg-names\tshall contain the register names implemented for the\n+\t\tinterconnect target module in question such as\n+\t\t\"rev, \"sysc\", and \"syss\"\n+\n+- ranges\tshall contain the interconnect target module IO range\n+\t\tavailable for one or more child device IP blocks managed\n+\t\tby the interconnect target module, the ranges may include\n+\t\tmultiple ranges such as device L4 range for control and\n+\t\tparent L3 range for DMA access\n+\n+Optional properties:\n+\n+- clocks\tclock specifier for each name in the clock-names as\n+\t\tspecified in the binding documentation for ti-clkctrl,\n+\t\ttypically available for all interconnect targets on TI SoCs\n+\t\tbased on omap4 except if it's read-only register in hwauto\n+\t\tmode as for example omap4 L4_CFG_CLKCTRL\n+\n+- clock-names\tshould contain \"clkctrl\"\n+\n+- ti,hwmods\toptional TI interconnect module name to use legacy\n+\t\thwmod platform data\n+\n+\n+Example: Single instance of MUSB controller on omap4 using interconnect ranges\n+using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):\n+\n+\ttarget-module@2b000 {\t\t/* 0x4a0ab000, ap 84 12.0 */\n+\t\tcompatible = \"ti,sysc-type1\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\treg = <0x2b400 0x4>,\n+\t\t      <0x2b404 0x4>,\n+\t\t      <0x2b408 0x4>;\n+\t\treg-names = \"rev\", \"sysc\", \"syss\";\n+\t\tranges = <0 0x2b000 0x1000>;\n+\t\tclocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;\n+\t\tclock-names = \"clkctrl\";\n+\n+\t\tusb_otg_hs: otg@0 {\n+\t\t\tcompatible = \"ti,omap4-musb\";\n+\t\t\treg = <0x0 0x7ff>;\n+\t\t\tinterrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tusb-phy = <&usb2_phy>;\n+\t\t\t...\n+\t\t};\n+\t};\n+\n+Note that other SoCs, such as am335x can have multipe child devices. On am335x\n+there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA\n+instance as children of a single interconnet target module.\n",
    "prefixes": [
        "01/10"
    ]
}