Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/816533/?format=api
{ "id": 816533, "url": "http://patchwork.ozlabs.org/api/patches/816533/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/036217613544270ed280f8beddb846bc6b78b4b6.1505929556.git.alistair.francis@xilinx.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<036217613544270ed280f8beddb846bc6b78b4b6.1505929556.git.alistair.francis@xilinx.com>", "list_archive_url": null, "date": "2017-09-20T22:01:50", "name": "[v3,6/8] xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2e37e45a30b4da5e5f141bbb6d2b09fbc6b31e75", "submitter": { "id": 47878, "url": "http://patchwork.ozlabs.org/api/people/47878/?format=api", "name": "Alistair Francis", "email": "alistair.francis@xilinx.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/036217613544270ed280f8beddb846bc6b78b4b6.1505929556.git.alistair.francis@xilinx.com/mbox/", "series": [ { "id": 4241, "url": "http://patchwork.ozlabs.org/api/series/4241/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4241", "date": "2017-09-20T22:01:31", "name": "Add the ZynqMP PMU and IPI", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/4241/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816533/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816533/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=xilinx.onmicrosoft.com\n\theader.i=@xilinx.onmicrosoft.com header.b=\"5iPLWCLi\"; \n\tdkim-atps=neutral", "spf=pass (sender IP is 149.199.60.100)\n\tsmtp.mailfrom=xilinx.com; nongnu.org; dkim=none (message not signed)\n\theader.d=none;nongnu.org; dmarc=bestguesspass action=none\n\theader.from=xilinx.com;" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xyDWK11pxz9s8J\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 21 Sep 2017 08:12:29 +1000 (AEST)", "from localhost ([::1]:50886 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dunEJ-0005y6-95\n\tfor incoming@patchwork.ozlabs.org; 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Wed, 20 Sep 2017 15:05:29 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=xilinx.onmicrosoft.com; s=selector1-xilinx-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=GWBzmC0nxls+1+1GbTw2ChPNol9jt0y8owOEPKmYAVM=;\n\tb=5iPLWCLiF7zehPXJxB6iVYH5ln53SlYFYxV/ki13OWpkVFZHxzVQcqDaGIgJ2iJpmjBMhyaHyo3IARLqWqs8l1KmOLXWVuNzhr6ctOIfKF7nE0ajLhLfRDXg/5hVKrwmqNqiAZdonhynfiDv4oW5QnoV7mh9VIgcFHL5M5sk1wE=", "Received-SPF": "Pass (protection.outlook.com: domain of xilinx.com designates\n\t149.199.60.100 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=149.199.60.100; helo=xsj-pvapsmtpgw02;", "From": "Alistair Francis <alistair.francis@xilinx.com>", "To": "<qemu-devel@nongnu.org>, <edgar.iglesias@xilinx.com>,\n\t<edgar.iglesias@gmail.com>", "Date": "Wed, 20 Sep 2017 15:01:50 -0700", "Message-ID": "<036217613544270ed280f8beddb846bc6b78b4b6.1505929556.git.alistair.francis@xilinx.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<cover.1505929556.git.alistair.francis@xilinx.com>", "References": "<cover.1505929556.git.alistair.francis@xilinx.com>", "X-RCIS-Action": "ALLOW", "X-TM-AS-Product-Ver": "IMSS-7.1.0.1224-8.1.0.1062-23340.005", "X-TM-AS-User-Approved-Sender": "Yes;Yes", "X-EOPAttributedMessage": "0", "X-MS-Office365-Filtering-HT": "Tenant", "X-Forefront-Antispam-Report": "CIP:149.199.60.100; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BLUPR02MB1122; ", "X-Forefront-PRVS": "04362AC73B", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "xilinx.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Sep 2017 22:05:39.4027\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "657af505-d5df-48d0-8300-c31994686c5c", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=657af505-d5df-48d0-8300-c31994686c5c; \n\tIp=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BLUPR02MB1122", "X-detected-operating-system": "by eggs.gnu.org: Windows 7 or 8 [fuzzy]", "X-Received-From": "104.47.42.41", "Subject": "[Qemu-devel] [PATCH v3 6/8] xlnx-zynqmp-ipi: Initial version of the\n\tXilinx IPI device", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alistair23@gmail.com, qemu-arm@nongnu.org, alistair.francis@xilinx.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "This is the initial version of the Inter Processor Interrupt device.\n\nSigned-off-by: Alistair Francis <alistair.francis@xilinx.com>\n---\n\n hw/intc/Makefile.objs | 1 +\n hw/intc/xlnx-zynqmp-ipi.c | 377 ++++++++++++++++++++++++++++++++++++++\n include/hw/intc/xlnx-zynqmp-ipi.h | 57 ++++++\n 3 files changed, 435 insertions(+)\n create mode 100644 hw/intc/xlnx-zynqmp-ipi.c\n create mode 100644 include/hw/intc/xlnx-zynqmp-ipi.h", "diff": "diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs\nindex 0fce61e2ce..8497d05695 100644\n--- a/hw/intc/Makefile.objs\n+++ b/hw/intc/Makefile.objs\n@@ -4,6 +4,7 @@ common-obj-$(CONFIG_PL190) += pl190.o\n common-obj-$(CONFIG_PUV3) += puv3_intc.o\n common-obj-$(CONFIG_XILINX) += xilinx_intc.o\n common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-intc.o\n+common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-ipi.o\n common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o\n common-obj-$(CONFIG_IMX) += imx_avic.o\n common-obj-$(CONFIG_LM32) += lm32_pic.o\ndiff --git a/hw/intc/xlnx-zynqmp-ipi.c b/hw/intc/xlnx-zynqmp-ipi.c\nnew file mode 100644\nindex 0000000000..6203b27e56\n--- /dev/null\n+++ b/hw/intc/xlnx-zynqmp-ipi.c\n@@ -0,0 +1,377 @@\n+/*\n+ * QEMU model of the IPI Inter Processor Interrupt block\n+ *\n+ * Copyright (c) 2014 Xilinx Inc.\n+ *\n+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>\n+ * Written by Alistair Francis <alistair.francis@xilinx.com>\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/sysbus.h\"\n+#include \"hw/register.h\"\n+#include \"qemu/bitops.h\"\n+#include \"qemu/log.h\"\n+#include \"hw/intc/xlnx-zynqmp-ipi.h\"\n+\n+#ifndef XLNX_ZYNQMP_IPI_ERR_DEBUG\n+#define XLNX_ZYNQMP_IPI_ERR_DEBUG 0\n+#endif\n+\n+#define DB_PRINT_L(lvl, fmt, args...) do {\\\n+ if (XLNX_ZYNQMP_IPI_ERR_DEBUG >= lvl) {\\\n+ qemu_log(TYPE_XLNX_ZYNQMP_IPI \": %s:\" fmt, __func__, ## args);\\\n+ } \\\n+} while (0);\n+\n+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)\n+\n+REG32(IPI_TRIG, 0x0)\n+ FIELD(IPI_TRIG, PL_3, 27, 1)\n+ FIELD(IPI_TRIG, PL_2, 26, 1)\n+ FIELD(IPI_TRIG, PL_1, 25, 1)\n+ FIELD(IPI_TRIG, PL_0, 24, 1)\n+ FIELD(IPI_TRIG, PMU_3, 19, 1)\n+ FIELD(IPI_TRIG, PMU_2, 18, 1)\n+ FIELD(IPI_TRIG, PMU_1, 17, 1)\n+ FIELD(IPI_TRIG, PMU_0, 16, 1)\n+ FIELD(IPI_TRIG, RPU_1, 9, 1)\n+ FIELD(IPI_TRIG, RPU_0, 8, 1)\n+ FIELD(IPI_TRIG, APU, 0, 1)\n+REG32(IPI_OBS, 0x4)\n+ FIELD(IPI_OBS, PL_3, 27, 1)\n+ FIELD(IPI_OBS, PL_2, 26, 1)\n+ FIELD(IPI_OBS, PL_1, 25, 1)\n+ FIELD(IPI_OBS, PL_0, 24, 1)\n+ FIELD(IPI_OBS, PMU_3, 19, 1)\n+ FIELD(IPI_OBS, PMU_2, 18, 1)\n+ FIELD(IPI_OBS, PMU_1, 17, 1)\n+ FIELD(IPI_OBS, PMU_0, 16, 1)\n+ FIELD(IPI_OBS, RPU_1, 9, 1)\n+ FIELD(IPI_OBS, RPU_0, 8, 1)\n+ FIELD(IPI_OBS, APU, 0, 1)\n+REG32(IPI_ISR, 0x10)\n+ FIELD(IPI_ISR, PL_3, 27, 1)\n+ FIELD(IPI_ISR, PL_2, 26, 1)\n+ FIELD(IPI_ISR, PL_1, 25, 1)\n+ FIELD(IPI_ISR, PL_0, 24, 1)\n+ FIELD(IPI_ISR, PMU_3, 19, 1)\n+ FIELD(IPI_ISR, PMU_2, 18, 1)\n+ FIELD(IPI_ISR, PMU_1, 17, 1)\n+ FIELD(IPI_ISR, PMU_0, 16, 1)\n+ FIELD(IPI_ISR, RPU_1, 9, 1)\n+ FIELD(IPI_ISR, RPU_0, 8, 1)\n+ FIELD(IPI_ISR, APU, 0, 1)\n+REG32(IPI_IMR, 0x14)\n+ FIELD(IPI_IMR, PL_3, 27, 1)\n+ FIELD(IPI_IMR, PL_2, 26, 1)\n+ FIELD(IPI_IMR, PL_1, 25, 1)\n+ FIELD(IPI_IMR, PL_0, 24, 1)\n+ FIELD(IPI_IMR, PMU_3, 19, 1)\n+ FIELD(IPI_IMR, PMU_2, 18, 1)\n+ FIELD(IPI_IMR, PMU_1, 17, 1)\n+ FIELD(IPI_IMR, PMU_0, 16, 1)\n+ FIELD(IPI_IMR, RPU_1, 9, 1)\n+ FIELD(IPI_IMR, RPU_0, 8, 1)\n+ FIELD(IPI_IMR, APU, 0, 1)\n+REG32(IPI_IER, 0x18)\n+ FIELD(IPI_IER, PL_3, 27, 1)\n+ FIELD(IPI_IER, PL_2, 26, 1)\n+ FIELD(IPI_IER, PL_1, 25, 1)\n+ FIELD(IPI_IER, PL_0, 24, 1)\n+ FIELD(IPI_IER, PMU_3, 19, 1)\n+ FIELD(IPI_IER, PMU_2, 18, 1)\n+ FIELD(IPI_IER, PMU_1, 17, 1)\n+ FIELD(IPI_IER, PMU_0, 16, 1)\n+ FIELD(IPI_IER, RPU_1, 9, 1)\n+ FIELD(IPI_IER, RPU_0, 8, 1)\n+ FIELD(IPI_IER, APU, 0, 1)\n+REG32(IPI_IDR, 0x1c)\n+ FIELD(IPI_IDR, PL_3, 27, 1)\n+ FIELD(IPI_IDR, PL_2, 26, 1)\n+ FIELD(IPI_IDR, PL_1, 25, 1)\n+ FIELD(IPI_IDR, PL_0, 24, 1)\n+ FIELD(IPI_IDR, PMU_3, 19, 1)\n+ FIELD(IPI_IDR, PMU_2, 18, 1)\n+ FIELD(IPI_IDR, PMU_1, 17, 1)\n+ FIELD(IPI_IDR, PMU_0, 16, 1)\n+ FIELD(IPI_IDR, RPU_1, 9, 1)\n+ FIELD(IPI_IDR, RPU_0, 8, 1)\n+ FIELD(IPI_IDR, APU, 0, 1)\n+\n+/* APU\n+ * RPU_0\n+ * RPU_1\n+ * PMU_0\n+ * PMU_1\n+ * PMU_2\n+ * PMU_3\n+ * PL_0\n+ * PL_1\n+ * PL_2\n+ * PL_3\n+ */\n+int index_array[NUM_IPIS] = {0, 8, 9, 16, 17, 18, 19, 24, 25, 26, 27};\n+static const char *index_array_names[NUM_IPIS] = {\"APU\", \"RPU_0\", \"RPU_1\",\n+ \"PMU_0\", \"PMU_1\", \"PMU_2\",\n+ \"PMU_3\", \"PL_0\", \"PL_1\",\n+ \"PL_2\", \"PL_3\"};\n+\n+static void xlnx_zynqmp_ipi_set_trig(XlnxZynqMPIPI *s, uint32_t val)\n+{\n+ int i, ipi_index, ipi_mask;\n+\n+ for (i = 0; i < NUM_IPIS; i++) {\n+ ipi_index = index_array[i];\n+ ipi_mask = (1 << ipi_index);\n+ DB_PRINT(\"Setting %s=%d\\n\", index_array_names[i],\n+ !!(val & ipi_mask));\n+ qemu_set_irq(s->irq_trig_out[i], !!(val & ipi_mask));\n+ }\n+}\n+\n+static void xlnx_zynqmp_ipi_set_obs(XlnxZynqMPIPI *s, uint32_t val)\n+{\n+ int i, ipi_index, ipi_mask;\n+\n+ for (i = 0; i < NUM_IPIS; i++) {\n+ ipi_index = index_array[i];\n+ ipi_mask = (1 << ipi_index);\n+ DB_PRINT(\"Setting %s=%d\\n\", index_array_names[i],\n+ !!(val & ipi_mask));\n+ qemu_set_irq(s->irq_obs_out[i], !!(val & ipi_mask));\n+ }\n+}\n+\n+static void xlnx_zynqmp_ipi_update_irq(XlnxZynqMPIPI *s)\n+{\n+ bool pending = s->regs[R_IPI_ISR] & ~s->regs[R_IPI_IMR];\n+\n+ DB_PRINT(\"irq=%d isr=%x mask=%x\\n\",\n+ pending, s->regs[R_IPI_ISR], s->regs[R_IPI_IMR]);\n+ qemu_set_irq(s->irq, pending);\n+}\n+\n+static uint64_t xlnx_zynqmp_ipi_trig_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);\n+\n+ xlnx_zynqmp_ipi_set_trig(s, val64);\n+\n+ return val64;\n+}\n+\n+static void xlnx_zynqmp_ipi_trig_postw(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);\n+\n+ /* TRIG generates a pulse on the outbound signals. We use the\n+ * post-write callback to bring the signal back-down.\n+ */\n+ s->regs[R_IPI_TRIG] = 0;\n+\n+ xlnx_zynqmp_ipi_set_trig(s, 0);\n+}\n+\n+static uint64_t xlnx_zynqmp_ipi_isr_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);\n+\n+ xlnx_zynqmp_ipi_set_obs(s, val64);\n+\n+ return val64;\n+}\n+\n+static void xlnx_zynqmp_ipi_isr_postw(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);\n+\n+ xlnx_zynqmp_ipi_update_irq(s);\n+}\n+\n+static uint64_t xlnx_zynqmp_ipi_ier_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);\n+ uint32_t val = val64;\n+\n+ s->regs[R_IPI_IMR] &= ~val;\n+ xlnx_zynqmp_ipi_update_irq(s);\n+ return 0;\n+}\n+\n+static uint64_t xlnx_zynqmp_ipi_idr_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);\n+ uint32_t val = val64;\n+\n+ s->regs[R_IPI_IMR] |= val;\n+ xlnx_zynqmp_ipi_update_irq(s);\n+ return 0;\n+}\n+\n+static const RegisterAccessInfo xlnx_zynqmp_ipi_regs_info[] = {\n+ { .name = \"IPI_TRIG\", .addr = A_IPI_TRIG,\n+ .rsvd = 0xf0f0fcfe,\n+ .ro = 0xf0f0fcfe,\n+ .pre_write = xlnx_zynqmp_ipi_trig_prew,\n+ .post_write = xlnx_zynqmp_ipi_trig_postw,\n+ },{ .name = \"IPI_OBS\", .addr = A_IPI_OBS,\n+ .rsvd = 0xf0f0fcfe,\n+ .ro = 0xffffffff,\n+ },{ .name = \"IPI_ISR\", .addr = A_IPI_ISR,\n+ .rsvd = 0xf0f0fcfe,\n+ .ro = 0xf0f0fcfe,\n+ .w1c = 0xf0f0301,\n+ .pre_write = xlnx_zynqmp_ipi_isr_prew,\n+ .post_write = xlnx_zynqmp_ipi_isr_postw,\n+ },{ .name = \"IPI_IMR\", .addr = A_IPI_IMR,\n+ .reset = 0xf0f0301,\n+ .rsvd = 0xf0f0fcfe,\n+ .ro = 0xffffffff,\n+ },{ .name = \"IPI_IER\", .addr = A_IPI_IER,\n+ .rsvd = 0xf0f0fcfe,\n+ .ro = 0xf0f0fcfe,\n+ .pre_write = xlnx_zynqmp_ipi_ier_prew,\n+ },{ .name = \"IPI_IDR\", .addr = A_IPI_IDR,\n+ .rsvd = 0xf0f0fcfe,\n+ .ro = 0xf0f0fcfe,\n+ .pre_write = xlnx_zynqmp_ipi_idr_prew,\n+ }\n+};\n+\n+static void xlnx_zynqmp_ipi_reset(DeviceState *dev)\n+{\n+ XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(dev);\n+ int i;\n+\n+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {\n+ register_reset(&s->regs_info[i]);\n+ }\n+\n+ xlnx_zynqmp_ipi_update_irq(s);\n+}\n+\n+static void xlnx_zynqmp_ipi_handler(void *opaque, int n, int level)\n+{\n+ XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque);\n+ uint32_t val = (!!level) << n;\n+\n+ DB_PRINT(\"IPI input irq[%d]=%d\\n\", n, level);\n+\n+ s->regs[R_IPI_ISR] |= val;\n+ xlnx_zynqmp_ipi_set_obs(s, s->regs[R_IPI_ISR]);\n+ xlnx_zynqmp_ipi_update_irq(s);\n+}\n+\n+static void xlnx_zynqmp_obs_handler(void *opaque, int n, int level)\n+{\n+ XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque);\n+\n+ DB_PRINT(\"OBS input irq[%d]=%d\\n\", n, level);\n+\n+ s->regs[R_IPI_OBS] &= ~(1ULL << n);\n+ s->regs[R_IPI_OBS] |= (level << n);\n+}\n+\n+static const MemoryRegionOps xlnx_zynqmp_ipi_ops = {\n+ .read = register_read_memory,\n+ .write = register_write_memory,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .valid = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ },\n+};\n+\n+static void xlnx_zynqmp_ipi_realize(DeviceState *dev, Error **errp)\n+{\n+ qdev_init_gpio_in_named(dev, xlnx_zynqmp_ipi_handler, \"IPI_INPUTS\", 32);\n+ qdev_init_gpio_in_named(dev, xlnx_zynqmp_obs_handler, \"OBS_INPUTS\", 32);\n+}\n+\n+static void xlnx_zynqmp_ipi_init(Object *obj)\n+{\n+ XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(obj);\n+ DeviceState *dev = DEVICE(obj);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);\n+ RegisterInfoArray *reg_array;\n+ char *irq_name;\n+ int i;\n+\n+ memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IPI,\n+ R_XLNX_ZYNQMP_IPI_MAX * 4);\n+ reg_array =\n+ register_init_block32(DEVICE(obj), xlnx_zynqmp_ipi_regs_info,\n+ ARRAY_SIZE(xlnx_zynqmp_ipi_regs_info),\n+ s->regs_info, s->regs,\n+ &xlnx_zynqmp_ipi_ops,\n+ XLNX_ZYNQMP_IPI_ERR_DEBUG,\n+ R_XLNX_ZYNQMP_IPI_MAX * 4);\n+ memory_region_add_subregion(&s->iomem,\n+ 0x0,\n+ ®_array->mem);\n+ sysbus_init_mmio(sbd, &s->iomem);\n+ sysbus_init_irq(sbd, &s->irq);\n+\n+ for (i = 0; i < NUM_IPIS; i++) {\n+ qdev_init_gpio_out_named(dev, &s->irq_trig_out[i],\n+ index_array_names[i], 1);\n+\n+ irq_name = g_strdup_printf(\"OBS_%s\", index_array_names[i]);\n+ qdev_init_gpio_out_named(dev, &s->irq_obs_out[i],\n+ irq_name, 1);\n+ g_free(irq_name);\n+ }\n+}\n+\n+static const VMStateDescription vmstate_zynqmp_pmu_ipi = {\n+ .name = TYPE_XLNX_ZYNQMP_IPI,\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPIPI, R_XLNX_ZYNQMP_IPI_MAX),\n+ VMSTATE_END_OF_LIST(),\n+ }\n+};\n+\n+static void xlnx_zynqmp_ipi_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->reset = xlnx_zynqmp_ipi_reset;\n+ dc->realize = xlnx_zynqmp_ipi_realize;\n+ dc->vmsd = &vmstate_zynqmp_pmu_ipi;\n+}\n+\n+static const TypeInfo xlnx_zynqmp_ipi_info = {\n+ .name = TYPE_XLNX_ZYNQMP_IPI,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(XlnxZynqMPIPI),\n+ .class_init = xlnx_zynqmp_ipi_class_init,\n+ .instance_init = xlnx_zynqmp_ipi_init,\n+};\n+\n+static void xlnx_zynqmp_ipi_register_types(void)\n+{\n+ type_register_static(&xlnx_zynqmp_ipi_info);\n+}\n+\n+type_init(xlnx_zynqmp_ipi_register_types)\ndiff --git a/include/hw/intc/xlnx-zynqmp-ipi.h b/include/hw/intc/xlnx-zynqmp-ipi.h\nnew file mode 100644\nindex 0000000000..4afa4ff313\n--- /dev/null\n+++ b/include/hw/intc/xlnx-zynqmp-ipi.h\n@@ -0,0 +1,57 @@\n+/*\n+ * QEMU model of the IPI Inter Processor Interrupt block\n+ *\n+ * Copyright (c) 2014 Xilinx Inc.\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#ifndef XLNX_ZYNQMP_IPI_H\n+#define XLNX_ZYNQMP_IPI_H\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/sysbus.h\"\n+#include \"hw/register.h\"\n+\n+#define TYPE_XLNX_ZYNQMP_IPI \"xlnx.zynqmp_ipi\"\n+\n+#define XLNX_ZYNQMP_IPI(obj) \\\n+ OBJECT_CHECK(XlnxZynqMPIPI, (obj), TYPE_XLNX_ZYNQMP_IPI)\n+\n+/* This is R_IPI_IDR + 1 */\n+#define R_XLNX_ZYNQMP_IPI_MAX ((0x1c / 4) + 1)\n+\n+#define NUM_IPIS 11\n+\n+typedef struct XlnxZynqMPIPI {\n+ /* Private */\n+ SysBusDevice parent_obj;\n+\n+ /* Public */\n+ MemoryRegion iomem;\n+ qemu_irq irq;\n+\n+ qemu_irq irq_trig_out[NUM_IPIS];\n+ qemu_irq irq_obs_out[NUM_IPIS];\n+\n+ uint32_t regs[R_XLNX_ZYNQMP_IPI_MAX];\n+ RegisterInfo regs_info[R_XLNX_ZYNQMP_IPI_MAX];\n+} XlnxZynqMPIPI;\n+\n+#endif /* XLNX_ZYNQMP_IPI_H */\n", "prefixes": [ "v3", "6/8" ] }