Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/816530/?format=api
{ "id": 816530, "url": "http://patchwork.ozlabs.org/api/patches/816530/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/37d4c6fb8fb41bd8dc04c61c5d604ec8302ed545.1505929556.git.alistair.francis@xilinx.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<37d4c6fb8fb41bd8dc04c61c5d604ec8302ed545.1505929556.git.alistair.francis@xilinx.com>", "list_archive_url": null, "date": "2017-09-20T22:01:44", "name": "[v3,4/8] xlnx-pmu-iomod-intc: Add the PMU Interrupt controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "52a208d777831b4fa4ff4fc5bd4b07693b1f2735", "submitter": { "id": 47878, "url": "http://patchwork.ozlabs.org/api/people/47878/?format=api", "name": "Alistair Francis", "email": "alistair.francis@xilinx.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/37d4c6fb8fb41bd8dc04c61c5d604ec8302ed545.1505929556.git.alistair.francis@xilinx.com/mbox/", "series": [ { "id": 4241, "url": "http://patchwork.ozlabs.org/api/series/4241/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4241", "date": "2017-09-20T22:01:31", "name": "Add the ZynqMP PMU and IPI", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/4241/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816530/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816530/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Wed, 20 Sep 2017 15:05:23 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=xilinx.onmicrosoft.com; s=selector1-xilinx-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=3ZqkR+YXndSB/HweNqMSMeXD6ktPmdO63Po/LqRhGbU=;\n\tb=qoxWUg1KBuYCeNd/srwNqAli/saNO8jPtBILVtL9BNQCTFPX3DcpqnUS/q2OnNsJKLMV9IrQ2e2Z3I+cvqd+y0e+T/I9wHxjZD6wbi1uyxuCvPyttadU5zZoKIFj9lQSrWe2X3SKT3GAbr+BKmpyoRbVs2b7Pter/TS5iSV+h/8=", "Received-SPF": "Pass (protection.outlook.com: domain of xilinx.com designates\n\t149.199.60.83 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=149.199.60.83; helo=xsj-pvapsmtpgw01;", "From": "Alistair Francis <alistair.francis@xilinx.com>", "To": "<qemu-devel@nongnu.org>, <edgar.iglesias@xilinx.com>,\n\t<edgar.iglesias@gmail.com>", "Date": "Wed, 20 Sep 2017 15:01:44 -0700", "Message-ID": "<37d4c6fb8fb41bd8dc04c61c5d604ec8302ed545.1505929556.git.alistair.francis@xilinx.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<cover.1505929556.git.alistair.francis@xilinx.com>", "References": "<cover.1505929556.git.alistair.francis@xilinx.com>", "X-RCIS-Action": "ALLOW", "X-TM-AS-Product-Ver": "IMSS-7.1.0.1224-8.1.0.1062-23340.005", "X-TM-AS-User-Approved-Sender": "Yes;Yes", "X-EOPAttributedMessage": "0", "X-MS-Office365-Filtering-HT": "Tenant", "X-Forefront-Antispam-Report": "CIP:149.199.60.83; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BLUPR02MB1122; ", "X-Forefront-PRVS": "04362AC73B", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "xilinx.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Sep 2017 22:05:28.8982\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "657af505-d5df-48d0-8300-c31994686c5c", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=657af505-d5df-48d0-8300-c31994686c5c; \n\tIp=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BLUPR02MB1122", "X-detected-operating-system": "by eggs.gnu.org: Windows 7 or 8 [fuzzy]", "X-Received-From": "104.47.34.41", "Subject": "[Qemu-devel] [PATCH v3 4/8] xlnx-pmu-iomod-intc: Add the PMU\n\tInterrupt controller", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alistair23@gmail.com, qemu-arm@nongnu.org, alistair.francis@xilinx.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Add the PMU IO Module Interrupt controller device.\n\nSigned-off-by: Alistair Francis <alistair.francis@xilinx.com>\n---\n\n default-configs/microblaze-softmmu.mak | 1 +\n hw/intc/Makefile.objs | 1 +\n hw/intc/xlnx-pmu-iomod-intc.c | 554 +++++++++++++++++++++++++++++++++\n include/hw/intc/xlnx-pmu-iomod-intc.h | 58 ++++\n 4 files changed, 614 insertions(+)\n create mode 100644 hw/intc/xlnx-pmu-iomod-intc.c\n create mode 100644 include/hw/intc/xlnx-pmu-iomod-intc.h", "diff": "diff --git a/default-configs/microblaze-softmmu.mak b/default-configs/microblaze-softmmu.mak\nindex ce2630818a..7fca8e4c99 100644\n--- a/default-configs/microblaze-softmmu.mak\n+++ b/default-configs/microblaze-softmmu.mak\n@@ -9,3 +9,4 @@ CONFIG_XILINX_SPI=y\n CONFIG_XILINX_ETHLITE=y\n CONFIG_SSI=y\n CONFIG_SSI_M25P80=y\n+CONFIG_XLNX_ZYNQMP=y\ndiff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs\nindex 78426a7daf..0fce61e2ce 100644\n--- a/hw/intc/Makefile.objs\n+++ b/hw/intc/Makefile.objs\n@@ -3,6 +3,7 @@ common-obj-$(CONFIG_I8259) += i8259_common.o i8259.o\n common-obj-$(CONFIG_PL190) += pl190.o\n common-obj-$(CONFIG_PUV3) += puv3_intc.o\n common-obj-$(CONFIG_XILINX) += xilinx_intc.o\n+common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-intc.o\n common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o\n common-obj-$(CONFIG_IMX) += imx_avic.o\n common-obj-$(CONFIG_LM32) += lm32_pic.o\ndiff --git a/hw/intc/xlnx-pmu-iomod-intc.c b/hw/intc/xlnx-pmu-iomod-intc.c\nnew file mode 100644\nindex 0000000000..4ec7991f4f\n--- /dev/null\n+++ b/hw/intc/xlnx-pmu-iomod-intc.c\n@@ -0,0 +1,554 @@\n+/*\n+ * QEMU model of Xilinx I/O Module Interrupt Controller\n+ *\n+ * Copyright (c) 2013 Xilinx Inc\n+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>\n+ * Written by Alistair Francis <alistair.francis@xilinx.com>\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/sysbus.h\"\n+#include \"hw/register.h\"\n+#include \"qemu/bitops.h\"\n+#include \"qemu/log.h\"\n+#include \"hw/intc/xlnx-pmu-iomod-intc.h\"\n+\n+#ifndef XLNX_PMU_IO_INTC_ERR_DEBUG\n+#define XLNX_PMU_IO_INTC_ERR_DEBUG 0\n+#endif\n+\n+#define DB_PRINT_L(lvl, fmt, args...) do {\\\n+ if (XLNX_PMU_IO_INTC_ERR_DEBUG >= lvl) {\\\n+ qemu_log(TYPE_XLNX_PMU_IO_INTC \": %s:\" fmt, __func__, ## args);\\\n+ } \\\n+} while (0);\n+\n+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)\n+\n+REG32(IRQ_MODE, 0xc)\n+REG32(GPO0, 0x10)\n+ FIELD(GPO0, MAGIC_WORD_1, 24, 8)\n+ FIELD(GPO0, MAGIC_WORD_2, 16, 8)\n+ FIELD(GPO0, FT_INJECT_FAILURE, 13, 3)\n+ FIELD(GPO0, DISABLE_RST_FTSM, 12, 1)\n+ FIELD(GPO0, RST_FTSM, 11, 1)\n+ FIELD(GPO0, CLR_FTSTS, 10, 1)\n+ FIELD(GPO0, RST_ON_SLEEP, 9, 1)\n+ FIELD(GPO0, DISABLE_TRACE_COMP, 8, 1)\n+ FIELD(GPO0, PIT3_PRESCALE, 7, 1)\n+ FIELD(GPO0, PIT2_PRESCALE, 5, 2)\n+ FIELD(GPO0, PIT1_PRESCALE, 3, 2)\n+ FIELD(GPO0, PIT0_PRESCALE, 1, 2)\n+ FIELD(GPO0, DEBUG_REMAP, 0, 1)\n+REG32(GPO1, 0x14)\n+ FIELD(GPO1, MIO_5, 5, 1)\n+ FIELD(GPO1, MIO_4, 4, 1)\n+ FIELD(GPO1, MIO_3, 3, 1)\n+ FIELD(GPO1, MIO_2, 2, 1)\n+ FIELD(GPO1, MIO_1, 1, 1)\n+ FIELD(GPO1, MIO_0, 0, 1)\n+REG32(GPO2, 0x18)\n+ FIELD(GPO2, DAP_RPU_WAKE_ACK, 9, 1)\n+ FIELD(GPO2, DAP_FP_WAKE_ACK, 8, 1)\n+ FIELD(GPO2, PS_STATUS, 7, 1)\n+ FIELD(GPO2, PCAP_EN, 6, 1)\n+REG32(GPO3, 0x1c)\n+ FIELD(GPO3, PL_GPO_31, 31, 1)\n+ FIELD(GPO3, PL_GPO_30, 30, 1)\n+ FIELD(GPO3, PL_GPO_29, 29, 1)\n+ FIELD(GPO3, PL_GPO_28, 28, 1)\n+ FIELD(GPO3, PL_GPO_27, 27, 1)\n+ FIELD(GPO3, PL_GPO_26, 26, 1)\n+ FIELD(GPO3, PL_GPO_25, 25, 1)\n+ FIELD(GPO3, PL_GPO_24, 24, 1)\n+ FIELD(GPO3, PL_GPO_23, 23, 1)\n+ FIELD(GPO3, PL_GPO_22, 22, 1)\n+ FIELD(GPO3, PL_GPO_21, 21, 1)\n+ FIELD(GPO3, PL_GPO_20, 20, 1)\n+ FIELD(GPO3, PL_GPO_19, 19, 1)\n+ FIELD(GPO3, PL_GPO_18, 18, 1)\n+ FIELD(GPO3, PL_GPO_17, 17, 1)\n+ FIELD(GPO3, PL_GPO_16, 16, 1)\n+ FIELD(GPO3, PL_GPO_15, 15, 1)\n+ FIELD(GPO3, PL_GPO_14, 14, 1)\n+ FIELD(GPO3, PL_GPO_13, 13, 1)\n+ FIELD(GPO3, PL_GPO_12, 12, 1)\n+ FIELD(GPO3, PL_GPO_11, 11, 1)\n+ FIELD(GPO3, PL_GPO_10, 10, 1)\n+ FIELD(GPO3, PL_GPO_9, 9, 1)\n+ FIELD(GPO3, PL_GPO_8, 8, 1)\n+ FIELD(GPO3, PL_GPO_7, 7, 1)\n+ FIELD(GPO3, PL_GPO_6, 6, 1)\n+ FIELD(GPO3, PL_GPO_5, 5, 1)\n+ FIELD(GPO3, PL_GPO_4, 4, 1)\n+ FIELD(GPO3, PL_GPO_3, 3, 1)\n+ FIELD(GPO3, PL_GPO_2, 2, 1)\n+ FIELD(GPO3, PL_GPO_1, 1, 1)\n+ FIELD(GPO3, PL_GPO_0, 0, 1)\n+REG32(GPI0, 0x20)\n+ FIELD(GPI0, RFT_ECC_FATAL_ERR, 31, 1)\n+ FIELD(GPI0, RFT_VOTER_ERR, 30, 1)\n+ FIELD(GPI0, RFT_COMPARE_ERR_23, 29, 1)\n+ FIELD(GPI0, RFT_COMPARE_ERR_13, 28, 1)\n+ FIELD(GPI0, RFT_COMPARE_ERR_12, 27, 1)\n+ FIELD(GPI0, RFT_LS_MISMATCH_23_B, 26, 1)\n+ FIELD(GPI0, RFT_LS_MISMATCH_13_B, 25, 1)\n+ FIELD(GPI0, RFT_LS_MISMATCH_12_B, 24, 1)\n+ FIELD(GPI0, RFT_MISMATCH_STATE, 23, 1)\n+ FIELD(GPI0, RFT_MISMATCH_CPU, 22, 1)\n+ FIELD(GPI0, RFT_SLEEP_RESET, 19, 1)\n+ FIELD(GPI0, RFT_LS_MISMATCH_23_A, 18, 1)\n+ FIELD(GPI0, RFT_LS_MISMATCH_13_A, 17, 1)\n+ FIELD(GPI0, RFT_LS_MISMATCH_12_A, 16, 1)\n+ FIELD(GPI0, NFT_ECC_FATAL_ERR, 15, 1)\n+ FIELD(GPI0, NFT_VOTER_ERR, 14, 1)\n+ FIELD(GPI0, NFT_COMPARE_ERR_23, 13, 1)\n+ FIELD(GPI0, NFT_COMPARE_ERR_13, 12, 1)\n+ FIELD(GPI0, NFT_COMPARE_ERR_12, 11, 1)\n+ FIELD(GPI0, NFT_LS_MISMATCH_23_B, 10, 1)\n+ FIELD(GPI0, NFT_LS_MISMATCH_13_B, 9, 1)\n+ FIELD(GPI0, NFT_LS_MISMATCH_12_B, 8, 1)\n+ FIELD(GPI0, NFT_MISMATCH_STATE, 7, 1)\n+ FIELD(GPI0, NFT_MISMATCH_CPU, 6, 1)\n+ FIELD(GPI0, NFT_SLEEP_RESET, 3, 1)\n+ FIELD(GPI0, NFT_LS_MISMATCH_23_A, 2, 1)\n+ FIELD(GPI0, NFT_LS_MISMATCH_13_A, 1, 1)\n+ FIELD(GPI0, NFT_LS_MISMATCH_12_A, 0, 1)\n+REG32(GPI1, 0x24)\n+ FIELD(GPI1, APB_AIB_ERROR, 31, 1)\n+ FIELD(GPI1, AXI_AIB_ERROR, 30, 1)\n+ FIELD(GPI1, ERROR_2, 29, 1)\n+ FIELD(GPI1, ERROR_1, 28, 1)\n+ FIELD(GPI1, ACPU_3_DBG_PWRUP, 23, 1)\n+ FIELD(GPI1, ACPU_2_DBG_PWRUP, 22, 1)\n+ FIELD(GPI1, ACPU_1_DBG_PWRUP, 21, 1)\n+ FIELD(GPI1, ACPU_0_DBG_PWRUP, 20, 1)\n+ FIELD(GPI1, FPD_WAKE_GIC_PROXY, 16, 1)\n+ FIELD(GPI1, MIO_WAKE_5, 15, 1)\n+ FIELD(GPI1, MIO_WAKE_4, 14, 1)\n+ FIELD(GPI1, MIO_WAKE_3, 13, 1)\n+ FIELD(GPI1, MIO_WAKE_2, 12, 1)\n+ FIELD(GPI1, MIO_WAKE_1, 11, 1)\n+ FIELD(GPI1, MIO_WAKE_0, 10, 1)\n+ FIELD(GPI1, DAP_RPU_WAKE, 9, 1)\n+ FIELD(GPI1, DAP_FPD_WAKE, 8, 1)\n+ FIELD(GPI1, USB_1_WAKE, 7, 1)\n+ FIELD(GPI1, USB_0_WAKE, 6, 1)\n+ FIELD(GPI1, R5_1_WAKE, 5, 1)\n+ FIELD(GPI1, R5_0_WAKE, 4, 1)\n+ FIELD(GPI1, ACPU_3_WAKE, 3, 1)\n+ FIELD(GPI1, ACPU_2_WAKE, 2, 1)\n+ FIELD(GPI1, ACPU_1_WAKE, 1, 1)\n+ FIELD(GPI1, ACPU_0_WAKE, 0, 1)\n+REG32(GPI2, 0x28)\n+ FIELD(GPI2, VCC_INT_FP_DISCONNECT, 31, 1)\n+ FIELD(GPI2, VCC_INT_DISCONNECT, 30, 1)\n+ FIELD(GPI2, VCC_AUX_DISCONNECT, 29, 1)\n+ FIELD(GPI2, DBG_ACPU3_RST_REQ, 23, 1)\n+ FIELD(GPI2, DBG_ACPU2_RST_REQ, 22, 1)\n+ FIELD(GPI2, DBG_ACPU1_RST_REQ, 21, 1)\n+ FIELD(GPI2, DBG_ACPU0_RST_REQ, 20, 1)\n+ FIELD(GPI2, CP_ACPU3_RST_REQ, 19, 1)\n+ FIELD(GPI2, CP_ACPU2_RST_REQ, 18, 1)\n+ FIELD(GPI2, CP_ACPU1_RST_REQ, 17, 1)\n+ FIELD(GPI2, CP_ACPU0_RST_REQ, 16, 1)\n+ FIELD(GPI2, DBG_RCPU1_RST_REQ, 9, 1)\n+ FIELD(GPI2, DBG_RCPU0_RST_REQ, 8, 1)\n+ FIELD(GPI2, R5_1_SLEEP, 5, 1)\n+ FIELD(GPI2, R5_0_SLEEP, 4, 1)\n+ FIELD(GPI2, ACPU_3_SLEEP, 3, 1)\n+ FIELD(GPI2, ACPU_2_SLEEP, 2, 1)\n+ FIELD(GPI2, ACPU_1_SLEEP, 1, 1)\n+ FIELD(GPI2, ACPU_0_SLEEP, 0, 1)\n+REG32(GPI3, 0x2c)\n+ FIELD(GPI3, PL_GPI_31, 31, 1)\n+ FIELD(GPI3, PL_GPI_30, 30, 1)\n+ FIELD(GPI3, PL_GPI_29, 29, 1)\n+ FIELD(GPI3, PL_GPI_28, 28, 1)\n+ FIELD(GPI3, PL_GPI_27, 27, 1)\n+ FIELD(GPI3, PL_GPI_26, 26, 1)\n+ FIELD(GPI3, PL_GPI_25, 25, 1)\n+ FIELD(GPI3, PL_GPI_24, 24, 1)\n+ FIELD(GPI3, PL_GPI_23, 23, 1)\n+ FIELD(GPI3, PL_GPI_22, 22, 1)\n+ FIELD(GPI3, PL_GPI_21, 21, 1)\n+ FIELD(GPI3, PL_GPI_20, 20, 1)\n+ FIELD(GPI3, PL_GPI_19, 19, 1)\n+ FIELD(GPI3, PL_GPI_18, 18, 1)\n+ FIELD(GPI3, PL_GPI_17, 17, 1)\n+ FIELD(GPI3, PL_GPI_16, 16, 1)\n+ FIELD(GPI3, PL_GPI_15, 15, 1)\n+ FIELD(GPI3, PL_GPI_14, 14, 1)\n+ FIELD(GPI3, PL_GPI_13, 13, 1)\n+ FIELD(GPI3, PL_GPI_12, 12, 1)\n+ FIELD(GPI3, PL_GPI_11, 11, 1)\n+ FIELD(GPI3, PL_GPI_10, 10, 1)\n+ FIELD(GPI3, PL_GPI_9, 9, 1)\n+ FIELD(GPI3, PL_GPI_8, 8, 1)\n+ FIELD(GPI3, PL_GPI_7, 7, 1)\n+ FIELD(GPI3, PL_GPI_6, 6, 1)\n+ FIELD(GPI3, PL_GPI_5, 5, 1)\n+ FIELD(GPI3, PL_GPI_4, 4, 1)\n+ FIELD(GPI3, PL_GPI_3, 3, 1)\n+ FIELD(GPI3, PL_GPI_2, 2, 1)\n+ FIELD(GPI3, PL_GPI_1, 1, 1)\n+ FIELD(GPI3, PL_GPI_0, 0, 1)\n+REG32(IRQ_STATUS, 0x30)\n+ FIELD(IRQ_STATUS, CSU_PMU_SEC_LOCK, 31, 1)\n+ FIELD(IRQ_STATUS, INV_ADDR, 29, 1)\n+ FIELD(IRQ_STATUS, PWR_DN_REQ, 28, 1)\n+ FIELD(IRQ_STATUS, PWR_UP_REQ, 27, 1)\n+ FIELD(IRQ_STATUS, SW_RST_REQ, 26, 1)\n+ FIELD(IRQ_STATUS, HW_RST_REQ, 25, 1)\n+ FIELD(IRQ_STATUS, ISO_REQ, 24, 1)\n+ FIELD(IRQ_STATUS, FW_REQ, 23, 1)\n+ FIELD(IRQ_STATUS, IPI3, 22, 1)\n+ FIELD(IRQ_STATUS, IPI2, 21, 1)\n+ FIELD(IRQ_STATUS, IPI1, 20, 1)\n+ FIELD(IRQ_STATUS, IPI0, 19, 1)\n+ FIELD(IRQ_STATUS, RTC_ALARM, 18, 1)\n+ FIELD(IRQ_STATUS, RTC_EVERY_SECOND, 17, 1)\n+ FIELD(IRQ_STATUS, CORRECTABLE_ECC, 16, 1)\n+ FIELD(IRQ_STATUS, GPI3, 14, 1)\n+ FIELD(IRQ_STATUS, GPI2, 13, 1)\n+ FIELD(IRQ_STATUS, GPI1, 12, 1)\n+ FIELD(IRQ_STATUS, GPI0, 11, 1)\n+ FIELD(IRQ_STATUS, PIT3, 6, 1)\n+ FIELD(IRQ_STATUS, PIT2, 5, 1)\n+ FIELD(IRQ_STATUS, PIT1, 4, 1)\n+ FIELD(IRQ_STATUS, PIT0, 3, 1)\n+REG32(IRQ_PENDING, 0x34)\n+ FIELD(IRQ_PENDING, CSU_PMU_SEC_LOCK, 31, 1)\n+ FIELD(IRQ_PENDING, INV_ADDR, 29, 1)\n+ FIELD(IRQ_PENDING, PWR_DN_REQ, 28, 1)\n+ FIELD(IRQ_PENDING, PWR_UP_REQ, 27, 1)\n+ FIELD(IRQ_PENDING, SW_RST_REQ, 26, 1)\n+ FIELD(IRQ_PENDING, HW_RST_REQ, 25, 1)\n+ FIELD(IRQ_PENDING, ISO_REQ, 24, 1)\n+ FIELD(IRQ_PENDING, FW_REQ, 23, 1)\n+ FIELD(IRQ_PENDING, IPI3, 22, 1)\n+ FIELD(IRQ_PENDING, IPI2, 21, 1)\n+ FIELD(IRQ_PENDING, IPI1, 20, 1)\n+ FIELD(IRQ_PENDING, IPI0, 19, 1)\n+ FIELD(IRQ_PENDING, RTC_ALARM, 18, 1)\n+ FIELD(IRQ_PENDING, RTC_EVERY_SECOND, 17, 1)\n+ FIELD(IRQ_PENDING, CORRECTABLE_ECC, 16, 1)\n+ FIELD(IRQ_PENDING, GPI3, 14, 1)\n+ FIELD(IRQ_PENDING, GPI2, 13, 1)\n+ FIELD(IRQ_PENDING, GPI1, 12, 1)\n+ FIELD(IRQ_PENDING, GPI0, 11, 1)\n+ FIELD(IRQ_PENDING, PIT3, 6, 1)\n+ FIELD(IRQ_PENDING, PIT2, 5, 1)\n+ FIELD(IRQ_PENDING, PIT1, 4, 1)\n+ FIELD(IRQ_PENDING, PIT0, 3, 1)\n+REG32(IRQ_ENABLE, 0x38)\n+ FIELD(IRQ_ENABLE, CSU_PMU_SEC_LOCK, 31, 1)\n+ FIELD(IRQ_ENABLE, INV_ADDR, 29, 1)\n+ FIELD(IRQ_ENABLE, PWR_DN_REQ, 28, 1)\n+ FIELD(IRQ_ENABLE, PWR_UP_REQ, 27, 1)\n+ FIELD(IRQ_ENABLE, SW_RST_REQ, 26, 1)\n+ FIELD(IRQ_ENABLE, HW_RST_REQ, 25, 1)\n+ FIELD(IRQ_ENABLE, ISO_REQ, 24, 1)\n+ FIELD(IRQ_ENABLE, FW_REQ, 23, 1)\n+ FIELD(IRQ_ENABLE, IPI3, 22, 1)\n+ FIELD(IRQ_ENABLE, IPI2, 21, 1)\n+ FIELD(IRQ_ENABLE, IPI1, 20, 1)\n+ FIELD(IRQ_ENABLE, IPI0, 19, 1)\n+ FIELD(IRQ_ENABLE, RTC_ALARM, 18, 1)\n+ FIELD(IRQ_ENABLE, RTC_EVERY_SECOND, 17, 1)\n+ FIELD(IRQ_ENABLE, CORRECTABLE_ECC, 16, 1)\n+ FIELD(IRQ_ENABLE, GPI3, 14, 1)\n+ FIELD(IRQ_ENABLE, GPI2, 13, 1)\n+ FIELD(IRQ_ENABLE, GPI1, 12, 1)\n+ FIELD(IRQ_ENABLE, GPI0, 11, 1)\n+ FIELD(IRQ_ENABLE, PIT3, 6, 1)\n+ FIELD(IRQ_ENABLE, PIT2, 5, 1)\n+ FIELD(IRQ_ENABLE, PIT1, 4, 1)\n+ FIELD(IRQ_ENABLE, PIT0, 3, 1)\n+REG32(IRQ_ACK, 0x3c)\n+ FIELD(IRQ_ACK, CSU_PMU_SEC_LOCK, 31, 1)\n+ FIELD(IRQ_ACK, INV_ADDR, 29, 1)\n+ FIELD(IRQ_ACK, PWR_DN_REQ, 28, 1)\n+ FIELD(IRQ_ACK, PWR_UP_REQ, 27, 1)\n+ FIELD(IRQ_ACK, SW_RST_REQ, 26, 1)\n+ FIELD(IRQ_ACK, HW_RST_REQ, 25, 1)\n+ FIELD(IRQ_ACK, ISO_REQ, 24, 1)\n+ FIELD(IRQ_ACK, FW_REQ, 23, 1)\n+ FIELD(IRQ_ACK, IPI3, 22, 1)\n+ FIELD(IRQ_ACK, IPI2, 21, 1)\n+ FIELD(IRQ_ACK, IPI1, 20, 1)\n+ FIELD(IRQ_ACK, IPI0, 19, 1)\n+ FIELD(IRQ_ACK, RTC_ALARM, 18, 1)\n+ FIELD(IRQ_ACK, RTC_EVERY_SECOND, 17, 1)\n+ FIELD(IRQ_ACK, CORRECTABLE_ECC, 16, 1)\n+ FIELD(IRQ_ACK, GPI3, 14, 1)\n+ FIELD(IRQ_ACK, GPI2, 13, 1)\n+ FIELD(IRQ_ACK, GPI1, 12, 1)\n+ FIELD(IRQ_ACK, GPI0, 11, 1)\n+ FIELD(IRQ_ACK, PIT3, 6, 1)\n+ FIELD(IRQ_ACK, PIT2, 5, 1)\n+ FIELD(IRQ_ACK, PIT1, 4, 1)\n+ FIELD(IRQ_ACK, PIT0, 3, 1)\n+REG32(PIT0_PRELOAD, 0x40)\n+REG32(PIT0_COUNTER, 0x44)\n+REG32(PIT0_CONTROL, 0x48)\n+ FIELD(PIT0_CONTROL, PRELOAD, 1, 1)\n+ FIELD(PIT0_CONTROL, EN, 0, 1)\n+REG32(PIT1_PRELOAD, 0x50)\n+REG32(PIT1_COUNTER, 0x54)\n+REG32(PIT1_CONTROL, 0x58)\n+ FIELD(PIT1_CONTROL, PRELOAD, 1, 1)\n+ FIELD(PIT1_CONTROL, EN, 0, 1)\n+REG32(PIT2_PRELOAD, 0x60)\n+REG32(PIT2_COUNTER, 0x64)\n+REG32(PIT2_CONTROL, 0x68)\n+ FIELD(PIT2_CONTROL, PRELOAD, 1, 1)\n+ FIELD(PIT2_CONTROL, EN, 0, 1)\n+REG32(PIT3_PRELOAD, 0x70)\n+REG32(PIT3_COUNTER, 0x74)\n+REG32(PIT3_CONTROL, 0x78)\n+ FIELD(PIT3_CONTROL, PRELOAD, 1, 1)\n+ FIELD(PIT3_CONTROL, EN, 0, 1)\n+\n+static void xlnx_pmu_io_irq_update(XlnxPMUIOIntc *s)\n+{\n+ bool irq_out;\n+\n+ s->regs[R_IRQ_PENDING] = s->regs[R_IRQ_STATUS] & s->regs[R_IRQ_ENABLE];\n+ irq_out = !!s->regs[R_IRQ_PENDING];\n+\n+ DB_PRINT(\"Setting IRQ output = %d\\n\", irq_out);\n+\n+ qemu_set_irq(s->parent_irq, irq_out);\n+}\n+\n+static void xlnx_pmu_io_irq_enable_postw(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque);\n+\n+ xlnx_pmu_io_irq_update(s);\n+}\n+\n+static void xlnx_pmu_io_irq_ack_postw(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque);\n+ uint32_t val = val64;\n+\n+ /* Only clear */\n+ val &= s->regs[R_IRQ_STATUS];\n+ s->regs[R_IRQ_STATUS] ^= val;\n+\n+ /* Active level triggered interrupts stay high. */\n+ s->regs[R_IRQ_STATUS] |= s->irq_raw & ~s->cfg.level_edge;\n+\n+ xlnx_pmu_io_irq_update(s);\n+}\n+\n+static const RegisterAccessInfo xlnx_pmu_io_intc_regs_info[] = {\n+ { .name = \"IRQ_MODE\", .addr = A_IRQ_MODE,\n+ .rsvd = 0xffffffff,\n+ },{ .name = \"GPO0\", .addr = A_GPO0,\n+ },{ .name = \"GPO1\", .addr = A_GPO1,\n+ .rsvd = 0xffffffc0,\n+ },{ .name = \"GPO2\", .addr = A_GPO2,\n+ .rsvd = 0xfffffc3f,\n+ },{ .name = \"GPO3\", .addr = A_GPO3,\n+ },{ .name = \"GPI0\", .addr = A_GPI0,\n+ .rsvd = 0x300030,\n+ .ro = 0xffcfffcf,\n+ },{ .name = \"GPI1\", .addr = A_GPI1,\n+ .rsvd = 0xf0e0000,\n+ .ro = 0xf0f1ffff,\n+ },{ .name = \"GPI2\", .addr = A_GPI2,\n+ .rsvd = 0x1f00fcc0,\n+ .ro = 0xe0ff033f,\n+ },{ .name = \"GPI3\", .addr = A_GPI3,\n+ .ro = 0xffffffff,\n+ },{ .name = \"IRQ_STATUS\", .addr = A_IRQ_STATUS,\n+ .rsvd = 0x40008787,\n+ .ro = 0xbfff7878,\n+ },{ .name = \"IRQ_PENDING\", .addr = A_IRQ_PENDING,\n+ .rsvd = 0x40008787,\n+ .ro = 0xdfff7ff8,\n+ },{ .name = \"IRQ_ENABLE\", .addr = A_IRQ_ENABLE,\n+ .rsvd = 0x40008787,\n+ .ro = 0x7800,\n+ .post_write = xlnx_pmu_io_irq_enable_postw,\n+ },{ .name = \"IRQ_ACK\", .addr = A_IRQ_ACK,\n+ .rsvd = 0x40008787,\n+ .post_write = xlnx_pmu_io_irq_ack_postw,\n+ },{ .name = \"PIT0_PRELOAD\", .addr = A_PIT0_PRELOAD,\n+ .ro = 0xffffffff,\n+ },{ .name = \"PIT0_COUNTER\", .addr = A_PIT0_COUNTER,\n+ .ro = 0xffffffff,\n+ },{ .name = \"PIT0_CONTROL\", .addr = A_PIT0_CONTROL,\n+ .rsvd = 0xfffffffc,\n+ },{ .name = \"PIT1_PRELOAD\", .addr = A_PIT1_PRELOAD,\n+ .ro = 0xffffffff,\n+ },{ .name = \"PIT1_COUNTER\", .addr = A_PIT1_COUNTER,\n+ .ro = 0xffffffff,\n+ },{ .name = \"PIT1_CONTROL\", .addr = A_PIT1_CONTROL,\n+ .rsvd = 0xfffffffc,\n+ },{ .name = \"PIT2_PRELOAD\", .addr = A_PIT2_PRELOAD,\n+ .ro = 0xffffffff,\n+ },{ .name = \"PIT2_COUNTER\", .addr = A_PIT2_COUNTER,\n+ .ro = 0xffffffff,\n+ },{ .name = \"PIT2_CONTROL\", .addr = A_PIT2_CONTROL,\n+ .rsvd = 0xfffffffc,\n+ },{ .name = \"PIT3_PRELOAD\", .addr = A_PIT3_PRELOAD,\n+ .ro = 0xffffffff,\n+ },{ .name = \"PIT3_COUNTER\", .addr = A_PIT3_COUNTER,\n+ .ro = 0xffffffff,\n+ },{ .name = \"PIT3_CONTROL\", .addr = A_PIT3_CONTROL,\n+ .rsvd = 0xfffffffc,\n+ }\n+};\n+\n+static void irq_handler(void *opaque, int irq, int level)\n+{\n+ XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(opaque);\n+ uint32_t mask = 1 << irq;\n+ uint32_t prev = s->irq_raw;\n+ uint32_t temp;\n+\n+ s->irq_raw &= ~mask;\n+ s->irq_raw |= (!!level) << irq;\n+\n+ /* Turn active-low into active-high. */\n+ s->irq_raw ^= (~s->cfg.positive);\n+ s->irq_raw &= mask;\n+\n+ if (s->cfg.level_edge & mask) {\n+ /* Edge triggered. */\n+ temp = (prev ^ s->irq_raw) & s->irq_raw;\n+ } else {\n+ /* Level triggered. */\n+ temp = s->irq_raw;\n+ }\n+ s->regs[R_IRQ_STATUS] |= temp;\n+\n+ xlnx_pmu_io_irq_update(s);\n+}\n+\n+static void xlnx_pmu_io_intc_reset(DeviceState *dev)\n+{\n+ XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(dev);\n+ unsigned int i;\n+\n+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {\n+ register_reset(&s->regs_info[i]);\n+ }\n+\n+ xlnx_pmu_io_irq_update(s);\n+}\n+\n+static const MemoryRegionOps xlnx_pmu_io_intc_ops = {\n+ .read = register_read_memory,\n+ .write = register_write_memory,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .valid = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ },\n+};\n+\n+static Property xlnx_pmu_io_intc_properties[] = {\n+ DEFINE_PROP_UINT32(\"intc-intr-size\", XlnxPMUIOIntc, cfg.intr_size, 0),\n+ DEFINE_PROP_UINT32(\"intc-level-edge\", XlnxPMUIOIntc, cfg.level_edge, 0),\n+ DEFINE_PROP_UINT32(\"intc-positive\", XlnxPMUIOIntc, cfg.positive, 0),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n+static void xlnx_pmu_io_intc_realize(DeviceState *dev, Error **errp)\n+{\n+ XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(dev);\n+\n+ /* Internal interrupts are edge triggered? */\n+ s->cfg.level_edge <<= 16;\n+ s->cfg.level_edge |= 0xffff;\n+\n+ /* Internal interrupts are postitive. */\n+ s->cfg.positive <<= 16;\n+ s->cfg.positive |= 0xffff;\n+\n+ /* Max 16 external interrupts. */\n+ assert(s->cfg.intr_size <= 16);\n+\n+ qdev_init_gpio_in(dev, irq_handler, 16 + s->cfg.intr_size);\n+}\n+\n+static void xlnx_pmu_io_intc_init(Object *obj)\n+{\n+ XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(obj);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);\n+ RegisterInfoArray *reg_array;\n+\n+ memory_region_init(&s->iomem, obj, TYPE_XLNX_PMU_IO_INTC,\n+ XlnxPMUIOIntc_R_MAX * 4);\n+ reg_array =\n+ register_init_block32(DEVICE(obj), xlnx_pmu_io_intc_regs_info,\n+ ARRAY_SIZE(xlnx_pmu_io_intc_regs_info),\n+ s->regs_info, s->regs,\n+ &xlnx_pmu_io_intc_ops,\n+ XLNX_PMU_IO_INTC_ERR_DEBUG,\n+ XlnxPMUIOIntc_R_MAX * 4);\n+ memory_region_add_subregion(&s->iomem,\n+ 0x0,\n+ ®_array->mem);\n+ sysbus_init_mmio(sbd, &s->iomem);\n+\n+ sysbus_init_irq(sbd, &s->parent_irq);\n+}\n+\n+static const VMStateDescription vmstate_xlnx_pmu_io_intc = {\n+ .name = TYPE_XLNX_PMU_IO_INTC,\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_UINT32_ARRAY(regs, XlnxPMUIOIntc, XlnxPMUIOIntc_R_MAX),\n+ VMSTATE_END_OF_LIST(),\n+ }\n+};\n+\n+static void xlnx_pmu_io_intc_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->reset = xlnx_pmu_io_intc_reset;\n+ dc->realize = xlnx_pmu_io_intc_realize;\n+ dc->vmsd = &vmstate_xlnx_pmu_io_intc;\n+ dc->props = xlnx_pmu_io_intc_properties;\n+}\n+\n+static const TypeInfo xlnx_pmu_io_intc_info = {\n+ .name = TYPE_XLNX_PMU_IO_INTC,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(XlnxPMUIOIntc),\n+ .class_init = xlnx_pmu_io_intc_class_init,\n+ .instance_init = xlnx_pmu_io_intc_init,\n+};\n+\n+static void xlnx_pmu_io_intc_register_types(void)\n+{\n+ type_register_static(&xlnx_pmu_io_intc_info);\n+}\n+\n+type_init(xlnx_pmu_io_intc_register_types)\ndiff --git a/include/hw/intc/xlnx-pmu-iomod-intc.h b/include/hw/intc/xlnx-pmu-iomod-intc.h\nnew file mode 100644\nindex 0000000000..3478d8cf6c\n--- /dev/null\n+++ b/include/hw/intc/xlnx-pmu-iomod-intc.h\n@@ -0,0 +1,58 @@\n+/*\n+ * QEMU model of Xilinx I/O Module Interrupt Controller\n+ *\n+ * Copyright (c) 2014 Xilinx Inc.\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#ifndef XLNX_PMU_IO_INTC_H\n+#define XLNX_PMU_IO_INTC_H\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/sysbus.h\"\n+#include \"hw/register.h\"\n+\n+#define TYPE_XLNX_PMU_IO_INTC \"xlnx.pmu_io_intc\"\n+\n+#define XLNX_PMU_IO_INTC(obj) \\\n+ OBJECT_CHECK(XlnxPMUIOIntc, (obj), TYPE_XLNX_PMU_IO_INTC)\n+\n+/* This is R_PIT3_CONTROL + 1 */\n+#define XlnxPMUIOIntc_R_MAX (0x78 + 1)\n+\n+typedef struct XlnxPMUIOIntc {\n+ SysBusDevice parent_obj;\n+ MemoryRegion iomem;\n+\n+ qemu_irq parent_irq;\n+\n+ struct {\n+ uint32_t intr_size;\n+ uint32_t level_edge;\n+ uint32_t positive;\n+ } cfg;\n+\n+ uint32_t irq_raw;\n+\n+ uint32_t regs[XlnxPMUIOIntc_R_MAX];\n+ RegisterInfo regs_info[XlnxPMUIOIntc_R_MAX];\n+} XlnxPMUIOIntc;\n+\n+#endif /* XLNX_PMU_IO_INTC_H */\n", "prefixes": [ "v3", "4/8" ] }