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GET /api/patches/816435/?format=api
{ "id": 816435, "url": "http://patchwork.ozlabs.org/api/patches/816435/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170920194934.23071-7-f4bug@amsat.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170920194934.23071-7-f4bug@amsat.org>", "list_archive_url": null, "date": "2017-09-20T19:49:34", "name": "[v4,6/6] mips: replace cpu_mips_init() with cpu_generic_init()", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a73a3670f882a13ed5225d8e2f3316e24c60e0e7", "submitter": { "id": 70924, "url": "http://patchwork.ozlabs.org/api/people/70924/?format=api", "name": "Philippe Mathieu-Daudé", "email": "f4bug@amsat.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170920194934.23071-7-f4bug@amsat.org/mbox/", "series": [ { "id": 4216, "url": "http://patchwork.ozlabs.org/api/series/4216/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4216", "date": "2017-09-20T19:49:28", "name": "QOMify MIPS cpu", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/4216/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816435/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816435/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"PabheXvu\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xy9WD0xC4z9sRV\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 21 Sep 2017 05:57:12 +1000 (AEST)", "from localhost ([::1]:50415 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dul73-0000dF-Gn\n\tfor incoming@patchwork.ozlabs.org; Wed, 20 Sep 2017 15:56:49 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:37932)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dul0c-0004SO-HT\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 15:50:11 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dul0X-0008Hk-Rv\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 15:50:10 -0400", "from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:35746)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dul0X-0008Gi-M5\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 15:50:05 -0400", "by mail-qt0-x241.google.com with SMTP id l25so2418089qtf.2\n\tfor <qemu-devel@nongnu.org>; Wed, 20 Sep 2017 12:50:05 -0700 (PDT)", "from yoga.offpageads.com ([181.93.89.178])\n\tby smtp.gmail.com with ESMTPSA id\n\ti84sm1952792qkh.17.2017.09.20.12.50.01\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 20 Sep 2017 12:50:03 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=PiqxucuauzVumsplSifEYGfHH8d5Q609nZtt/wUnhxc=;\n\tb=PabheXvuBQ+Qeb9V7TS0umdaaIzptWYhDOV3419Hs90YhgSo8njrK6RnMpEu7L8OFf\n\tRjqB3sSV2w1LFi/hGREbKMUbSpVjp+Q/wz4By++1Im3kz+WhC1IJD4j8OH+zLNlbpN4N\n\tjhefAqwvvErlJeFvz/yGOb9zoFuYA+4pg/Qo1NuMfWpfqXFDxERScsNNdMorybCNq+kH\n\tq1szvgk3iKYBtsXw0qFampZ21b5PDeZLDZxqPNJiV4b4kWfQjTlBOzLAJrJ7dSQ20+md\n\tPfXt/TTbGy/ZMRrDMqQtbUCWP4RSvbwkmxRKWKYmO9jVnuk2BJLEKulD+b4+9jsbKGKZ\n\tOcGQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references:mime-version:content-transfer-encoding;\n\tbh=PiqxucuauzVumsplSifEYGfHH8d5Q609nZtt/wUnhxc=;\n\tb=Q2cJIDLH9wKJ6mYrpYsy7C1+/5VT+zKYfOWYfe7HYrbG/V4DwhpYdP/t2IvRcila+f\n\tvF6c5ctGheuDyLceZR09RKkUpzUv0uJtnzFBUYnRDFn+h4oWsCBAhhfKE+gps3FSG2R9\n\t8bYN4XIavx1ekSpfyS3dygLGPd6y3JQ58GIZTWR4C3TOuKxyXKeQq3ff+ms5fu0cjrCC\n\t2e/qdC1rm8uMIICeisbqG6/U321NqjoSoQMKn18+QCjhmNN81hBbf21RjmCLRB5PIXHB\n\t5rAI6cLSkqmEmKOV56DZZPKLJ8Be4SCNsdp2YuAeIhh7h3PV0efydgHFXhXjU63hNzV8\n\tLygg==", "X-Gm-Message-State": "AHPjjUiKD3M9Zw8O8z7NjJ8PrEPoO2eh46otW3JUF3lvuCZLCvVjd4iS\n\tWhaXR3oQ+o+uvQFqVXMABks=", "X-Google-Smtp-Source": "AOwi7QAU2cjmoL//6EVzuCt1Nt+Txazts2QjGhtcxEHitA/UOLebCxIbMsDlRh+RVU9yqc2dwfh4tQ==", "X-Received": "by 10.237.42.167 with SMTP id t36mr8908877qtd.320.1505937005125; \n\tWed, 20 Sep 2017 12:50:05 -0700 (PDT)", "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>", "To": "Igor Mammedov <imammedo@redhat.com>,\n\tEduardo Habkost <ehabkost@redhat.com>, \n\tAurelien Jarno <aurelien@aurel32.net>,\n\tYongbok Kim <yongbok.kim@imgtec.com>,\n\tMarcel Apfelbaum <marcel@redhat.com>", "Date": "Wed, 20 Sep 2017 16:49:34 -0300", "Message-Id": "<20170920194934.23071-7-f4bug@amsat.org>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170920194934.23071-1-f4bug@amsat.org>", "References": "<20170920194934.23071-1-f4bug@amsat.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400d:c0d::241", "Subject": "[Qemu-devel] [PATCH v4 6/6] mips: replace cpu_mips_init() with\n\tcpu_generic_init()", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Thomas Huth <thuth@redhat.com>, James Hogan <james.hogan@imgtec.com>,\n\t=?utf-8?q?Herv=C3=A9_Poussineau?= <hpoussin@reactos.org>,\n\tqemu-devel@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?=\n\t<f4bug@amsat.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Igor Mammedov <imammedo@redhat.com>\n\nnow cpu_mips_init() reimplements subset of cpu_generic_init()\ntasks, so just drop it and use cpu_generic_init() directly.\n\nSigned-off-by: Igor Mammedov <imammedo@redhat.com>\nReviewed-by: Hervé Poussineau <hpoussin@reactos.org>\nSigned-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\n[PMD: use internal.h instead of cpu.h]\nTested-by: James Hogan <james.hogan@imgtec.com>\nReviewed-by: Eduardo Habkost <ehabkost@redhat.com>\n---\n target/mips/cpu.h | 3 +--\n hw/mips/cps.c | 2 +-\n hw/mips/mips_fulong2e.c | 2 +-\n hw/mips/mips_jazz.c | 2 +-\n hw/mips/mips_malta.c | 2 +-\n hw/mips/mips_mipssim.c | 2 +-\n hw/mips/mips_r4k.c | 2 +-\n target/mips/translate.c | 17 -----------------\n 8 files changed, 7 insertions(+), 25 deletions(-)", "diff": "diff --git a/target/mips/cpu.h b/target/mips/cpu.h\nindex 2f81e0f950..66265e4eb6 100644\n--- a/target/mips/cpu.h\n+++ b/target/mips/cpu.h\n@@ -737,10 +737,9 @@ enum {\n */\n #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0\n \n-MIPSCPU *cpu_mips_init(const char *cpu_model);\n int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);\n \n-#define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))\n+#define cpu_init(cpu_model) cpu_generic_init(TYPE_MIPS_CPU, cpu_model)\n bool cpu_supports_cps_smp(const char *cpu_model);\n bool cpu_supports_isa(const char *cpu_model, unsigned int isa);\n void cpu_set_exception_base(int vp_index, target_ulong address);\ndiff --git a/hw/mips/cps.c b/hw/mips/cps.c\nindex 79d4c5e30a..fe5c630af6 100644\n--- a/hw/mips/cps.c\n+++ b/hw/mips/cps.c\n@@ -71,7 +71,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)\n bool itu_present = false;\n \n for (i = 0; i < s->num_vp; i++) {\n- cpu = cpu_mips_init(s->cpu_model);\n+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, s->cpu_model));\n \n /* Init internal devices */\n cpu_mips_irq_init_cpu(cpu);\ndiff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c\nindex 439a3d7a66..75318680e1 100644\n--- a/hw/mips/mips_fulong2e.c\n+++ b/hw/mips/mips_fulong2e.c\n@@ -280,7 +280,7 @@ static void mips_fulong2e_init(MachineState *machine)\n if (cpu_model == NULL) {\n cpu_model = \"Loongson-2E\";\n }\n- cpu = cpu_mips_init(cpu_model);\n+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));\n env = &cpu->env;\n \n qemu_register_reset(main_cpu_reset, cpu);\ndiff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c\nindex ae10670efd..7e6626dc88 100644\n--- a/hw/mips/mips_jazz.c\n+++ b/hw/mips/mips_jazz.c\n@@ -151,7 +151,7 @@ static void mips_jazz_init(MachineState *machine,\n if (cpu_model == NULL) {\n cpu_model = \"R4000\";\n }\n- cpu = cpu_mips_init(cpu_model);\n+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));\n env = &cpu->env;\n qemu_register_reset(main_cpu_reset, cpu);\n \ndiff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c\nindex e87cd3230b..2adb9bcf89 100644\n--- a/hw/mips/mips_malta.c\n+++ b/hw/mips/mips_malta.c\n@@ -931,7 +931,7 @@ static void create_cpu_without_cps(const char *cpu_model,\n int i;\n \n for (i = 0; i < smp_cpus; i++) {\n- cpu = cpu_mips_init(cpu_model);\n+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));\n \n /* Init internal devices */\n cpu_mips_irq_init_cpu(cpu);\ndiff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c\nindex 49cd38d680..a092072e2a 100644\n--- a/hw/mips/mips_mipssim.c\n+++ b/hw/mips/mips_mipssim.c\n@@ -163,7 +163,7 @@ mips_mipssim_init(MachineState *machine)\n cpu_model = \"24Kf\";\n #endif\n }\n- cpu = cpu_mips_init(cpu_model);\n+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));\n env = &cpu->env;\n \n reset_info = g_malloc0(sizeof(ResetData));\ndiff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c\nindex 7efee94431..1272d4ef9d 100644\n--- a/hw/mips/mips_r4k.c\n+++ b/hw/mips/mips_r4k.c\n@@ -193,7 +193,7 @@ void mips_r4k_init(MachineState *machine)\n cpu_model = \"24Kf\";\n #endif\n }\n- cpu = cpu_mips_init(cpu_model);\n+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));\n env = &cpu->env;\n \n reset_info = g_malloc0(sizeof(ResetData));\ndiff --git a/target/mips/translate.c b/target/mips/translate.c\nindex f7128bc91d..d16d879df7 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -20523,23 +20523,6 @@ void cpu_mips_realize_env(CPUMIPSState *env)\n mvp_init(env, env->cpu_model);\n }\n \n-MIPSCPU *cpu_mips_init(const char *cpu_model)\n-{\n- ObjectClass *oc;\n- MIPSCPU *cpu;\n-\n- oc = cpu_class_by_name(TYPE_MIPS_CPU, cpu_model);\n- if (oc == NULL) {\n- return NULL;\n- }\n-\n- cpu = MIPS_CPU(object_new(object_class_get_name(oc)));\n-\n- object_property_set_bool(OBJECT(cpu), true, \"realized\", NULL);\n-\n- return cpu;\n-}\n-\n bool cpu_supports_cps_smp(const char *cpu_model)\n {\n const mips_def_t *def = cpu_mips_find_by_name(cpu_model);\n", "prefixes": [ "v4", "6/6" ] }