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GET /api/patches/816420/?format=api
{ "id": 816420, "url": "http://patchwork.ozlabs.org/api/patches/816420/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170920193831.20268-5-jernej.skrabec@siol.net/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170920193831.20268-5-jernej.skrabec@siol.net>", "list_archive_url": null, "date": "2017-09-20T19:38:28", "name": "[RFC,4/7] dt-bindings: Document Allwinner DWC HDMI TX node", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cf1fc662558b19532bace73d4513b4dc2e790415", "submitter": { "id": 70601, "url": "http://patchwork.ozlabs.org/api/people/70601/?format=api", "name": "Jernej Škrabec", "email": "jernej.skrabec@siol.net" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170920193831.20268-5-jernej.skrabec@siol.net/mbox/", "series": [ { "id": 4208, "url": "http://patchwork.ozlabs.org/api/series/4208/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4208", "date": "2017-09-20T19:38:24", "name": "sun8i H3 HDMI glue driver for DW HDMI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4208/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816420/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816420/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xy97s68yZz9s8J\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 21 Sep 2017 05:40:25 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751707AbdITTi6 (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tWed, 20 Sep 2017 15:38:58 -0400", "from mailoutvs7.siol.net ([213.250.19.138]:43687 \"EHLO\n\tmail.siol.net\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1751175AbdITTiz (ORCPT <rfc822;devicetree@vger.kernel.org>);\n\tWed, 20 Sep 2017 15:38:55 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.siol.net (Postfix) with ESMTP id 2E76D5284FE;\n\tWed, 20 Sep 2017 21:39:00 +0200 (CEST)", "from mail.siol.net ([127.0.0.1])\n\tby localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, \n\tport 10032)\n\twith ESMTP id HCLqoR7zG_cB; Wed, 20 Sep 2017 21:38:59 +0200 (CEST)", "from mail.siol.net (localhost [127.0.0.1])\n\tby mail.siol.net (Postfix) with ESMTPS id 650925284FF;\n\tWed, 20 Sep 2017 21:38:59 +0200 (CEST)", "from localhost.localdomain (cpe-86-58-68-135.ftth.triera.net\n\t[86.58.68.135]) (Authenticated sender: 031275009)\n\tby mail.siol.net (Postfix) with ESMTPSA id 0193E5284FE;\n\tWed, 20 Sep 2017 21:38:56 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at psrvmta11.zcs-production.pri", "From": "Jernej Skrabec <jernej.skrabec@siol.net>", "To": "maxime.ripard@free-electrons.com, wens@csie.org", "Cc": "Laurent.pinchart@ideasonboard.com, narmstrong@baylibre.com,\n\tdri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, icenowy@aosc.io, linux-sunxi@googlegroups.com", "Subject": "[RFC PATCH 4/7] dt-bindings: Document Allwinner DWC HDMI TX node", "Date": "Wed, 20 Sep 2017 21:38:28 +0200", "Message-Id": "<20170920193831.20268-5-jernej.skrabec@siol.net>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170920193831.20268-1-jernej.skrabec@siol.net>", "References": "<20170920193831.20268-1-jernej.skrabec@siol.net>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Add documentation about Allwinner DWC HDMI TX node, found in H3 SoC.\n\nSigned-off-by: Jernej Skrabec <jernej.skrabec@siol.net>\n---\n .../bindings/display/sunxi/sun4i-drm.txt | 158 ++++++++++++++++++++-\n 1 file changed, 157 insertions(+), 1 deletion(-)", "diff": "diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt\nindex 92512953943e..cb6aee5c486f 100644\n--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt\n+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt\n@@ -60,6 +60,40 @@ Required properties:\n first port should be the input endpoint. The second should be the\n output, usually to an HDMI connector.\n \n+DWC HDMI TX Encoder\n+-----------------------------\n+\n+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP\n+with Allwinner's own PHY IP. It supports audio and video outputs and CEC.\n+\n+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in\n+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the\n+following device-specific properties.\n+\n+Required properties:\n+\n+ - compatible: value must be one of:\n+ * \"allwinner,sun8i-h3-dw-hdmi\"\n+ - reg: two pairs of base address and size of memory-mapped region, first\n+ for controller and second for PHY\n+ registers.\n+ - reg-io-width: See dw_hdmi.txt. Shall be 1.\n+ - interrupts: HDMI interrupt number\n+ - clocks: phandles to the clocks feeding the HDMI encoder\n+ * iahb: the HDMI interface clock\n+ * isfr: the HDMI module clock\n+ * ddc: the HDMI ddc clock\n+ - clock-names: the clock names mentioned above\n+ - resets: phandles to the reset controllers driving the encoder\n+ * hdmi: the reset line for the HDMI\n+ * ddc: the reset line for the DDC\n+ - reset-names: the reset names mentioned above\n+\n+ - ports: A ports node with endpoint definitions as defined in\n+ Documentation/devicetree/bindings/media/video-interfaces.txt. The\n+ first port should be the input endpoint. The second should be the\n+ output, usually to an HDMI connector.\n+\n TV Encoder\n ----------\n \n@@ -255,7 +289,7 @@ Required properties:\n - allwinner,pipelines: list of phandle to the display engine\n frontends (DE 1.0) or mixers (DE 2.0) available.\n \n-Example:\n+Example 1:\n \n panel: panel {\n \tcompatible = \"olimex,lcd-olinuxino-43-ts\";\n@@ -455,3 +489,125 @@ display-engine {\n \tcompatible = \"allwinner,sun5i-a13-display-engine\";\n \tallwinner,pipelines = <&fe0>;\n };\n+\n+Example 2:\n+\n+connector {\n+\tcompatible = \"hdmi-connector\";\n+\ttype = \"a\";\n+\n+\tport {\n+\t\thdmi_con_in: endpoint {\n+\t\t\tremote-endpoint = <&hdmi_out_con>;\n+\t\t};\n+\t};\n+};\n+\n+de: display-engine {\n+\tcompatible = \"allwinner,sun8i-h3-display-engine\";\n+\tallwinner,pipelines = <&mixer0>;\n+};\n+\n+hdmi: hdmi@1ee0000 {\n+\tcompatible = \"allwinner,h3-dw-hdmi\";\n+\treg = <0x01ee0000 0x10000>,\n+\t <0x01ef0000 0x10000>;\n+\treg-io-width = <1>;\n+\tinterrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;\n+\tclocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI>,\n+\t\t <&ccu CLK_HDMI_DDC>;\n+\tclock-names = \"iahb\", \"isfr\", \"ddc\";\n+\tresets = <&ccu RST_BUS_HDMI0>, <&ccu RST_BUS_HDMI1>;\n+\treset-names = \"hdmi\", \"ddc\";\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\thdmi_in: port@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\n+\t\t\thdmi_in_tcon0: endpoint@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tremote-endpoint = <&tcon0_out_hdmi>;\n+\t\t\t};\n+\t\t};\n+\n+\t\thdmi_out: port@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\n+\t\t\thdmi_out_con: endpoint {\n+\t\t\t\tremote-endpoint = <&hdmi_con_in>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+mixer0: mixer@1100000 {\n+\tcompatible = \"allwinner,sun8i-h3-de2-mixer0\";\n+\treg = <0x01100000 0x100000>;\n+\tclocks = <&display_clocks CLK_BUS_MIXER0>,\n+\t\t <&display_clocks CLK_MIXER0>;\n+\tclock-names = \"bus\",\n+\t\t \"mod\";\n+\tresets = <&display_clocks RST_MIXER0>;\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tmixer0_out: port@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\n+\t\t\tmixer0_out_tcon0: endpoint@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tremote-endpoint = <&tcon0_in_mixer0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+tcon0: lcd-controller@1c0c000 {\n+\tcompatible = \"allwinner,sun8i-h3-tcon\";\n+\treg = <0x01c0c000 0x1000>;\n+\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n+\tclocks = <&ccu CLK_BUS_TCON0>,\n+\t\t <&ccu CLK_TCON0>;\n+\tclock-names = \"ahb\",\n+\t\t \"tcon-ch1\";\n+\tresets = <&ccu RST_BUS_TCON0>;\n+\treset-names = \"lcd\";\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\ttcon0_in: port@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\n+\t\t\ttcon0_in_mixer0: endpoint@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tremote-endpoint = <&mixer0_out_tcon0>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ttcon0_out: port@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\n+\t\t\ttcon0_out_hdmi: endpoint@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tremote-endpoint = <&hdmi_in_tcon0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n", "prefixes": [ "RFC", "4/7" ] }