Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 816218,
    "url": "http://patchwork.ozlabs.org/api/patches/816218/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170920133927.17390-4-jbrunet@baylibre.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170920133927.17390-4-jbrunet@baylibre.com>",
    "list_archive_url": null,
    "date": "2017-09-20T13:39:22",
    "name": "[3/8] pinctrl: meson: remove offset continued - gxl",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "87558eafab0835b630ef3a1c0829db08090e2eee",
    "submitter": {
        "id": 69839,
        "url": "http://patchwork.ozlabs.org/api/people/69839/?format=api",
        "name": "Jerome Brunet",
        "email": "jbrunet@baylibre.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170920133927.17390-4-jbrunet@baylibre.com/mbox/",
    "series": [
        {
            "id": 4115,
            "url": "http://patchwork.ozlabs.org/api/series/4115/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=4115",
            "date": "2017-09-20T13:39:19",
            "name": "pinctrl: meson: clean pin offsets",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/4115/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/816218/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/816218/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-gpio-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": [
            "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
            "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=baylibre-com.20150623.gappssmtp.com\n\theader.i=@baylibre-com.20150623.gappssmtp.com\n\theader.b=\"U1RdIVz1\"; dkim-atps=neutral"
        ],
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xy17k5gngz9sP1\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 20 Sep 2017 23:39:46 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751758AbdITNjo (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 20 Sep 2017 09:39:44 -0400",
            "from mail-wr0-f170.google.com ([209.85.128.170]:56152 \"EHLO\n\tmail-wr0-f170.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751612AbdITNjl (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Wed, 20 Sep 2017 09:39:41 -0400",
            "by mail-wr0-f170.google.com with SMTP id l39so2194590wrl.12\n\tfor <linux-gpio@vger.kernel.org>;\n\tWed, 20 Sep 2017 06:39:40 -0700 (PDT)",
            "from localhost.localdomain ([90.63.244.31])\n\tby smtp.googlemail.com with ESMTPSA id\n\ta39sm1938888wrc.48.2017.09.20.06.39.38\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 20 Sep 2017 06:39:38 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=baylibre-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=noJRcXBhMklG9HUJM/FdbI7IM8BbOHD7HUzoxTto+SI=;\n\tb=U1RdIVz1HY+5sPfJmWTkyambHU0z0RYQQGc61L0C7rEFr3kG8hzxYZh+CsfzHRWQ3Z\n\tqtJuxmqfx8Mg4IEs0cpAV467ldpIdldabBILYNJOc89loZfnXJqA9icp7T+Nvx1BU2LL\n\tfT8DLDVffMOrAA60fzgx46x3GPtedeNRvAd7eiLzelu2ehe1IPJq45EnghPJ+VHgBVGI\n\tW9MPC7vi+GNML8yRWVSND7Q0UCJidmY6klMCjD5Kc+OwrtOnGDB+8nGwrtKYLIYfWzYW\n\tCGSa6WcdrtCCBAJACAY6ouUiXeMOfTUysIJpKJNkPBuJWZy2gDg0o0hVzCPcTXRy59Yw\n\t4eow==",
        "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=noJRcXBhMklG9HUJM/FdbI7IM8BbOHD7HUzoxTto+SI=;\n\tb=JHrOBt7Q+dnceefDFOMbXcX9EgH1QdcXZ4pMMlVNuqEUHhJpgHAj+bUd/PhsEPeRAo\n\t4dx4LdvAcWENNojbkGIB66eaBCenWoDYcWu81Ngi7bTDIDPcKwV94NaeDx49MODorElA\n\tl5WDopVMQmqpHzF9pYKvCeYOQKBfgmpP10l88e+se4LFC1VTBfpKSTONKdD/WLOS0km+\n\tZoCZOts9Qh4pXEjdHjxbAjMOpsC/gye5DfcQQ3oH0pouV0guxXJ1e8UQ7n9qeKjDGkBo\n\tbC++o1vsQJ7HWd96NsF5ISy3NGw455V3LpgOwWwtA5qHSHvSothzYRKlk7S4FDhnP5qd\n\t7YwA==",
        "X-Gm-Message-State": "AHPjjUgoWfzBOpKJJR/C06W0JAKH2WjOjRN76ipbk24gzMXsGXY5lKg9\n\tn+mDjD7f9emcXIm2wCTDzOLs9NmM",
        "X-Google-Smtp-Source": "AOwi7QD3KbeoMh4GR9ZW5EoM850LgD8Kge53FhPye6eI9OyiSeU3coeqw/eOPsFpw+WF/mYivk7oJg==",
        "X-Received": "by 10.223.174.141 with SMTP id y13mr4354713wrc.209.1505914779420;\n\tWed, 20 Sep 2017 06:39:39 -0700 (PDT)",
        "From": "Jerome Brunet <jbrunet@baylibre.com>",
        "To": "Linus Walleij <linus.walleij@linaro.org>,\n\tKevin Hilman <khilman@baylibre.com>, Carlo Caione <carlo@caione.org>",
        "Cc": "Jerome Brunet <jbrunet@baylibre.com>, linux-gpio@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tMartin Blumenstingl <martin.blumenstingl@googlemail.com>",
        "Subject": "[PATCH 3/8] pinctrl: meson: remove offset continued - gxl",
        "Date": "Wed, 20 Sep 2017 15:39:22 +0200",
        "Message-Id": "<20170920133927.17390-4-jbrunet@baylibre.com>",
        "X-Mailer": "git-send-email 2.13.5",
        "In-Reply-To": "<20170920133927.17390-1-jbrunet@baylibre.com>",
        "References": "<20170920133927.17390-1-jbrunet@baylibre.com>",
        "Sender": "linux-gpio-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-gpio.vger.kernel.org>",
        "X-Mailing-List": "linux-gpio@vger.kernel.org"
    },
    "content": "Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>\n---\n drivers/pinctrl/meson/pinctrl-meson-gxl.c | 814 +++++++++++++++---------------\n 1 file changed, 402 insertions(+), 412 deletions(-)",
    "diff": "diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c\nindex 36c14b85fc7c..32e35ba9c04e 100644\n--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c\n+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c\n@@ -15,407 +15,397 @@\n #include <dt-bindings/gpio/meson-gxl-gpio.h>\n #include \"pinctrl-meson.h\"\n \n-#define EE_OFF\t10\n-\n static const struct pinctrl_pin_desc meson_gxl_periphs_pins[] = {\n-\tMESON_PIN(GPIOZ_0, EE_OFF),\n-\tMESON_PIN(GPIOZ_1, EE_OFF),\n-\tMESON_PIN(GPIOZ_2, EE_OFF),\n-\tMESON_PIN(GPIOZ_3, EE_OFF),\n-\tMESON_PIN(GPIOZ_4, EE_OFF),\n-\tMESON_PIN(GPIOZ_5, EE_OFF),\n-\tMESON_PIN(GPIOZ_6, EE_OFF),\n-\tMESON_PIN(GPIOZ_7, EE_OFF),\n-\tMESON_PIN(GPIOZ_8, EE_OFF),\n-\tMESON_PIN(GPIOZ_9, EE_OFF),\n-\tMESON_PIN(GPIOZ_10, EE_OFF),\n-\tMESON_PIN(GPIOZ_11, EE_OFF),\n-\tMESON_PIN(GPIOZ_12, EE_OFF),\n-\tMESON_PIN(GPIOZ_13, EE_OFF),\n-\tMESON_PIN(GPIOZ_14, EE_OFF),\n-\tMESON_PIN(GPIOZ_15, EE_OFF),\n-\n-\tMESON_PIN(GPIOH_0, EE_OFF),\n-\tMESON_PIN(GPIOH_1, EE_OFF),\n-\tMESON_PIN(GPIOH_2, EE_OFF),\n-\tMESON_PIN(GPIOH_3, EE_OFF),\n-\tMESON_PIN(GPIOH_4, EE_OFF),\n-\tMESON_PIN(GPIOH_5, EE_OFF),\n-\tMESON_PIN(GPIOH_6, EE_OFF),\n-\tMESON_PIN(GPIOH_7, EE_OFF),\n-\tMESON_PIN(GPIOH_8, EE_OFF),\n-\tMESON_PIN(GPIOH_9, EE_OFF),\n-\n-\tMESON_PIN(BOOT_0, EE_OFF),\n-\tMESON_PIN(BOOT_1, EE_OFF),\n-\tMESON_PIN(BOOT_2, EE_OFF),\n-\tMESON_PIN(BOOT_3, EE_OFF),\n-\tMESON_PIN(BOOT_4, EE_OFF),\n-\tMESON_PIN(BOOT_5, EE_OFF),\n-\tMESON_PIN(BOOT_6, EE_OFF),\n-\tMESON_PIN(BOOT_7, EE_OFF),\n-\tMESON_PIN(BOOT_8, EE_OFF),\n-\tMESON_PIN(BOOT_9, EE_OFF),\n-\tMESON_PIN(BOOT_10, EE_OFF),\n-\tMESON_PIN(BOOT_11, EE_OFF),\n-\tMESON_PIN(BOOT_12, EE_OFF),\n-\tMESON_PIN(BOOT_13, EE_OFF),\n-\tMESON_PIN(BOOT_14, EE_OFF),\n-\tMESON_PIN(BOOT_15, EE_OFF),\n-\n-\tMESON_PIN(CARD_0, EE_OFF),\n-\tMESON_PIN(CARD_1, EE_OFF),\n-\tMESON_PIN(CARD_2, EE_OFF),\n-\tMESON_PIN(CARD_3, EE_OFF),\n-\tMESON_PIN(CARD_4, EE_OFF),\n-\tMESON_PIN(CARD_5, EE_OFF),\n-\tMESON_PIN(CARD_6, EE_OFF),\n-\n-\tMESON_PIN(GPIODV_0, EE_OFF),\n-\tMESON_PIN(GPIODV_1, EE_OFF),\n-\tMESON_PIN(GPIODV_2, EE_OFF),\n-\tMESON_PIN(GPIODV_3, EE_OFF),\n-\tMESON_PIN(GPIODV_4, EE_OFF),\n-\tMESON_PIN(GPIODV_5, EE_OFF),\n-\tMESON_PIN(GPIODV_6, EE_OFF),\n-\tMESON_PIN(GPIODV_7, EE_OFF),\n-\tMESON_PIN(GPIODV_8, EE_OFF),\n-\tMESON_PIN(GPIODV_9, EE_OFF),\n-\tMESON_PIN(GPIODV_10, EE_OFF),\n-\tMESON_PIN(GPIODV_11, EE_OFF),\n-\tMESON_PIN(GPIODV_12, EE_OFF),\n-\tMESON_PIN(GPIODV_13, EE_OFF),\n-\tMESON_PIN(GPIODV_14, EE_OFF),\n-\tMESON_PIN(GPIODV_15, EE_OFF),\n-\tMESON_PIN(GPIODV_16, EE_OFF),\n-\tMESON_PIN(GPIODV_17, EE_OFF),\n-\tMESON_PIN(GPIODV_18, EE_OFF),\n-\tMESON_PIN(GPIODV_19, EE_OFF),\n-\tMESON_PIN(GPIODV_20, EE_OFF),\n-\tMESON_PIN(GPIODV_21, EE_OFF),\n-\tMESON_PIN(GPIODV_22, EE_OFF),\n-\tMESON_PIN(GPIODV_23, EE_OFF),\n-\tMESON_PIN(GPIODV_24, EE_OFF),\n-\tMESON_PIN(GPIODV_25, EE_OFF),\n-\tMESON_PIN(GPIODV_26, EE_OFF),\n-\tMESON_PIN(GPIODV_27, EE_OFF),\n-\tMESON_PIN(GPIODV_28, EE_OFF),\n-\tMESON_PIN(GPIODV_29, EE_OFF),\n-\n-\tMESON_PIN(GPIOX_0, EE_OFF),\n-\tMESON_PIN(GPIOX_1, EE_OFF),\n-\tMESON_PIN(GPIOX_2, EE_OFF),\n-\tMESON_PIN(GPIOX_3, EE_OFF),\n-\tMESON_PIN(GPIOX_4, EE_OFF),\n-\tMESON_PIN(GPIOX_5, EE_OFF),\n-\tMESON_PIN(GPIOX_6, EE_OFF),\n-\tMESON_PIN(GPIOX_7, EE_OFF),\n-\tMESON_PIN(GPIOX_8, EE_OFF),\n-\tMESON_PIN(GPIOX_9, EE_OFF),\n-\tMESON_PIN(GPIOX_10, EE_OFF),\n-\tMESON_PIN(GPIOX_11, EE_OFF),\n-\tMESON_PIN(GPIOX_12, EE_OFF),\n-\tMESON_PIN(GPIOX_13, EE_OFF),\n-\tMESON_PIN(GPIOX_14, EE_OFF),\n-\tMESON_PIN(GPIOX_15, EE_OFF),\n-\tMESON_PIN(GPIOX_16, EE_OFF),\n-\tMESON_PIN(GPIOX_17, EE_OFF),\n-\tMESON_PIN(GPIOX_18, EE_OFF),\n-\n-\tMESON_PIN(GPIOCLK_0, EE_OFF),\n-\tMESON_PIN(GPIOCLK_1, EE_OFF),\n-\n-\tMESON_PIN(GPIO_TEST_N, EE_OFF),\n+\tMESON_PIN(GPIOZ_0),\n+\tMESON_PIN(GPIOZ_1),\n+\tMESON_PIN(GPIOZ_2),\n+\tMESON_PIN(GPIOZ_3),\n+\tMESON_PIN(GPIOZ_4),\n+\tMESON_PIN(GPIOZ_5),\n+\tMESON_PIN(GPIOZ_6),\n+\tMESON_PIN(GPIOZ_7),\n+\tMESON_PIN(GPIOZ_8),\n+\tMESON_PIN(GPIOZ_9),\n+\tMESON_PIN(GPIOZ_10),\n+\tMESON_PIN(GPIOZ_11),\n+\tMESON_PIN(GPIOZ_12),\n+\tMESON_PIN(GPIOZ_13),\n+\tMESON_PIN(GPIOZ_14),\n+\tMESON_PIN(GPIOZ_15),\n+\n+\tMESON_PIN(GPIOH_0),\n+\tMESON_PIN(GPIOH_1),\n+\tMESON_PIN(GPIOH_2),\n+\tMESON_PIN(GPIOH_3),\n+\tMESON_PIN(GPIOH_4),\n+\tMESON_PIN(GPIOH_5),\n+\tMESON_PIN(GPIOH_6),\n+\tMESON_PIN(GPIOH_7),\n+\tMESON_PIN(GPIOH_8),\n+\tMESON_PIN(GPIOH_9),\n+\n+\tMESON_PIN(BOOT_0),\n+\tMESON_PIN(BOOT_1),\n+\tMESON_PIN(BOOT_2),\n+\tMESON_PIN(BOOT_3),\n+\tMESON_PIN(BOOT_4),\n+\tMESON_PIN(BOOT_5),\n+\tMESON_PIN(BOOT_6),\n+\tMESON_PIN(BOOT_7),\n+\tMESON_PIN(BOOT_8),\n+\tMESON_PIN(BOOT_9),\n+\tMESON_PIN(BOOT_10),\n+\tMESON_PIN(BOOT_11),\n+\tMESON_PIN(BOOT_12),\n+\tMESON_PIN(BOOT_13),\n+\tMESON_PIN(BOOT_14),\n+\tMESON_PIN(BOOT_15),\n+\n+\tMESON_PIN(CARD_0),\n+\tMESON_PIN(CARD_1),\n+\tMESON_PIN(CARD_2),\n+\tMESON_PIN(CARD_3),\n+\tMESON_PIN(CARD_4),\n+\tMESON_PIN(CARD_5),\n+\tMESON_PIN(CARD_6),\n+\n+\tMESON_PIN(GPIODV_0),\n+\tMESON_PIN(GPIODV_1),\n+\tMESON_PIN(GPIODV_2),\n+\tMESON_PIN(GPIODV_3),\n+\tMESON_PIN(GPIODV_4),\n+\tMESON_PIN(GPIODV_5),\n+\tMESON_PIN(GPIODV_6),\n+\tMESON_PIN(GPIODV_7),\n+\tMESON_PIN(GPIODV_8),\n+\tMESON_PIN(GPIODV_9),\n+\tMESON_PIN(GPIODV_10),\n+\tMESON_PIN(GPIODV_11),\n+\tMESON_PIN(GPIODV_12),\n+\tMESON_PIN(GPIODV_13),\n+\tMESON_PIN(GPIODV_14),\n+\tMESON_PIN(GPIODV_15),\n+\tMESON_PIN(GPIODV_16),\n+\tMESON_PIN(GPIODV_17),\n+\tMESON_PIN(GPIODV_18),\n+\tMESON_PIN(GPIODV_19),\n+\tMESON_PIN(GPIODV_20),\n+\tMESON_PIN(GPIODV_21),\n+\tMESON_PIN(GPIODV_22),\n+\tMESON_PIN(GPIODV_23),\n+\tMESON_PIN(GPIODV_24),\n+\tMESON_PIN(GPIODV_25),\n+\tMESON_PIN(GPIODV_26),\n+\tMESON_PIN(GPIODV_27),\n+\tMESON_PIN(GPIODV_28),\n+\tMESON_PIN(GPIODV_29),\n+\n+\tMESON_PIN(GPIOX_0),\n+\tMESON_PIN(GPIOX_1),\n+\tMESON_PIN(GPIOX_2),\n+\tMESON_PIN(GPIOX_3),\n+\tMESON_PIN(GPIOX_4),\n+\tMESON_PIN(GPIOX_5),\n+\tMESON_PIN(GPIOX_6),\n+\tMESON_PIN(GPIOX_7),\n+\tMESON_PIN(GPIOX_8),\n+\tMESON_PIN(GPIOX_9),\n+\tMESON_PIN(GPIOX_10),\n+\tMESON_PIN(GPIOX_11),\n+\tMESON_PIN(GPIOX_12),\n+\tMESON_PIN(GPIOX_13),\n+\tMESON_PIN(GPIOX_14),\n+\tMESON_PIN(GPIOX_15),\n+\tMESON_PIN(GPIOX_16),\n+\tMESON_PIN(GPIOX_17),\n+\tMESON_PIN(GPIOX_18),\n+\n+\tMESON_PIN(GPIOCLK_0),\n+\tMESON_PIN(GPIOCLK_1),\n+\n+\tMESON_PIN(GPIO_TEST_N),\n };\n \n static const unsigned int emmc_nand_d07_pins[] = {\n-\tPIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),\n-\tPIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),\n-\tPIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),\n-};\n-static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };\n-static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };\n-static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };\n-\n-static const unsigned int nor_d_pins[]\t\t= { PIN(BOOT_11, EE_OFF) };\n-static const unsigned int nor_q_pins[]\t\t= { PIN(BOOT_12, EE_OFF) };\n-static const unsigned int nor_c_pins[]\t\t= { PIN(BOOT_13, EE_OFF) };\n-static const unsigned int nor_cs_pins[]\t\t= { PIN(BOOT_15, EE_OFF) };\n-\n-static const unsigned int spi_mosi_pins[]\t= { PIN(GPIOX_8, EE_OFF) };\n-static const unsigned int spi_miso_pins[]\t= { PIN(GPIOX_9, EE_OFF) };\n-static const unsigned int spi_ss0_pins[]\t= { PIN(GPIOX_10, EE_OFF) };\n-static const unsigned int spi_sclk_pins[]\t= { PIN(GPIOX_11, EE_OFF) };\n-\n-static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };\n-static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };\n-static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };\n-static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };\n-static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };\n-static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };\n-\n-static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) };\n-static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) };\n-static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) };\n-static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) };\n-static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) };\n-static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) };\n-static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) };\n-\n-static const unsigned int nand_ce0_pins[]\t= { PIN(BOOT_8, EE_OFF) };\n-static const unsigned int nand_ce1_pins[]\t= { PIN(BOOT_9, EE_OFF) };\n-static const unsigned int nand_rb0_pins[]\t= { PIN(BOOT_10, EE_OFF) };\n-static const unsigned int nand_ale_pins[]\t= { PIN(BOOT_11, EE_OFF) };\n-static const unsigned int nand_cle_pins[]\t= { PIN(BOOT_12, EE_OFF) };\n-static const unsigned int nand_wen_clk_pins[]\t= { PIN(BOOT_13, EE_OFF) };\n-static const unsigned int nand_ren_wr_pins[]\t= { PIN(BOOT_14, EE_OFF) };\n-static const unsigned int nand_dqs_pins[]\t= { PIN(BOOT_15, EE_OFF) };\n-\n-static const unsigned int uart_tx_a_pins[]\t= { PIN(GPIOX_12, EE_OFF) };\n-static const unsigned int uart_rx_a_pins[]\t= { PIN(GPIOX_13, EE_OFF) };\n-static const unsigned int uart_cts_a_pins[]\t= { PIN(GPIOX_14, EE_OFF) };\n-static const unsigned int uart_rts_a_pins[]\t= { PIN(GPIOX_15, EE_OFF) };\n-\n-static const unsigned int uart_tx_b_pins[]\t= { PIN(GPIODV_24, EE_OFF) };\n-static const unsigned int uart_rx_b_pins[]\t= { PIN(GPIODV_25, EE_OFF) };\n-static const unsigned int uart_cts_b_pins[]\t= { PIN(GPIODV_26, EE_OFF) };\n-static const unsigned int uart_rts_b_pins[]\t= { PIN(GPIODV_27, EE_OFF) };\n-\n-static const unsigned int uart_tx_c_pins[]\t= { PIN(GPIOX_8, EE_OFF) };\n-static const unsigned int uart_rx_c_pins[]\t= { PIN(GPIOX_9, EE_OFF) };\n-static const unsigned int uart_cts_c_pins[]\t= { PIN(GPIOX_10, EE_OFF) };\n-static const unsigned int uart_rts_c_pins[]\t= { PIN(GPIOX_11, EE_OFF) };\n-\n-static const unsigned int i2c_sck_a_pins[]\t= { PIN(GPIODV_25, EE_OFF) };\n-static const unsigned int i2c_sda_a_pins[]\t= { PIN(GPIODV_24, EE_OFF) };\n-\n-static const unsigned int i2c_sck_b_pins[]\t= { PIN(GPIODV_27, EE_OFF) };\n-static const unsigned int i2c_sda_b_pins[]\t= { PIN(GPIODV_26, EE_OFF) };\n-\n-static const unsigned int i2c_sck_c_pins[]\t= { PIN(GPIODV_29, EE_OFF) };\n-static const unsigned int i2c_sda_c_pins[]\t= { PIN(GPIODV_28, EE_OFF) };\n-\n-static const unsigned int i2c_sck_c_dv19_pins[]\t= { PIN(GPIODV_19, EE_OFF) };\n-static const unsigned int i2c_sda_c_dv18_pins[]\t= { PIN(GPIODV_18, EE_OFF) };\n-\n-static const unsigned int eth_mdio_pins[]\t= { PIN(GPIOZ_0, EE_OFF) };\n-static const unsigned int eth_mdc_pins[]\t= { PIN(GPIOZ_1, EE_OFF) };\n-static const unsigned int eth_clk_rx_clk_pins[]\t= { PIN(GPIOZ_2, EE_OFF) };\n-static const unsigned int eth_rx_dv_pins[]\t= { PIN(GPIOZ_3, EE_OFF) };\n-static const unsigned int eth_rxd0_pins[]\t= { PIN(GPIOZ_4, EE_OFF) };\n-static const unsigned int eth_rxd1_pins[]\t= { PIN(GPIOZ_5, EE_OFF) };\n-static const unsigned int eth_rxd2_pins[]\t= { PIN(GPIOZ_6, EE_OFF) };\n-static const unsigned int eth_rxd3_pins[]\t= { PIN(GPIOZ_7, EE_OFF) };\n-static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) };\n-static const unsigned int eth_tx_en_pins[]\t= { PIN(GPIOZ_9, EE_OFF) };\n-static const unsigned int eth_txd0_pins[]\t= { PIN(GPIOZ_10, EE_OFF) };\n-static const unsigned int eth_txd1_pins[]\t= { PIN(GPIOZ_11, EE_OFF) };\n-static const unsigned int eth_txd2_pins[]\t= { PIN(GPIOZ_12, EE_OFF) };\n-static const unsigned int eth_txd3_pins[]\t= { PIN(GPIOZ_13, EE_OFF) };\n-\n-static const unsigned int pwm_a_pins[]\t\t= { PIN(GPIOX_6, EE_OFF) };\n-\n-static const unsigned int pwm_b_pins[]\t\t= { PIN(GPIODV_29, EE_OFF) };\n-\n-static const unsigned int pwm_c_pins[]\t\t= { PIN(GPIOZ_15, EE_OFF) };\n-\n-static const unsigned int pwm_d_pins[]\t\t= { PIN(GPIODV_28, EE_OFF) };\n-\n-static const unsigned int pwm_e_pins[]\t\t= { PIN(GPIOX_16, EE_OFF) };\n-\n-static const unsigned int pwm_f_clk_pins[]\t= { PIN(GPIOCLK_1, EE_OFF) };\n-static const unsigned int pwm_f_x_pins[]\t= { PIN(GPIOX_7, EE_OFF) };\n-\n-static const unsigned int hdmi_hpd_pins[]\t= { PIN(GPIOH_0, EE_OFF) };\n-static const unsigned int hdmi_sda_pins[]\t= { PIN(GPIOH_1, EE_OFF) };\n-static const unsigned int hdmi_scl_pins[]\t= { PIN(GPIOH_2, EE_OFF) };\n-\n-static const unsigned int i2s_am_clk_pins[]\t= { PIN(GPIOH_6, EE_OFF) };\n-static const unsigned int i2s_out_ao_clk_pins[]\t= { PIN(GPIOH_7, EE_OFF) };\n-static const unsigned int i2s_out_lr_clk_pins[]\t= { PIN(GPIOH_8, EE_OFF) };\n-static const unsigned int i2s_out_ch01_pins[]\t= { PIN(GPIOH_9, EE_OFF) };\n-static const unsigned int i2s_out_ch23_z_pins[]\t= { PIN(GPIOZ_5, EE_OFF) };\n-static const unsigned int i2s_out_ch45_z_pins[]\t= { PIN(GPIOZ_6, EE_OFF) };\n-static const unsigned int i2s_out_ch67_z_pins[]\t= { PIN(GPIOZ_7, EE_OFF) };\n-\n-static const unsigned int spdif_out_h_pins[]\t= { PIN(GPIOH_4, EE_OFF) };\n-\n-static const unsigned int eth_link_led_pins[]\t= { PIN(GPIOZ_14, EE_OFF) };\n-static const unsigned int eth_act_led_pins[]\t= { PIN(GPIOZ_15, EE_OFF) };\n-\n-static const unsigned int tsin_a_d0_pins[]\t= { PIN(GPIODV_0, EE_OFF) };\n-static const unsigned int tsin_a_d0_x_pins[]\t= { PIN(GPIOX_10, EE_OFF) };\n-static const unsigned int tsin_a_clk_pins[]\t= { PIN(GPIODV_8, EE_OFF) };\n-static const unsigned int tsin_a_clk_x_pins[]\t= { PIN(GPIOX_11, EE_OFF) };\n-static const unsigned int tsin_a_sop_pins[]\t= { PIN(GPIODV_9, EE_OFF) };\n-static const unsigned int tsin_a_sop_x_pins[]\t= { PIN(GPIOX_8, EE_OFF) };\n-static const unsigned int tsin_a_d_valid_pins[]\t= { PIN(GPIODV_10, EE_OFF) };\n-static const unsigned int tsin_a_d_valid_x_pins[] = { PIN(GPIOX_9, EE_OFF) };\n-static const unsigned int tsin_a_fail_pins[]\t= { PIN(GPIODV_11, EE_OFF) };\n+\tBOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7,\n+};\n+static const unsigned int emmc_clk_pins[]\t= { BOOT_8 };\n+static const unsigned int emmc_cmd_pins[]\t= { BOOT_10 };\n+static const unsigned int emmc_ds_pins[]\t= { BOOT_15 };\n+\n+static const unsigned int nor_d_pins[]\t\t= { BOOT_11 };\n+static const unsigned int nor_q_pins[]\t\t= { BOOT_12 };\n+static const unsigned int nor_c_pins[]\t\t= { BOOT_13 };\n+static const unsigned int nor_cs_pins[]\t\t= { BOOT_15 };\n+\n+static const unsigned int spi_mosi_pins[]\t= { GPIOX_8 };\n+static const unsigned int spi_miso_pins[]\t= { GPIOX_9 };\n+static const unsigned int spi_ss0_pins[]\t= { GPIOX_10 };\n+static const unsigned int spi_sclk_pins[]\t= { GPIOX_11 };\n+\n+static const unsigned int sdcard_d0_pins[]\t= { CARD_1 };\n+static const unsigned int sdcard_d1_pins[]\t= { CARD_0 };\n+static const unsigned int sdcard_d2_pins[]\t= { CARD_5 };\n+static const unsigned int sdcard_d3_pins[]\t= { CARD_4 };\n+static const unsigned int sdcard_cmd_pins[]\t= { CARD_3 };\n+static const unsigned int sdcard_clk_pins[]\t= { CARD_2 };\n+\n+static const unsigned int sdio_d0_pins[]\t= { GPIOX_0 };\n+static const unsigned int sdio_d1_pins[]\t= { GPIOX_1 };\n+static const unsigned int sdio_d2_pins[]\t= { GPIOX_2 };\n+static const unsigned int sdio_d3_pins[]\t= { GPIOX_3 };\n+static const unsigned int sdio_cmd_pins[]\t= { GPIOX_4 };\n+static const unsigned int sdio_clk_pins[]\t= { GPIOX_5 };\n+static const unsigned int sdio_irq_pins[]\t= { GPIOX_7 };\n+\n+static const unsigned int nand_ce0_pins[]\t= { BOOT_8 };\n+static const unsigned int nand_ce1_pins[]\t= { BOOT_9 };\n+static const unsigned int nand_rb0_pins[]\t= { BOOT_10 };\n+static const unsigned int nand_ale_pins[]\t= { BOOT_11 };\n+static const unsigned int nand_cle_pins[]\t= { BOOT_12 };\n+static const unsigned int nand_wen_clk_pins[]\t= { BOOT_13 };\n+static const unsigned int nand_ren_wr_pins[]\t= { BOOT_14 };\n+static const unsigned int nand_dqs_pins[]\t= { BOOT_15 };\n+\n+static const unsigned int uart_tx_a_pins[]\t= { GPIOX_12 };\n+static const unsigned int uart_rx_a_pins[]\t= { GPIOX_13 };\n+static const unsigned int uart_cts_a_pins[]\t= { GPIOX_14 };\n+static const unsigned int uart_rts_a_pins[]\t= { GPIOX_15 };\n+\n+static const unsigned int uart_tx_b_pins[]\t= { GPIODV_24 };\n+static const unsigned int uart_rx_b_pins[]\t= { GPIODV_25 };\n+static const unsigned int uart_cts_b_pins[]\t= { GPIODV_26 };\n+static const unsigned int uart_rts_b_pins[]\t= { GPIODV_27 };\n+\n+static const unsigned int uart_tx_c_pins[]\t= { GPIOX_8 };\n+static const unsigned int uart_rx_c_pins[]\t= { GPIOX_9 };\n+static const unsigned int uart_cts_c_pins[]\t= { GPIOX_10 };\n+static const unsigned int uart_rts_c_pins[]\t= { GPIOX_11 };\n+\n+static const unsigned int i2c_sck_a_pins[]\t= { GPIODV_25 };\n+static const unsigned int i2c_sda_a_pins[]\t= { GPIODV_24 };\n+\n+static const unsigned int i2c_sck_b_pins[]\t= { GPIODV_27 };\n+static const unsigned int i2c_sda_b_pins[]\t= { GPIODV_26 };\n+\n+static const unsigned int i2c_sck_c_pins[]\t= { GPIODV_29 };\n+static const unsigned int i2c_sda_c_pins[]\t= { GPIODV_28 };\n+\n+static const unsigned int i2c_sck_c_dv19_pins[] = { GPIODV_19 };\n+static const unsigned int i2c_sda_c_dv18_pins[] = { GPIODV_18 };\n+\n+static const unsigned int eth_mdio_pins[]\t= { GPIOZ_0 };\n+static const unsigned int eth_mdc_pins[]\t= { GPIOZ_1 };\n+static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 };\n+static const unsigned int eth_rx_dv_pins[]\t= { GPIOZ_3 };\n+static const unsigned int eth_rxd0_pins[]\t= { GPIOZ_4 };\n+static const unsigned int eth_rxd1_pins[]\t= { GPIOZ_5 };\n+static const unsigned int eth_rxd2_pins[]\t= { GPIOZ_6 };\n+static const unsigned int eth_rxd3_pins[]\t= { GPIOZ_7 };\n+static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 };\n+static const unsigned int eth_tx_en_pins[]\t= { GPIOZ_9 };\n+static const unsigned int eth_txd0_pins[]\t= { GPIOZ_10 };\n+static const unsigned int eth_txd1_pins[]\t= { GPIOZ_11 };\n+static const unsigned int eth_txd2_pins[]\t= { GPIOZ_12 };\n+static const unsigned int eth_txd3_pins[]\t= { GPIOZ_13 };\n+\n+static const unsigned int pwm_a_pins[]\t\t= { GPIOX_6 };\n+\n+static const unsigned int pwm_b_pins[]\t\t= { GPIODV_29 };\n+\n+static const unsigned int pwm_c_pins[]\t\t= { GPIOZ_15 };\n+\n+static const unsigned int pwm_d_pins[]\t\t= { GPIODV_28 };\n+\n+static const unsigned int pwm_e_pins[]\t\t= { GPIOX_16 };\n+\n+static const unsigned int pwm_f_clk_pins[]\t= { GPIOCLK_1 };\n+static const unsigned int pwm_f_x_pins[]\t= { GPIOX_7 };\n+\n+static const unsigned int hdmi_hpd_pins[]\t= { GPIOH_0 };\n+static const unsigned int hdmi_sda_pins[]\t= { GPIOH_1 };\n+static const unsigned int hdmi_scl_pins[]\t= { GPIOH_2 };\n+\n+static const unsigned int i2s_am_clk_pins[]\t= { GPIOH_6 };\n+static const unsigned int i2s_out_ao_clk_pins[] = { GPIOH_7 };\n+static const unsigned int i2s_out_lr_clk_pins[] = { GPIOH_8 };\n+static const unsigned int i2s_out_ch01_pins[]\t= { GPIOH_9 };\n+static const unsigned int i2s_out_ch23_z_pins[] = { GPIOZ_5 };\n+static const unsigned int i2s_out_ch45_z_pins[] = { GPIOZ_6 };\n+static const unsigned int i2s_out_ch67_z_pins[] = { GPIOZ_7 };\n+\n+static const unsigned int spdif_out_h_pins[]\t= { GPIOH_4 };\n+\n+static const unsigned int eth_link_led_pins[]\t= { GPIOZ_14 };\n+static const unsigned int eth_act_led_pins[]\t= { GPIOZ_15 };\n+\n+static const unsigned int tsin_a_d0_pins[]\t= { GPIODV_0 };\n+static const unsigned int tsin_a_d0_x_pins[]\t= { GPIOX_10 };\n+static const unsigned int tsin_a_clk_pins[]\t= { GPIODV_8 };\n+static const unsigned int tsin_a_clk_x_pins[]\t= { GPIOX_11 };\n+static const unsigned int tsin_a_sop_pins[]\t= { GPIODV_9 };\n+static const unsigned int tsin_a_sop_x_pins[]\t= { GPIOX_8 };\n+static const unsigned int tsin_a_d_valid_pins[] = { GPIODV_10 };\n+static const unsigned int tsin_a_d_valid_x_pins[] = { GPIOX_9 };\n+static const unsigned int tsin_a_fail_pins[]\t= { GPIODV_11 };\n static const unsigned int tsin_a_dp_pins[] = {\n-\tPIN(GPIODV_1, EE_OFF),\n-\tPIN(GPIODV_2, EE_OFF),\n-\tPIN(GPIODV_3, EE_OFF),\n-\tPIN(GPIODV_4, EE_OFF),\n-\tPIN(GPIODV_5, EE_OFF),\n-\tPIN(GPIODV_6, EE_OFF),\n-\tPIN(GPIODV_7, EE_OFF),\n+\tGPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7,\n };\n \n static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = {\n-\tMESON_PIN(GPIOAO_0, 0),\n-\tMESON_PIN(GPIOAO_1, 0),\n-\tMESON_PIN(GPIOAO_2, 0),\n-\tMESON_PIN(GPIOAO_3, 0),\n-\tMESON_PIN(GPIOAO_4, 0),\n-\tMESON_PIN(GPIOAO_5, 0),\n-\tMESON_PIN(GPIOAO_6, 0),\n-\tMESON_PIN(GPIOAO_7, 0),\n-\tMESON_PIN(GPIOAO_8, 0),\n-\tMESON_PIN(GPIOAO_9, 0),\n-};\n-\n-static const unsigned int uart_tx_ao_a_pins[]\t= { PIN(GPIOAO_0, 0) };\n-static const unsigned int uart_rx_ao_a_pins[]\t= { PIN(GPIOAO_1, 0) };\n-static const unsigned int uart_tx_ao_b_0_pins[]\t= { PIN(GPIOAO_0, 0) };\n-static const unsigned int uart_rx_ao_b_1_pins[]\t= { PIN(GPIOAO_1, 0) };\n-static const unsigned int uart_cts_ao_a_pins[]\t= { PIN(GPIOAO_2, 0) };\n-static const unsigned int uart_rts_ao_a_pins[]\t= { PIN(GPIOAO_3, 0) };\n-static const unsigned int uart_tx_ao_b_pins[]\t= { PIN(GPIOAO_4, 0) };\n-static const unsigned int uart_rx_ao_b_pins[]\t= { PIN(GPIOAO_5, 0) };\n-static const unsigned int uart_cts_ao_b_pins[]\t= { PIN(GPIOAO_2, 0) };\n-static const unsigned int uart_rts_ao_b_pins[]\t= { PIN(GPIOAO_3, 0) };\n-\n-static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };\n-static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };\n-static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };\n-static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };\n-\n-static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) };\n-\n-static const unsigned int pwm_ao_a_3_pins[]\t= { PIN(GPIOAO_3, 0) };\n-static const unsigned int pwm_ao_a_8_pins[]\t= { PIN(GPIOAO_8, 0) };\n-\n-static const unsigned int pwm_ao_b_pins[]\t= { PIN(GPIOAO_9, 0) };\n-static const unsigned int pwm_ao_b_6_pins[]\t= { PIN(GPIOAO_6, 0) };\n-\n-static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_8, 0) };\n-static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_9, 0) };\n-\n-static const unsigned int spdif_out_ao_6_pins[]\t= { PIN(GPIOAO_6, 0) };\n-static const unsigned int spdif_out_ao_9_pins[]\t= { PIN(GPIOAO_9, 0) };\n-\n-static const unsigned int ao_cec_pins[]\t\t= { PIN(GPIOAO_8, 0) };\n-static const unsigned int ee_cec_pins[]\t\t= { PIN(GPIOAO_8, 0) };\n+\tMESON_PIN(GPIOAO_0),\n+\tMESON_PIN(GPIOAO_1),\n+\tMESON_PIN(GPIOAO_2),\n+\tMESON_PIN(GPIOAO_3),\n+\tMESON_PIN(GPIOAO_4),\n+\tMESON_PIN(GPIOAO_5),\n+\tMESON_PIN(GPIOAO_6),\n+\tMESON_PIN(GPIOAO_7),\n+\tMESON_PIN(GPIOAO_8),\n+\tMESON_PIN(GPIOAO_9),\n+};\n+\n+static const unsigned int uart_tx_ao_a_pins[]\t= { GPIOAO_0 };\n+static const unsigned int uart_rx_ao_a_pins[]\t= { GPIOAO_1 };\n+static const unsigned int uart_tx_ao_b_0_pins[] = { GPIOAO_0 };\n+static const unsigned int uart_rx_ao_b_1_pins[] = { GPIOAO_1 };\n+static const unsigned int uart_cts_ao_a_pins[]\t= { GPIOAO_2 };\n+static const unsigned int uart_rts_ao_a_pins[]\t= { GPIOAO_3 };\n+static const unsigned int uart_tx_ao_b_pins[]\t= { GPIOAO_4 };\n+static const unsigned int uart_rx_ao_b_pins[]\t= { GPIOAO_5 };\n+static const unsigned int uart_cts_ao_b_pins[]\t= { GPIOAO_2 };\n+static const unsigned int uart_rts_ao_b_pins[]\t= { GPIOAO_3 };\n+\n+static const unsigned int i2c_sck_ao_pins[]\t= {GPIOAO_4 };\n+static const unsigned int i2c_sda_ao_pins[]\t= {GPIOAO_5 };\n+static const unsigned int i2c_slave_sck_ao_pins[] = {GPIOAO_4 };\n+static const unsigned int i2c_slave_sda_ao_pins[] = {GPIOAO_5 };\n+\n+static const unsigned int remote_input_ao_pins[] = {GPIOAO_7 };\n+\n+static const unsigned int pwm_ao_a_3_pins[]\t= { GPIOAO_3 };\n+static const unsigned int pwm_ao_a_8_pins[]\t= { GPIOAO_8 };\n+\n+static const unsigned int pwm_ao_b_pins[]\t= { GPIOAO_9 };\n+static const unsigned int pwm_ao_b_6_pins[]\t= { GPIOAO_6 };\n+\n+static const unsigned int i2s_out_ch23_ao_pins[] = { GPIOAO_8 };\n+static const unsigned int i2s_out_ch45_ao_pins[] = { GPIOAO_9 };\n+\n+static const unsigned int spdif_out_ao_6_pins[] = { GPIOAO_6 };\n+static const unsigned int spdif_out_ao_9_pins[] = { GPIOAO_9 };\n+\n+static const unsigned int ao_cec_pins[]\t\t= { GPIOAO_8 };\n+static const unsigned int ee_cec_pins[]\t\t= { GPIOAO_8 };\n \n static struct meson_pmx_group meson_gxl_periphs_groups[] = {\n-\tGPIO_GROUP(GPIOZ_0, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_1, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_2, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_3, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_4, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_5, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_6, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_7, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_8, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_9, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_10, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_11, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_12, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_13, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_14, EE_OFF),\n-\tGPIO_GROUP(GPIOZ_15, EE_OFF),\n-\n-\tGPIO_GROUP(GPIOH_0, EE_OFF),\n-\tGPIO_GROUP(GPIOH_1, EE_OFF),\n-\tGPIO_GROUP(GPIOH_2, EE_OFF),\n-\tGPIO_GROUP(GPIOH_3, EE_OFF),\n-\tGPIO_GROUP(GPIOH_4, EE_OFF),\n-\tGPIO_GROUP(GPIOH_5, EE_OFF),\n-\tGPIO_GROUP(GPIOH_6, EE_OFF),\n-\tGPIO_GROUP(GPIOH_7, EE_OFF),\n-\tGPIO_GROUP(GPIOH_8, EE_OFF),\n-\tGPIO_GROUP(GPIOH_9, EE_OFF),\n-\n-\tGPIO_GROUP(BOOT_0, EE_OFF),\n-\tGPIO_GROUP(BOOT_1, EE_OFF),\n-\tGPIO_GROUP(BOOT_2, EE_OFF),\n-\tGPIO_GROUP(BOOT_3, EE_OFF),\n-\tGPIO_GROUP(BOOT_4, EE_OFF),\n-\tGPIO_GROUP(BOOT_5, EE_OFF),\n-\tGPIO_GROUP(BOOT_6, EE_OFF),\n-\tGPIO_GROUP(BOOT_7, EE_OFF),\n-\tGPIO_GROUP(BOOT_8, EE_OFF),\n-\tGPIO_GROUP(BOOT_9, EE_OFF),\n-\tGPIO_GROUP(BOOT_10, EE_OFF),\n-\tGPIO_GROUP(BOOT_11, EE_OFF),\n-\tGPIO_GROUP(BOOT_12, EE_OFF),\n-\tGPIO_GROUP(BOOT_13, EE_OFF),\n-\tGPIO_GROUP(BOOT_14, EE_OFF),\n-\tGPIO_GROUP(BOOT_15, EE_OFF),\n-\n-\tGPIO_GROUP(CARD_0, EE_OFF),\n-\tGPIO_GROUP(CARD_1, EE_OFF),\n-\tGPIO_GROUP(CARD_2, EE_OFF),\n-\tGPIO_GROUP(CARD_3, EE_OFF),\n-\tGPIO_GROUP(CARD_4, EE_OFF),\n-\tGPIO_GROUP(CARD_5, EE_OFF),\n-\tGPIO_GROUP(CARD_6, EE_OFF),\n-\n-\tGPIO_GROUP(GPIODV_0, EE_OFF),\n-\tGPIO_GROUP(GPIODV_1, EE_OFF),\n-\tGPIO_GROUP(GPIODV_2, EE_OFF),\n-\tGPIO_GROUP(GPIODV_3, EE_OFF),\n-\tGPIO_GROUP(GPIODV_4, EE_OFF),\n-\tGPIO_GROUP(GPIODV_5, EE_OFF),\n-\tGPIO_GROUP(GPIODV_6, EE_OFF),\n-\tGPIO_GROUP(GPIODV_7, EE_OFF),\n-\tGPIO_GROUP(GPIODV_8, EE_OFF),\n-\tGPIO_GROUP(GPIODV_9, EE_OFF),\n-\tGPIO_GROUP(GPIODV_10, EE_OFF),\n-\tGPIO_GROUP(GPIODV_11, EE_OFF),\n-\tGPIO_GROUP(GPIODV_12, EE_OFF),\n-\tGPIO_GROUP(GPIODV_13, EE_OFF),\n-\tGPIO_GROUP(GPIODV_14, EE_OFF),\n-\tGPIO_GROUP(GPIODV_15, EE_OFF),\n-\tGPIO_GROUP(GPIODV_16, EE_OFF),\n-\tGPIO_GROUP(GPIODV_17, EE_OFF),\n-\tGPIO_GROUP(GPIODV_19, EE_OFF),\n-\tGPIO_GROUP(GPIODV_20, EE_OFF),\n-\tGPIO_GROUP(GPIODV_21, EE_OFF),\n-\tGPIO_GROUP(GPIODV_22, EE_OFF),\n-\tGPIO_GROUP(GPIODV_23, EE_OFF),\n-\tGPIO_GROUP(GPIODV_24, EE_OFF),\n-\tGPIO_GROUP(GPIODV_25, EE_OFF),\n-\tGPIO_GROUP(GPIODV_26, EE_OFF),\n-\tGPIO_GROUP(GPIODV_27, EE_OFF),\n-\tGPIO_GROUP(GPIODV_28, EE_OFF),\n-\tGPIO_GROUP(GPIODV_29, EE_OFF),\n-\n-\tGPIO_GROUP(GPIOX_0, EE_OFF),\n-\tGPIO_GROUP(GPIOX_1, EE_OFF),\n-\tGPIO_GROUP(GPIOX_2, EE_OFF),\n-\tGPIO_GROUP(GPIOX_3, EE_OFF),\n-\tGPIO_GROUP(GPIOX_4, EE_OFF),\n-\tGPIO_GROUP(GPIOX_5, EE_OFF),\n-\tGPIO_GROUP(GPIOX_6, EE_OFF),\n-\tGPIO_GROUP(GPIOX_7, EE_OFF),\n-\tGPIO_GROUP(GPIOX_8, EE_OFF),\n-\tGPIO_GROUP(GPIOX_9, EE_OFF),\n-\tGPIO_GROUP(GPIOX_10, EE_OFF),\n-\tGPIO_GROUP(GPIOX_11, EE_OFF),\n-\tGPIO_GROUP(GPIOX_12, EE_OFF),\n-\tGPIO_GROUP(GPIOX_13, EE_OFF),\n-\tGPIO_GROUP(GPIOX_14, EE_OFF),\n-\tGPIO_GROUP(GPIOX_15, EE_OFF),\n-\tGPIO_GROUP(GPIOX_16, EE_OFF),\n-\tGPIO_GROUP(GPIOX_17, EE_OFF),\n-\tGPIO_GROUP(GPIOX_18, EE_OFF),\n-\n-\tGPIO_GROUP(GPIOCLK_0, EE_OFF),\n-\tGPIO_GROUP(GPIOCLK_1, EE_OFF),\n-\n-\tGPIO_GROUP(GPIO_TEST_N, EE_OFF),\n+\tGPIO_GROUP(GPIOZ_0),\n+\tGPIO_GROUP(GPIOZ_1),\n+\tGPIO_GROUP(GPIOZ_2),\n+\tGPIO_GROUP(GPIOZ_3),\n+\tGPIO_GROUP(GPIOZ_4),\n+\tGPIO_GROUP(GPIOZ_5),\n+\tGPIO_GROUP(GPIOZ_6),\n+\tGPIO_GROUP(GPIOZ_7),\n+\tGPIO_GROUP(GPIOZ_8),\n+\tGPIO_GROUP(GPIOZ_9),\n+\tGPIO_GROUP(GPIOZ_10),\n+\tGPIO_GROUP(GPIOZ_11),\n+\tGPIO_GROUP(GPIOZ_12),\n+\tGPIO_GROUP(GPIOZ_13),\n+\tGPIO_GROUP(GPIOZ_14),\n+\tGPIO_GROUP(GPIOZ_15),\n+\n+\tGPIO_GROUP(GPIOH_0),\n+\tGPIO_GROUP(GPIOH_1),\n+\tGPIO_GROUP(GPIOH_2),\n+\tGPIO_GROUP(GPIOH_3),\n+\tGPIO_GROUP(GPIOH_4),\n+\tGPIO_GROUP(GPIOH_5),\n+\tGPIO_GROUP(GPIOH_6),\n+\tGPIO_GROUP(GPIOH_7),\n+\tGPIO_GROUP(GPIOH_8),\n+\tGPIO_GROUP(GPIOH_9),\n+\n+\tGPIO_GROUP(BOOT_0),\n+\tGPIO_GROUP(BOOT_1),\n+\tGPIO_GROUP(BOOT_2),\n+\tGPIO_GROUP(BOOT_3),\n+\tGPIO_GROUP(BOOT_4),\n+\tGPIO_GROUP(BOOT_5),\n+\tGPIO_GROUP(BOOT_6),\n+\tGPIO_GROUP(BOOT_7),\n+\tGPIO_GROUP(BOOT_8),\n+\tGPIO_GROUP(BOOT_9),\n+\tGPIO_GROUP(BOOT_10),\n+\tGPIO_GROUP(BOOT_11),\n+\tGPIO_GROUP(BOOT_12),\n+\tGPIO_GROUP(BOOT_13),\n+\tGPIO_GROUP(BOOT_14),\n+\tGPIO_GROUP(BOOT_15),\n+\n+\tGPIO_GROUP(CARD_0),\n+\tGPIO_GROUP(CARD_1),\n+\tGPIO_GROUP(CARD_2),\n+\tGPIO_GROUP(CARD_3),\n+\tGPIO_GROUP(CARD_4),\n+\tGPIO_GROUP(CARD_5),\n+\tGPIO_GROUP(CARD_6),\n+\n+\tGPIO_GROUP(GPIODV_0),\n+\tGPIO_GROUP(GPIODV_1),\n+\tGPIO_GROUP(GPIODV_2),\n+\tGPIO_GROUP(GPIODV_3),\n+\tGPIO_GROUP(GPIODV_4),\n+\tGPIO_GROUP(GPIODV_5),\n+\tGPIO_GROUP(GPIODV_6),\n+\tGPIO_GROUP(GPIODV_7),\n+\tGPIO_GROUP(GPIODV_8),\n+\tGPIO_GROUP(GPIODV_9),\n+\tGPIO_GROUP(GPIODV_10),\n+\tGPIO_GROUP(GPIODV_11),\n+\tGPIO_GROUP(GPIODV_12),\n+\tGPIO_GROUP(GPIODV_13),\n+\tGPIO_GROUP(GPIODV_14),\n+\tGPIO_GROUP(GPIODV_15),\n+\tGPIO_GROUP(GPIODV_16),\n+\tGPIO_GROUP(GPIODV_17),\n+\tGPIO_GROUP(GPIODV_19),\n+\tGPIO_GROUP(GPIODV_20),\n+\tGPIO_GROUP(GPIODV_21),\n+\tGPIO_GROUP(GPIODV_22),\n+\tGPIO_GROUP(GPIODV_23),\n+\tGPIO_GROUP(GPIODV_24),\n+\tGPIO_GROUP(GPIODV_25),\n+\tGPIO_GROUP(GPIODV_26),\n+\tGPIO_GROUP(GPIODV_27),\n+\tGPIO_GROUP(GPIODV_28),\n+\tGPIO_GROUP(GPIODV_29),\n+\n+\tGPIO_GROUP(GPIOX_0),\n+\tGPIO_GROUP(GPIOX_1),\n+\tGPIO_GROUP(GPIOX_2),\n+\tGPIO_GROUP(GPIOX_3),\n+\tGPIO_GROUP(GPIOX_4),\n+\tGPIO_GROUP(GPIOX_5),\n+\tGPIO_GROUP(GPIOX_6),\n+\tGPIO_GROUP(GPIOX_7),\n+\tGPIO_GROUP(GPIOX_8),\n+\tGPIO_GROUP(GPIOX_9),\n+\tGPIO_GROUP(GPIOX_10),\n+\tGPIO_GROUP(GPIOX_11),\n+\tGPIO_GROUP(GPIOX_12),\n+\tGPIO_GROUP(GPIOX_13),\n+\tGPIO_GROUP(GPIOX_14),\n+\tGPIO_GROUP(GPIOX_15),\n+\tGPIO_GROUP(GPIOX_16),\n+\tGPIO_GROUP(GPIOX_17),\n+\tGPIO_GROUP(GPIOX_18),\n+\n+\tGPIO_GROUP(GPIOCLK_0),\n+\tGPIO_GROUP(GPIOCLK_1),\n+\n+\tGPIO_GROUP(GPIO_TEST_N),\n \n \t/* Bank X */\n \tGROUP(sdio_d0,\t\t5,\t31),\n@@ -530,16 +520,16 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {\n };\n \n static struct meson_pmx_group meson_gxl_aobus_groups[] = {\n-\tGPIO_GROUP(GPIOAO_0, 0),\n-\tGPIO_GROUP(GPIOAO_1, 0),\n-\tGPIO_GROUP(GPIOAO_2, 0),\n-\tGPIO_GROUP(GPIOAO_3, 0),\n-\tGPIO_GROUP(GPIOAO_4, 0),\n-\tGPIO_GROUP(GPIOAO_5, 0),\n-\tGPIO_GROUP(GPIOAO_6, 0),\n-\tGPIO_GROUP(GPIOAO_7, 0),\n-\tGPIO_GROUP(GPIOAO_8, 0),\n-\tGPIO_GROUP(GPIOAO_9, 0),\n+\tGPIO_GROUP(GPIOAO_0),\n+\tGPIO_GROUP(GPIOAO_1),\n+\tGPIO_GROUP(GPIOAO_2),\n+\tGPIO_GROUP(GPIOAO_3),\n+\tGPIO_GROUP(GPIOAO_4),\n+\tGPIO_GROUP(GPIOAO_5),\n+\tGPIO_GROUP(GPIOAO_6),\n+\tGPIO_GROUP(GPIOAO_7),\n+\tGPIO_GROUP(GPIOAO_8),\n+\tGPIO_GROUP(GPIOAO_9),\n \n \t/* bank AO */\n \tGROUP(uart_tx_ao_b_0,\t0,\t26),\n@@ -800,24 +790,24 @@ static struct meson_pmx_func meson_gxl_aobus_functions[] = {\n };\n \n static struct meson_bank meson_gxl_periphs_banks[] = {\n-\t/*   name    first                      last                    irq\t  pullen  pull    dir     out     in  */\n-\tBANK(\"X\",    PIN(GPIOX_0, EE_OFF),\tPIN(GPIOX_18, EE_OFF),   89, 107, 4,  0,  4,  0,  12, 0,  13, 0,  14, 0),\n-\tBANK(\"DV\",   PIN(GPIODV_0, EE_OFF),\tPIN(GPIODV_29, EE_OFF),  83,  88, 0,  0,  0,  0,  0,  0,  1,  0,  2,  0),\n-\tBANK(\"H\",    PIN(GPIOH_0, EE_OFF),\tPIN(GPIOH_9, EE_OFF),    26,  35, 1, 20,  1, 20,  3, 20,  4, 20,  5, 20),\n-\tBANK(\"Z\",    PIN(GPIOZ_0, EE_OFF),\tPIN(GPIOZ_15, EE_OFF),   10,  25, 3,  0,  3,  0,  9,  0,  10, 0, 11,  0),\n-\tBANK(\"CARD\", PIN(CARD_0, EE_OFF),\tPIN(CARD_6, EE_OFF),     52,  58, 2, 20,  2, 20,  6, 20,  7, 20,  8, 20),\n-\tBANK(\"BOOT\", PIN(BOOT_0, EE_OFF),\tPIN(BOOT_15, EE_OFF),    36,  51, 2,  0,  2,  0,  6,  0,  7,  0,  8,  0),\n-\tBANK(\"CLK\",  PIN(GPIOCLK_0, EE_OFF),\tPIN(GPIOCLK_1, EE_OFF), 108, 109, 3, 28,  3, 28,  9, 28, 10, 28, 11, 28),\n+\t/*   name    first      last       irq\t     pullen  pull    dir     out     in  */\n+\tBANK(\"X\",    GPIOX_0,\tGPIOX_18,   89, 107, 4,  0,  4,  0,  12, 0,  13, 0,  14, 0),\n+\tBANK(\"DV\",   GPIODV_0,\tGPIODV_29,  83,  88, 0,  0,  0,  0,  0,  0,  1,  0,  2,  0),\n+\tBANK(\"H\",    GPIOH_0,\tGPIOH_9,    26,  35, 1, 20,  1, 20,  3, 20,  4, 20,  5, 20),\n+\tBANK(\"Z\",    GPIOZ_0,\tGPIOZ_15,   10,  25, 3,  0,  3,  0,  9,  0,  10, 0, 11,  0),\n+\tBANK(\"CARD\", CARD_0,\tCARD_6,     52,  58, 2, 20,  2, 20,  6, 20,  7, 20,  8, 20),\n+\tBANK(\"BOOT\", BOOT_0,\tBOOT_15,    36,  51, 2,  0,  2,  0,  6,  0,  7,  0,  8,  0),\n+\tBANK(\"CLK\",  GPIOCLK_0,\tGPIOCLK_1, 108, 109, 3, 28,  3, 28,  9, 28, 10, 28, 11, 28),\n };\n \n static struct meson_bank meson_gxl_aobus_banks[] = {\n-\t/*   name    first              last              irq\tpullen  pull    dir     out     in  */\n-\tBANK(\"AO\",   PIN(GPIOAO_0, 0),  PIN(GPIOAO_9, 0), 0, 9, 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),\n+\t/*   name    first      last      irq\tpullen  pull    dir     out     in  */\n+\tBANK(\"AO\",   GPIOAO_0,  GPIOAO_9, 0, 9, 0,  0,  0, 16,  0,  0,  0, 16,  1,  0),\n };\n \n struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {\n \t.name\t\t= \"periphs-banks\",\n-\t.pin_base\t= 10,\n+\t.pin_base\t= 0,\n \t.pins\t\t= meson_gxl_periphs_pins,\n \t.groups\t\t= meson_gxl_periphs_groups,\n \t.funcs\t\t= meson_gxl_periphs_functions,\n",
    "prefixes": [
        "3/8"
    ]
}