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GET /api/patches/815441/?format=api
{ "id": 815441, "url": "http://patchwork.ozlabs.org/api/patches/815441/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505818769-49370-1-git-send-email-david.wu@rock-chips.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505818769-49370-1-git-send-email-david.wu@rock-chips.com>", "list_archive_url": null, "date": "2017-09-19T10:59:29", "name": "[U-Boot,U-Boot,v2,07/14] clk: rockchip: Add rk3399 SARADC clock support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "447142b40b759802707cb7ce31fb0beffb2c6791", "submitter": { "id": 68083, "url": "http://patchwork.ozlabs.org/api/people/68083/?format=api", "name": "David Wu", "email": "david.wu@rock-chips.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505818769-49370-1-git-send-email-david.wu@rock-chips.com/mbox/", "series": [ { "id": 3839, "url": "http://patchwork.ozlabs.org/api/series/3839/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3839", "date": "2017-09-19T10:53:11", "name": "Add rockchip SARADC support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/3839/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815441/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815441/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxKfV3f8fz9s7m\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 21:00:34 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 2FF38C21FCD; Tue, 19 Sep 2017 11:00:22 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 9F301C21F22;\n\tTue, 19 Sep 2017 11:00:19 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid BE5FBC21F22; Tue, 19 Sep 2017 11:00:18 +0000 (UTC)", "from localhost by lists.denx.de with SpamAssassin (version 3.4.0); \n\tTue, 19 Sep 2017 11:00:18 +0000" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.0 required=5.0 tests=ALL_TRUSTED\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "From": "David Wu <david.wu@rock-chips.com>", "To": "sjg@chromium.org,\n\tphilipp.tomsich@theobroma-systems.com", "Date": "Tue, 19 Sep 2017 18:59:29 +0800", "Message-Id": "<1505818769-49370-1-git-send-email-david.wu@rock-chips.com>", "MIME-Version": "1.0", "Content-Type": "multipart/mixed; boundary=\"----------=_59C0F8C2.AF8D941A\"", "Cc": "huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, \n\tDavid Wu <david.wu@rock-chips.com>, andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com", "Subject": "[U-Boot] [U-Boot, v2,\n\t07/14] clk: rockchip: Add rk3399 SARADC clock support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Spam detection software, running on the system \"lists.denx.de\",\nhas identified this incoming email as possible spam. The original\nmessage has been attached to this so you can view it or label\nsimilar future email. If you have any questions, see\n@@CONTACT_ADDRESS@@ for details.\n\nContent preview: The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\n SARADC integer divider control register is 8-bits width. Signed-off-by: David\n Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\n Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> ---\n [...] \n\nContent analysis details: (6.9 points, 5.0 required)\n\n pts rule name description\n---- ---------------------- --------------------------------------------------\n 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server\n [58.22.7.114 listed in dnsbl.sorbs.net]\n 1.2 RCVD_IN_BL_SPAMCOP_NET RBL: Received via a relay in bl.spamcop.net\n [Blocked - see <http://www.spamcop.net/bl.shtml?58.22.7.114>]\n 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL\n [211.157.147.135 listed in psbl.surriel.com]\n 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5)\n [211.157.147.135 listed in bl.mailspike.net]\n 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted\nThe clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\nSARADC integer divider control register is 8-bits width.\n\nSigned-off-by: David Wu <david.wu@rock-chips.com>\nAcked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\nReviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\n---\n\nChange in v2:\n - Use GENMASK.\n\n drivers/clk/rockchip/clk_rk3399.c | 36 +++++++++++++++++++++++++++++++++++-\n 1 file changed, 35 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c\nindex 3edafea..105c499 100644\n--- a/drivers/clk/rockchip/clk_rk3399.c\n+++ b/drivers/clk/rockchip/clk_rk3399.c\n@@ -12,6 +12,7 @@\n #include <errno.h>\n #include <mapmem.h>\n #include <syscon.h>\n+#include <bitfield.h>\n #include <asm/io.h>\n #include <asm/arch/clock.h>\n #include <asm/arch/cru_rk3399.h>\n@@ -181,7 +182,8 @@ enum {\n \n \t/* CLKSEL_CON26 */\n \tCLK_SARADC_DIV_CON_SHIFT\t= 8,\n-\tCLK_SARADC_DIV_CON_MASK\t\t= 0xff << CLK_SARADC_DIV_CON_SHIFT,\n+\tCLK_SARADC_DIV_CON_MASK\t\t= GENMASK(15, 8),\n+\tCLK_SARADC_DIV_CON_WIDTH\t= 8,\n \n \t/* CLKSEL_CON27 */\n \tCLK_TSADC_SEL_X24M\t\t= 0x0,\n@@ -860,6 +862,32 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,\n \n \treturn set_rate;\n }\n+\n+static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)\n+{\n+\tu32 div, val;\n+\n+\tval = readl(&cru->clksel_con[26]);\n+\tdiv = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,\n+\t\t\t CLK_SARADC_DIV_CON_WIDTH);\n+\n+\treturn DIV_TO_RATE(OSC_HZ, div);\n+}\n+\n+static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)\n+{\n+\tint src_clk_div;\n+\n+\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n+\tassert(src_clk_div < 128);\n+\n+\trk_clrsetreg(&cru->clksel_con[26],\n+\t\t CLK_SARADC_DIV_CON_MASK,\n+\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n+\n+\treturn rk3399_saradc_get_clk(cru);\n+}\n+\n static ulong rk3399_clk_get_rate(struct clk *clk)\n {\n \tstruct rk3399_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -895,6 +923,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)\n \t\tbreak;\n \tcase PCLK_EFUSE1024NS:\n \t\tbreak;\n+\tcase SCLK_SARADC:\n+\t\trate = rk3399_saradc_get_clk(priv->cru);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n@@ -943,6 +974,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)\n \t\tbreak;\n \tcase PCLK_EFUSE1024NS:\n \t\tbreak;\n+\tcase SCLK_SARADC:\n+\t\tret = rk3399_saradc_set_clk(priv->cru, rate);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n", "prefixes": [ "U-Boot", "U-Boot", "v2", "07/14" ] }