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GET /api/patches/815434/?format=api
{ "id": 815434, "url": "http://patchwork.ozlabs.org/api/patches/815434/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170919105605.18533-2-vigneshr@ti.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170919105605.18533-2-vigneshr@ti.com>", "list_archive_url": null, "date": "2017-09-19T10:56:01", "name": "[RESEND,v2,1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "e3ecfb01b85f55c37fef1ebd66f9a2612f5233c8", "submitter": { "id": 65039, "url": "http://patchwork.ozlabs.org/api/people/65039/?format=api", "name": "Raghavendra, Vignesh", "email": "vigneshr@ti.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170919105605.18533-2-vigneshr@ti.com/mbox/", "series": [ { "id": 3840, "url": "http://patchwork.ozlabs.org/api/series/3840/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=3840", "date": "2017-09-19T10:56:01", "name": "K2G: Add QSPI support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/3840/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815434/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815434/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"mvSo1kHi\"; \n\tdkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxKZc6gZcz9sP1\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 20:57:12 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751431AbdISK5L (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 19 Sep 2017 06:57:11 -0400", "from lelnx193.ext.ti.com ([198.47.27.77]:9970 \"EHLO\n\tlelnx193.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751450AbdISK5K (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Tue, 19 Sep 2017 06:57:10 -0400", "from dflxv15.itg.ti.com ([128.247.5.124])\n\tby lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8JAuEmX016474; \n\tTue, 19 Sep 2017 05:56:14 -0500", "from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8JAuEwv008809;\n\tTue, 19 Sep 2017 05:56:14 -0500", "from DFLE105.ent.ti.com (10.64.6.26) by DFLE115.ent.ti.com\n\t(10.64.6.36) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tTue, 19 Sep 2017 05:56:13 -0500", "from dlep32.itg.ti.com (157.170.170.100) by DFLE105.ent.ti.com\n\t(10.64.6.26) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Tue, 19 Sep 2017 05:56:13 -0500", "from a0132425.india.ti.com (ileax41-snat.itg.ti.com\n\t[10.172.224.153])\n\tby dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8JAu6Rd022115;\n\tTue, 19 Sep 2017 05:56:10 -0500" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1505818574;\n\tbh=k8p/LqUqVDVFSLOJH+ZUps60729d8JHs9HdJk1vHZ9c=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=mvSo1kHi4A0iKrVp/Ee4k962o/hZCof88+yYCvxj5KbmkFZyF5v4KezafXN6ZoEWN\n\tP9Go4OIwCkNYRYFilArdWJfMtD4nYJm/Z/Oqc54AVZtRCcF9q0Y6rSbp19mhv25m/P\n\tbI/a1aYS1jUh/024TFULx+/c93BmGizKAzHwiNF8=", "From": "Vignesh R <vigneshr@ti.com>", "To": "Marek Vasut <marek.vasut@gmail.com>,\n\tCyrille Pitchen <cyrille.pitchen@wedev4u.fr>", "CC": "David Woodhouse <dwmw2@infradead.org>,\n\tBrian Norris <computersforpeace@gmail.com>,\n\tBoris Brezillon <boris.brezillon@free-electrons.com>,\n\tRob Herring <robh+dt@kernel.org>,\n\t<linux-mtd@lists.infradead.org>, <devicetree@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Vignesh R <vigneshr@ti.com>,\n\tlinux-arm-kernel <linux-arm-kernel@lists.infradead.org>", "Subject": "[RESEND PATCH v2 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G\n\tSoC specific compatible", "Date": "Tue, 19 Sep 2017 16:26:01 +0530", "Message-ID": "<20170919105605.18533-2-vigneshr@ti.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170919105605.18533-1-vigneshr@ti.com>", "References": "<20170919105605.18533-1-vigneshr@ti.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Update binding documentation to add a new compatible for TI 66AK2G SoC,\nto handle TI SoC specific quirks in the driver.\n\nSigned-off-by: Vignesh R <vigneshr@ti.com>\nAcked-by: Rob Herring <robh@kernel.org>\n---\n Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)", "diff": "diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt\nindex f248056da24c..7dbe3bd9ac56 100644\n--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt\n+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt\n@@ -1,7 +1,9 @@\n * Cadence Quad SPI controller\n \n Required properties:\n-- compatible : Should be \"cdns,qspi-nor\".\n+- compatible : should be one of the following:\n+\tGeneric default - \"cdns,qspi-nor\".\n+\tFor TI 66AK2G SoC - \"ti,k2g-qspi\", \"cdns,qspi-nor\".\n - reg : Contains two entries, each of which is a tuple consisting of a\n \tphysical address and length. The first entry is the address and\n \tlength of the controller register set. The second entry is the\n", "prefixes": [ "RESEND", "v2", "1/5" ] }