Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/815433/?format=api
{ "id": 815433, "url": "http://patchwork.ozlabs.org/api/patches/815433/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505818405-49082-4-git-send-email-david.wu@rock-chips.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505818405-49082-4-git-send-email-david.wu@rock-chips.com>", "list_archive_url": null, "date": "2017-09-19T10:53:14", "name": "[U-Boot,U-Boot,v2,03/14] clk: rockchip: Add rv1108 SARADC clock support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "aed80b3bdbf1a160e3ea2ae70d5f9dc74915abc7", "submitter": { "id": 68083, "url": "http://patchwork.ozlabs.org/api/people/68083/?format=api", "name": "David Wu", "email": "david.wu@rock-chips.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505818405-49082-4-git-send-email-david.wu@rock-chips.com/mbox/", "series": [ { "id": 3839, "url": "http://patchwork.ozlabs.org/api/series/3839/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3839", "date": "2017-09-19T10:53:11", "name": "Add rockchip SARADC support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/3839/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815433/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815433/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxKZ76xpFz9sBZ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 20:56:47 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid A340BC21F44; Tue, 19 Sep 2017 10:55:32 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id A9644C21F03;\n\tTue, 19 Sep 2017 10:55:29 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 0845CC21EFB; Tue, 19 Sep 2017 10:54:52 +0000 (UTC)", "from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.130])\n\tby lists.denx.de (Postfix) with ESMTPS id 21982C21F06\n\tfor <u-boot@lists.denx.de>; Tue, 19 Sep 2017 10:54:47 +0000 (UTC)", "from david.wu?rock-chips.com (unknown [192.168.167.153])\n\tby lucky1.263xmail.com (Postfix) with ESMTP id A91B41EF2ED;\n\tTue, 19 Sep 2017 18:54:42 +0800 (CST)", "from localhost.localdomain (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id B8189387;\n\tTue, 19 Sep 2017 18:54:40 +0800 (CST)", "from unknown (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith SMTP id 857DD46IG;\n\tTue, 19 Sep 2017 18:54:43 +0800 (CST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "****", "X-Spam-Status": "No, score=4.2 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET,\n\tRCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no\n\tautolearn_force=no version=3.4.0", "X-263anti-spam": "KSV:0;", "X-MAIL-GRAY": "1", "X-MAIL-DELIVERY": "0", "X-KSVirus-check": "0", "X-ABS-CHECKED": "4", "X-RL-SENDER": "david.wu@rock-chips.com", "X-FST-TO": "sjg@chromium.org", "X-SENDER-IP": "58.22.7.114", "X-LOGIN-NAME": "david.wu@rock-chips.com", "X-UNIQUE-TAG": "<e34cb206db31541150068057d84ee1af>", "X-ATTACHMENT-NUM": "0", "X-SENDER": "wdc@rock-chips.com", "X-DNS-TYPE": "0", "From": "David Wu <david.wu@rock-chips.com>", "To": "sjg@chromium.org,\n\tphilipp.tomsich@theobroma-systems.com", "Date": "Tue, 19 Sep 2017 18:53:14 +0800", "Message-Id": "<1505818405-49082-4-git-send-email-david.wu@rock-chips.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505818405-49082-1-git-send-email-david.wu@rock-chips.com>", "References": "<1505818405-49082-1-git-send-email-david.wu@rock-chips.com>", "Cc": "huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, \n\tDavid Wu <david.wu@rock-chips.com>, andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com", "Subject": "[U-Boot] [U-Boot, v2,\n\t03/14] clk: rockchip: Add rv1108 SARADC clock support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\nSARADC integer divider control register is 10-bits width.\n\nSigned-off-by: David Wu <david.wu@rock-chips.com>\nAcked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\nReviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\n---\n\nChange in v2:\n - Use extract_bits.\n\n arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5 ++++\n drivers/clk/rockchip/clk_rv1108.c | 33 ++++++++++++++++++++++++-\n include/dt-bindings/clock/rv1108-cru.h | 2 ++\n 3 files changed, 39 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h\nindex 2a1ae69..ad2dc96 100644\n--- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h\n+++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h\n@@ -90,6 +90,11 @@ enum {\n \tCORE_CLK_DIV_SHIFT\t= 0,\n \tCORE_CLK_DIV_MASK\t= 0x1f << CORE_CLK_DIV_SHIFT,\n \n+\t/* CLKSEL_CON22 */\n+\tCLK_SARADC_DIV_CON_SHIFT= 0,\n+\tCLK_SARADC_DIV_CON_MASK\t= GENMASK(9, 0),\n+\tCLK_SARADC_DIV_CON_WIDTH= 10,\n+\n \t/* CLKSEL24_CON */\n \tMAC_PLL_SEL_SHIFT\t= 12,\n \tMAC_PLL_SEL_MASK\t= 1 << MAC_PLL_SEL_SHIFT,\ndiff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c\nindex cf966bb..86e73e4 100644\n--- a/drivers/clk/rockchip/clk_rv1108.c\n+++ b/drivers/clk/rockchip/clk_rv1108.c\n@@ -5,6 +5,7 @@\n */\n \n #include <common.h>\n+#include <bitfield.h>\n #include <clk-uclass.h>\n #include <dm.h>\n #include <errno.h>\n@@ -36,7 +37,7 @@ enum {\n \t\t\t #hz \"Hz cannot be hit with PLL \"\\\n \t\t\t \"divisors on line \" __stringify(__LINE__));\n \n-/* use interge mode*/\n+/* use integer mode */\n static inline int rv1108_pll_id(enum rk_clk_id clk_id)\n {\n \tint id = 0;\n@@ -130,6 +131,31 @@ static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)\n \treturn DIV_TO_RATE(pll_rate, div);\n }\n \n+static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)\n+{\n+\tu32 div, val;\n+\n+\tval = readl(&cru->clksel_con[22]);\n+\tdiv = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,\n+\t\t\t CLK_SARADC_DIV_CON_WIDTH);\n+\n+\treturn DIV_TO_RATE(OSC_HZ, div);\n+}\n+\n+static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)\n+{\n+\tint src_clk_div;\n+\n+\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n+\tassert(src_clk_div < 128);\n+\n+\trk_clrsetreg(&cru->clksel_con[22],\n+\t\t CLK_SARADC_DIV_CON_MASK,\n+\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n+\n+\treturn rv1108_saradc_get_clk(cru);\n+}\n+\n static ulong rv1108_clk_get_rate(struct clk *clk)\n {\n \tstruct rv1108_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -137,6 +163,8 @@ static ulong rv1108_clk_get_rate(struct clk *clk)\n \tswitch (clk->id) {\n \tcase 0 ... 63:\n \t\treturn rkclk_pll_get_rate(priv->cru, clk->id);\n+\tcase SCLK_SARADC:\n+\t\treturn rv1108_saradc_get_clk(priv->cru);\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n@@ -154,6 +182,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)\n \tcase SCLK_SFC:\n \t\tnew_rate = rv1108_sfc_set_clk(priv->cru, rate);\n \t\tbreak;\n+\tcase SCLK_SARADC:\n+\t\tnew_rate = rv1108_saradc_set_clk(priv->cru, rate);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\ndiff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h\nindex d2ad3bb..7defc6b 100644\n--- a/include/dt-bindings/clock/rv1108-cru.h\n+++ b/include/dt-bindings/clock/rv1108-cru.h\n@@ -39,6 +39,7 @@\n #define SCLK_MAC_TX\t\t\t88\n #define SCLK_MACREF\t\t\t89\n #define SCLK_MACREF_OUT\t\t\t90\n+#define SCLK_SARADC\t\t\t91\n \n \n /* aclk gates */\n@@ -67,6 +68,7 @@\n #define PCLK_TIMER\t\t\t270\n #define PCLK_PERI\t\t\t271\n #define PCLK_GMAC\t\t\t272\n+#define PCLK_SARADC\t\t\t273\n \n /* hclk gates */\n #define HCLK_I2S0_8CH\t\t\t320\n", "prefixes": [ "U-Boot", "U-Boot", "v2", "03/14" ] }