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GET /api/patches/815397/?format=api
{ "id": 815397, "url": "http://patchwork.ozlabs.org/api/patches/815397/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170919092658.22482-6-Zhiqiang.Hou@nxp.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20170919092658.22482-6-Zhiqiang.Hou@nxp.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20170919092658.22482-6-Zhiqiang.Hou@nxp.com/", "date": "2017-09-19T09:26:58", "name": "[5/5] arm64: dts: ls1046a: add PCIe controller DT nodes", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "3d3af5e09ea08c20da36cde5a1e6454d2536295f", "submitter": { "id": 67929, "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api", "name": "Z.Q. Hou", "email": "zhiqiang.hou@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170919092658.22482-6-Zhiqiang.Hou@nxp.com/mbox/", "series": [ { "id": 3817, "url": "http://patchwork.ozlabs.org/api/series/3817/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=3817", "date": "2017-09-19T09:26:53", "name": "arm64: add ls1012a and ls1046a pcie support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3817/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815397/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815397/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxJ9G22pBz9s7B\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 19 Sep 2017 19:53:38 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xxJ9G0z8mzDrbS\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 19 Sep 2017 19:53:38 +1000 (AEST)", "from NAM02-CY1-obe.outbound.protection.outlook.com\n\t(mail-cys01nam02on0073.outbound.protection.outlook.com\n\t[104.47.37.73])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xxHz82kQtzDqXj\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 19 Sep 2017 19:44:52 +1000 (AEST)", "from DM5PR03CA0034.namprd03.prod.outlook.com (10.174.189.151) by\n\tBN3PR03MB2354.namprd03.prod.outlook.com (10.166.74.149) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.56.11; Tue, 19 Sep 2017 09:44:46 +0000", "from BN1AFFO11FD036.protection.gbl (2a01:111:f400:7c10::148) by\n\tDM5PR03CA0034.outlook.office365.com (2603:10b6:4:3b::23) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.56.9 via Frontend Transport; Tue, 19 Sep 2017 09:44:46 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBN1AFFO11FD036.mail.protection.outlook.com (10.58.52.240) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.35.14\n\tvia Frontend Transport; Tue, 19 Sep 2017 09:44:46 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv8J9iINS014190; Tue, 19 Sep 2017 02:44:41 -0700" ], "Authentication-Results": [ "ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nxp.com\n\t(client-ip=104.47.37.73;\n\thelo=nam02-cy1-obe.outbound.protection.outlook.com; \n\tenvelope-from=zhiqiang.hou@nxp.com; receiver=<UNKNOWN>)", "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;" ], "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Zhiqiang Hou <Zhiqiang.Hou@nxp.com>", "To": "<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, \n\t<linuxppc-dev@lists.ozlabs.org>, <marc.zyngier@arm.com>,\n\t<robh+dt@kernel.org>, <mark.rutland@arm.com>, <bhelgaas@google.com>, \n\t<shawnguo@kernel.org>, <Mingkai.Hu@nxp.com>, <Minghuan.Lian@nxp.com>, \n\t<roy.zang@nxp.com>", "Subject": "[PATCH 5/5] arm64: dts: ls1046a: add PCIe controller DT nodes", "Date": "Tue, 19 Sep 2017 17:26:58 +0800", "Message-ID": "<20170919092658.22482-6-Zhiqiang.Hou@nxp.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170919092658.22482-1-Zhiqiang.Hou@nxp.com>", "References": "<20170919092658.22482-1-Zhiqiang.Hou@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131502878862807775;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BN3PR03MB2354; ", "X-Forefront-PRVS": "04359FAD81", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Sep 2017 09:44:46.0935\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN3PR03MB2354", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Hou Zhiqiang <Zhiqiang.Hou@nxp.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nLS1046a implements 3 PCIe 3.0 controllers.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n---\n arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 75 ++++++++++++++++++++++++++\n 1 file changed, 75 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi\nindex c8ff0baddf1d..eac8c32f64b0 100644\n--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi\n+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi\n@@ -661,6 +661,81 @@\n \t\t\t\t <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;\n \t\t};\n \n+\t\tpcie@3400000 {\n+\t\t\tcompatible = \"fsl,ls1046a-pcie\", \"snps,dw-pcie\";\n+\t\t\treg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */\n+\t\t\t 0x40 0x00000000 0x0 0x00002000>; /* configuration space */\n+\t\t\treg-names = \"regs\", \"config\";\n+\t\t\tinterrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */\n+\t\t\t\t <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */\n+\t\t\tinterrupt-names = \"aer\", \"pme\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tdma-coherent;\n+\t\t\tnum-lanes = <4>;\n+\t\t\tbus-range = <0x0 0xff>;\n+\t\t\tranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */\n+\t\t\t\t 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */\n+\t\t\tmsi-parent = <&msi1>, <&msi2>, <&msi3>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\t\tinterrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t};\n+\n+\t\tpcie@3500000 {\n+\t\t\tcompatible = \"fsl,ls1046a-pcie\", \"snps,dw-pcie\";\n+\t\t\treg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */\n+\t\t\t 0x48 0x00000000 0x0 0x00002000>; /* configuration space */\n+\t\t\treg-names = \"regs\", \"config\";\n+\t\t\tinterrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */\n+\t\t\t\t <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */\n+\t\t\tinterrupt-names = \"aer\", \"pme\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tdma-coherent;\n+\t\t\tnum-lanes = <2>;\n+\t\t\tbus-range = <0x0 0xff>;\n+\t\t\tranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */\n+\t\t\t\t 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */\n+\t\t\tmsi-parent = <&msi2>, <&msi3>, <&msi1>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\t\tinterrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t};\n+\n+\t\tpcie@3600000 {\n+\t\t\tcompatible = \"fsl,ls1046a-pcie\", \"snps,dw-pcie\";\n+\t\t\treg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */\n+\t\t\t 0x50 0x00000000 0x0 0x00002000>; /* configuration space */\n+\t\t\treg-names = \"regs\", \"config\";\n+\t\t\tinterrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */\n+\t\t\t\t <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */\n+\t\t\tinterrupt-names = \"aer\", \"pme\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tdma-coherent;\n+\t\t\tnum-lanes = <2>;\n+\t\t\tbus-range = <0x0 0xff>;\n+\t\t\tranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */\n+\t\t\t\t 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */\n+\t\t\tmsi-parent = <&msi3>, <&msi1>, <&msi2>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\t\tinterrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t};\n+\n \t};\n \n \treserved-memory {\n", "prefixes": [ "5/5" ] }