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GET /api/patches/815385/?format=api
{ "id": 815385, "url": "http://patchwork.ozlabs.org/api/patches/815385/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170919092658.22482-5-Zhiqiang.Hou@nxp.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170919092658.22482-5-Zhiqiang.Hou@nxp.com>", "list_archive_url": null, "date": "2017-09-19T09:26:57", "name": "[4/5] arm64: dts: ls1012a: Add PCIe controller DT node", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "d1b3766340be585f718c7e862edeb9cebb01d2e9", "submitter": { "id": 67929, "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api", "name": "Z.Q. Hou", "email": "zhiqiang.hou@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170919092658.22482-5-Zhiqiang.Hou@nxp.com/mbox/", "series": [ { "id": 3816, "url": "http://patchwork.ozlabs.org/api/series/3816/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=3816", "date": "2017-09-19T09:26:58", "name": "arm64: add ls1012a and ls1046a pcie support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3816/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815385/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815385/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxJ0n2fxJz9sMN\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 19:46:17 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751463AbdISJpU (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 19 Sep 2017 05:45:20 -0400", "from mail-cys01nam02on0089.outbound.protection.outlook.com\n\t([104.47.37.89]:52480\n\t\"EHLO NAM02-CY1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1751361AbdISJoo (ORCPT <rfc822;linux-pci@vger.kernel.org>);\n\tTue, 19 Sep 2017 05:44:44 -0400", "from BN6PR03CA0071.namprd03.prod.outlook.com (10.173.137.33) by\n\tCO2PR03MB2360.namprd03.prod.outlook.com (10.166.93.20) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.56.11; Tue, 19 Sep 2017 09:44:42 +0000", "from BL2FFO11OLC005.protection.gbl (2a01:111:f400:7c09::194) by\n\tBN6PR03CA0071.outlook.office365.com (2603:10b6:404:4c::33) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.56.11 via\n\tFrontend Transport; Tue, 19 Sep 2017 09:44:41 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBL2FFO11OLC005.mail.protection.outlook.com (10.173.160.91) with\n\tMicrosoft\n\tSMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id\n\t15.20.35.14 via Frontend Transport; Tue, 19 Sep 2017 09:44:41 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv8J9iINR014190; Tue, 19 Sep 2017 02:44:37 -0700" ], "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Zhiqiang Hou <Zhiqiang.Hou@nxp.com>", "To": "<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,\n\t<linuxppc-dev@lists.ozlabs.org>, <marc.zyngier@arm.com>,\n\t<robh+dt@kernel.org>, <mark.rutland@arm.com>,\n\t<bhelgaas@google.com>, <shawnguo@kernel.org>, <Mingkai.Hu@nxp.com>,\n\t<Minghuan.Lian@nxp.com>, <roy.zang@nxp.com>", "CC": "Hou Zhiqiang <Zhiqiang.Hou@nxp.com>", "Subject": "[PATCH 4/5] arm64: dts: ls1012a: Add PCIe controller DT node", "Date": "Tue, 19 Sep 2017 17:26:57 +0800", "Message-ID": "<20170919092658.22482-5-Zhiqiang.Hou@nxp.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170919092658.22482-1-Zhiqiang.Hou@nxp.com>", "References": "<20170919092658.22482-1-Zhiqiang.Hou@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131502878820528731;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CO2PR03MB2360; ", "X-Forefront-PRVS": "04359FAD81", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Sep 2017 09:44:41.8812\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CO2PR03MB2360", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nAdd PCIe controller node for ls1012a platform.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n---\n arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 24 ++++++++++++++++++++++++\n 1 file changed, 24 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi\nindex a7698ac7264b..140570d45ff3 100644\n--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi\n+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi\n@@ -478,5 +478,29 @@\n \t\t\tmsi-controller;\n \t\t\tinterrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;\n \t\t};\n+\n+\t\tpcie@3400000 {\n+\t\t\tcompatible = \"fsl,ls1012a-pcie\", \"snps,dw-pcie\";\n+\t\t\treg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */\n+\t\t\t 0x40 0x00000000 0x0 0x00002000>; /* configuration space */\n+\t\t\treg-names = \"regs\", \"config\";\n+\t\t\tinterrupts = <0 118 0x4>, /* controller interrupt */\n+\t\t\t\t <0 117 0x4>; /* PME interrupt */\n+\t\t\tinterrupt-names = \"aer\", \"pme\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tnum-lanes = <4>;\n+\t\t\tbus-range = <0x0 0xff>;\n+\t\t\tranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */\n+\t\t\t\t 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */\n+\t\t\tmsi-parent = <&msi>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\t\tinterrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t};\n \t};\n };\n", "prefixes": [ "4/5" ] }