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GET /api/patches/815368/?format=api
{ "id": 815368, "url": "http://patchwork.ozlabs.org/api/patches/815368/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-6-git-send-email-chin.liang.see@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505812951-25088-6-git-send-email-chin.liang.see@intel.com>", "list_archive_url": null, "date": "2017-09-19T09:22:22", "name": "[U-Boot,05/14] arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "2877afd2dcf0b3859194c14c7cf18efc7e4b586e", "submitter": { "id": 70182, "url": "http://patchwork.ozlabs.org/api/people/70182/?format=api", "name": "See, Chin Liang", "email": "chin.liang.see@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-6-git-send-email-chin.liang.see@intel.com/mbox/", "series": [ { "id": 3810, "url": "http://patchwork.ozlabs.org/api/series/3810/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3810", "date": "2017-09-19T09:22:17", "name": "Enable Stratix10 SoC support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3810/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815368/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815368/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHgs5l2qz9sMN\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 19:31:37 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 7145DC21EEF; Tue, 19 Sep 2017 09:28:54 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 47B75C21ED2;\n\tTue, 19 Sep 2017 09:24:50 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid CF3BCC21DD1; Tue, 19 Sep 2017 09:23:37 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby lists.denx.de (Postfix) with ESMTPS id 264E6C21EEE\n\tfor <u-boot@lists.denx.de>; Tue, 19 Sep 2017 09:23:31 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:29 -0700", "from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:22:48 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220782156\"", "From": "chin.liang.see@intel.com", "To": "u-boot@lists.denx.de,\n\tMarek Vasut <marex@denx.de>", "Date": "Tue, 19 Sep 2017 17:22:22 +0800", "Message-Id": "<1505812951-25088-6-git-send-email-chin.liang.see@intel.com>", "X-Mailer": "git-send-email 2.2.2", "In-Reply-To": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "References": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "Cc": "Tien Fong Chee <tien.fong.chee@intel.com>,\n\tChin Liang See <chin.liang.see@intel.com>", "Subject": "[U-Boot] [PATCH 05/14] arm: socfpga: stratix10: Add pinmux support\n\tfor Stratix10 SoC", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Chin Liang See <chin.liang.see@intel.com>\n\nAdd pinmux driver support for Stratix SoC\n\nSigned-off-by: Chin Liang See <chin.liang.see@intel.com>\n---\n arch/arm/mach-socfpga/Makefile | 2 +\n .../arm/mach-socfpga/include/mach/system_manager.h | 5 +-\n .../mach-socfpga/include/mach/system_manager_s10.h | 169 +++++++++++++++++++++\n arch/arm/mach-socfpga/system_manager_s10.c | 91 +++++++++++\n arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 55 +++++++\n 5 files changed, 321 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h\n create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c\n create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c", "diff": "diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile\nindex f10b05c..910eb6f 100644\n--- a/arch/arm/mach-socfpga/Makefile\n+++ b/arch/arm/mach-socfpga/Makefile\n@@ -33,6 +33,8 @@ endif\n ifdef CONFIG_TARGET_SOCFPGA_STRATIX10\n obj-y\t+= clock_manager_s10.o\n obj-y\t+= reset_manager_s10.o\n+obj-y\t+= system_manager_s10.o\n+obj-y\t+= wrap_pinmux_config_s10.o\n obj-y\t+= wrap_pll_config_s10.o\n endif\n ifdef CONFIG_SPL_BUILD\ndiff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h\nindex e6d4280..80c7d0b 100644\n--- a/arch/arm/mach-socfpga/include/mach/system_manager.h\n+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h\n@@ -7,6 +7,9 @@\n #ifndef _SYSTEM_MANAGER_H_\n #define _SYSTEM_MANAGER_H_\n \n+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)\n+#include <asm/arch/system_manager_s10.h>\n+#else\n #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX\tBIT(0)\n #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO\tBIT(1)\n #define SYSMGR_ECC_OCRAM_EN\tBIT(0)\n@@ -89,5 +92,5 @@\n \n #define SYSMGR_GET_BOOTINFO_BSEL(bsel)\t\t\\\n \t\t(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)\n-\n+#endif\n #endif /* _SYSTEM_MANAGER_H_ */\ndiff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h\nnew file mode 100644\nindex 0000000..d992072\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h\n@@ -0,0 +1,169 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#ifndef\t_SYSTEM_MANAGER_S10_\n+#define\t_SYSTEM_MANAGER_S10_\n+\n+void sysmgr_pinmux_init(void);\n+void populate_sysmgr_fpgaintf_module(void);\n+void populate_sysmgr_pinmux(void);\n+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);\n+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);\n+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);\n+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);\n+\n+struct socfpga_system_manager {\n+\t/* System Manager Module */\n+\tu32\tsiliconid1;\t\t\t/* 0x00 */\n+\tu32\tsiliconid2;\n+\tu32\twddbg;\n+\tu32\t_pad_0xc;\n+\tu32\tmpu_status;\t\t\t/* 0x10 */\n+\tu32\tmpu_ace;\n+\tu32\t_pad_0x18_0x1c[2];\n+\tu32\tdma;\t\t\t\t/* 0x20 */\n+\tu32\tdma_periph;\n+\t/* SDMMC Controller Group */\n+\tu32\tsdmmcgrp_ctrl;\n+\tu32\tsdmmcgrp_l3master;\n+\t/* NAND Flash Controller Register Group */\n+\tu32\tnandgrp_bootstrap;\t\t/* 0x30 */\n+\tu32\tnandgrp_l3master;\n+\t/* USB Controller Group */\n+\tu32\tusb0_l3master;\n+\tu32\tusb1_l3master;\n+\t/* EMAC Group */\n+\tu32\temac_gbl;\t\t\t/* 0x40 */\n+\tu32\temac0;\n+\tu32\temac1;\n+\tu32\temac2;\n+\tu32\temac0_ace;\t\t\t/* 0x50 */\n+\tu32\temac1_ace;\n+\tu32\temac2_ace;\n+\tu32\tnand_axuser;\n+\tu32\t_pad_0x60_0x64[2];\t\t/* 0x60 */\n+\t/* FPGA interface Group */\n+\tu32\tfpgaintf_en_1;\n+\tu32\tfpgaintf_en_2;\n+\tu32\tfpgaintf_en_3;\t\t\t/* 0x70 */\n+\tu32\tdma_l3master;\n+\tu32\tetr_l3master;\n+\tu32\t_pad_0x7c;\n+\tu32\tsec_ctrl_slt;\t\t\t/* 0x80 */\n+\tu32\tosc_trim;\n+\tu32\t_pad_0x88_0x8c[2];\n+\t/* ECC Group */\n+\tu32\tecc_intmask_value;\t\t/* 0x90 */\n+\tu32\tecc_intmask_set;\n+\tu32\tecc_intmask_clr;\n+\tu32\tecc_intstatus_serr;\n+\tu32\tecc_intstatus_derr;\t\t/* 0xa0 */\n+\tu32\t_pad_0xa4_0xac[3];\n+\tu32\tnoc_addr_remap;\t\t\t/* 0xb0 */\n+\tu32\thmc_clk;\n+\tu32\tio_pa_ctrl;\n+\tu32\t_pad_0xbc;\n+\t/* NOC Group */\n+\tu32\tnoc_timeout;\t\t\t/* 0xc0 */\n+\tu32\tnoc_idlereq_set;\n+\tu32\tnoc_idlereq_clr;\n+\tu32\tnoc_idlereq_value;\n+\tu32\tnoc_idleack;\t\t\t/* 0xd0 */\n+\tu32\tnoc_idlestatus;\n+\tu32\tfpga2soc_ctrl;\n+\tu32\tfpga_config;\n+\tu32\tiocsrclk_gate;\t\t\t/* 0xe0 */\n+\tu32\tgpo;\n+\tu32\tgpi;\n+\tu32\t_pad_0xec;\n+\tu32\tmpu;\t\t\t\t/* 0xf0 */\n+\tu32\tsdm_hps_spare;\n+\tu32\thps_sdm_spare;\n+\tu32\t_pad_0xfc_0x1fc[65];\n+\t/* Boot scratch register group */\n+\tu32\tboot_scratch_cold0;\t\t/* 0x200 */\n+\tu32\tboot_scratch_cold1;\n+\tu32\tboot_scratch_cold2;\n+\tu32\tboot_scratch_cold3;\n+\tu32\tboot_scratch_cold4;\t\t/* 0x210 */\n+\tu32\tboot_scratch_cold5;\n+\tu32\tboot_scratch_cold6;\n+\tu32\tboot_scratch_cold7;\n+\tu32\tboot_scratch_cold8;\t\t/* 0x220 */\n+\tu32\tboot_scratch_cold9;\n+\tu32\t_pad_0x228_0xffc[886];\n+\t/* Pin select and pin control group */\n+\tu32\tpinsel0[40];\t\t\t/* 0x1000 */\n+\tu32\t_pad_0x10a0_0x10fc[24];\n+\tu32\tpinsel40[8];\n+\tu32\t_pad_0x1120_0x112c[4];\n+\tu32\tioctrl0[28];\n+\tu32\t_pad_0x11a0_0x11fc[24];\n+\tu32\tioctrl28[20];\n+\tu32\t_pad_0x1250_0x12fc[44];\n+\t/* Use FPGA mux */\n+\tu32\trgmii0usefpga;\t\t\t/* 0x1300 */\n+\tu32\trgmii1usefpga;\n+\tu32\trgmii2usefpga;\n+\tu32\ti2c0usefpga;\n+\tu32\ti2c1usefpga;\n+\tu32\ti2c_emac0_usefpga;\n+\tu32\ti2c_emac1_usefpga;\n+\tu32\ti2c_emac2_usefpga;\n+\tu32\tnandusefpga;\n+\tu32\t_pad_0x1324;\n+\tu32\tspim0usefpga;\n+\tu32\tspim1usefpga;\n+\tu32\tspis0usefpga;\n+\tu32\tspis1usefpga;\n+\tu32\tuart0usefpga;\n+\tu32\tuart1usefpga;\n+\tu32\tmdio0usefpga;\n+\tu32\tmdio1usefpga;\n+\tu32\tmdio2usefpga;\n+\tu32\t_pad_0x134c;\n+\tu32\tjtagusefpga;\n+\tu32\tsdmmcusefpga;\n+\tu32\thps_osc_clk;\n+\tu32\t_pad_0x135c_0x13fc[41];\n+\tu32\tiodelay0[40];\n+\tu32\t_pad_0x14a0_0x14fc[24];\n+\tu32\tiodelay40[8];\n+\n+};\n+\n+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX\t(1 << 0)\n+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO\t(1 << 1)\n+#define SYSMGR_ECC_OCRAM_EN\t(1 << 0)\n+#define SYSMGR_ECC_OCRAM_SERR\t(1 << 3)\n+#define SYSMGR_ECC_OCRAM_DERR\t(1 << 4)\n+#define SYSMGR_FPGAINTF_USEFPGA\t0x1\n+\n+#define SYSMGR_FPGAINTF_NAND\t(1 << 4)\n+#define SYSMGR_FPGAINTF_SDMMC\t(1 << 8)\n+#define SYSMGR_FPGAINTF_SPIM0\t(1 << 16)\n+#define SYSMGR_FPGAINTF_SPIM1\t(1 << 24)\n+#define SYSMGR_FPGAINTF_EMAC0\t(0x11 << 0)\n+#define SYSMGR_FPGAINTF_EMAC1\t(0x11 << 8)\n+#define SYSMGR_FPGAINTF_EMAC2\t(0x11 << 16)\n+\n+#define SYSMGR_SDMMC_SMPLSEL_SHIFT\t4\n+#define SYSMGR_SDMMC_DRVSEL_SHIFT\t0\n+\n+/* EMAC Group Bit definitions */\n+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII\t0x0\n+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII\t\t0x1\n+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII\t\t0x2\n+\n+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB\t\t\t0\n+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB\t\t\t2\n+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK\t\t\t0x3\n+\n+#define SYSMGR_NOC_H2F_MSK\t\t0x00000001\n+#define SYSMGR_NOC_LWH2F_MSK\t\t0x00000010\n+#define SYSMGR_HMC_CLK_STATUS_MSK\t0x00000001\n+\n+#endif /* _SYSTEM_MANAGER_S10_ */\ndiff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c\nnew file mode 100644\nindex 0000000..8c7a715\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/system_manager_s10.c\n@@ -0,0 +1,91 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include <common.h>\n+#include <asm/io.h>\n+#include <asm/arch/system_manager.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static struct socfpga_system_manager *sysmgr_regs =\n+\t(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;\n+\n+/*\n+ * Configure all the pin muxes\n+ */\n+void sysmgr_pinmux_init(void)\n+{\n+\tpopulate_sysmgr_pinmux();\n+\tpopulate_sysmgr_fpgaintf_module();\n+}\n+\n+/*\n+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.\n+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but\n+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.\n+ */\n+void populate_sysmgr_fpgaintf_module(void)\n+{\n+\tuint32_t handoff_val = 0;\n+\n+\t/* Enable the signal for those HPS peripherals that use FPGA. */\n+\tif (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)\n+\t\thandoff_val |= SYSMGR_FPGAINTF_NAND;\n+\tif (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)\n+\t\thandoff_val |= SYSMGR_FPGAINTF_SDMMC;\n+\tif (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)\n+\t\thandoff_val |= SYSMGR_FPGAINTF_SPIM0;\n+\tif (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)\n+\t\thandoff_val |= SYSMGR_FPGAINTF_SPIM1;\n+\twritel(handoff_val, &sysmgr_regs->fpgaintf_en_2);\n+\n+\thandoff_val = 0;\n+\tif (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)\n+\t\thandoff_val |= SYSMGR_FPGAINTF_EMAC0;\n+\tif (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)\n+\t\thandoff_val |= SYSMGR_FPGAINTF_EMAC1;\n+\tif (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA)\n+\t\thandoff_val |= SYSMGR_FPGAINTF_EMAC2;\n+\twritel(handoff_val, &sysmgr_regs->fpgaintf_en_3);\n+}\n+\n+/*\n+ * Configure all the pin muxes\n+ */\n+void populate_sysmgr_pinmux(void)\n+{\n+\tconst u32 *sys_mgr_table_u32;\n+\tunsigned int len, i;\n+\n+\t/* setup the pin sel */\n+\tsysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);\n+\tfor (i = 0; i < len; i = i+2) {\n+\t\twritel(sys_mgr_table_u32[i+1],\n+\t\t sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]);\n+\t}\n+\n+\t/* setup the pin ctrl */\n+\tsysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);\n+\tfor (i = 0; i < len; i = i+2) {\n+\t\twritel(sys_mgr_table_u32[i+1],\n+\t\t sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]);\n+\t}\n+\n+\t/* setup the fpga use */\n+\tsysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len);\n+\tfor (i = 0; i < len; i = i+2) {\n+\t\twritel(sys_mgr_table_u32[i+1],\n+\t\t sys_mgr_table_u32[i] +\n+\t\t (u8 *)&sysmgr_regs->rgmii0usefpga);\n+\t}\n+\n+\t/* setup the IO delay */\n+\tsysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);\n+\tfor (i = 0; i < len; i = i+2) {\n+\t\twritel(sys_mgr_table_u32[i+1],\n+\t\t sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]);\n+\t}\n+}\ndiff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c\nnew file mode 100644\nindex 0000000..b6a9f68\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0\n+ */\n+\n+#include <common.h>\n+#include <errno.h>\n+#include <asm/io.h>\n+#include <asm/arch/handoff_s10.h>\n+\n+static void sysmgr_pinmux_handoff_read(void *handoff_address,\n+\t\t\t\tconst u32 **table, unsigned int *table_len)\n+{\n+\tunsigned int handoff_entry = (swab32(readl(handoff_address +\n+\t\t\t\t\tCONFIG_HANDOFF_OFFSET_LENGTH)) -\n+\t\t\t\t\tCONFIG_HANDOFF_OFFSET_DATA) /\n+\t\t\t\t\tsizeof(unsigned int);\n+\tunsigned int handoff_chunk[handoff_entry], temp, i;\n+\n+\tif (swab32(readl(CONFIG_HANDOFF_MUX)) == CONFIG_HANDOFF_MAGIC_MUX) {\n+\t\t/* using handoff from Quartus tools if exists */\n+\t\tfor (i = 0; i < handoff_entry; i++) {\n+\t\t\ttemp = readl(handoff_address +\n+\t\t\t\t CONFIG_HANDOFF_OFFSET_DATA + (i * 4));\n+\t\t\thandoff_chunk[i] = swab32(temp);\n+\t\t}\n+\t\t*table = handoff_chunk;\n+\t\t*table_len = ARRAY_SIZE(handoff_chunk);\n+\t}\n+}\n+\n+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len)\n+{\n+\tsysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_MUX, table,\n+\t\t\t\t table_len);\n+}\n+\n+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len)\n+{\n+\tsysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_IOCTL, table,\n+\t\t\t\t table_len);\n+}\n+\n+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len)\n+{\n+\tsysmgr_pinmux_handoff_read((void *)CONFIG_HANDOFF_FPGA, table,\n+\t\t\t\t table_len);\n+}\n+\n+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len)\n+{\n+\tsysmgr_pinmux_handoff_read((void *)CONFIG_HANODFF_DELAY, table,\n+\t\t\t\t table_len);\n+}\n", "prefixes": [ "U-Boot", "05/14" ] }