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GET /api/patches/815367/?format=api
{ "id": 815367, "url": "http://patchwork.ozlabs.org/api/patches/815367/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-15-git-send-email-chin.liang.see@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505812951-25088-15-git-send-email-chin.liang.see@intel.com>", "list_archive_url": null, "date": "2017-09-19T09:22:31", "name": "[U-Boot,14/14] arm: socfpga: stratix10: Enable Stratix10 SoC build", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "f39836e1870abb3c401ebaedbd0adf767f479d5a", "submitter": { "id": 70182, "url": "http://patchwork.ozlabs.org/api/people/70182/?format=api", "name": "See, Chin Liang", "email": "chin.liang.see@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-15-git-send-email-chin.liang.see@intel.com/mbox/", "series": [ { "id": 3810, "url": "http://patchwork.ozlabs.org/api/series/3810/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3810", "date": "2017-09-19T09:22:17", "name": "Enable Stratix10 SoC support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3810/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815367/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815367/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHfV1N2Sz9sMN\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 19:30:26 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid F227AC21EDC; Tue, 19 Sep 2017 09:26:00 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 40E86C21EEE;\n\tTue, 19 Sep 2017 09:24:08 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 6EE5CC21EC9; Tue, 19 Sep 2017 09:23:48 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby lists.denx.de (Postfix) with ESMTPS id 48670C21E7B\n\tfor <u-boot@lists.denx.de>; Tue, 19 Sep 2017 09:23:43 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:42 -0700", "from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:23:06 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.5 required=5.0 tests=RCVD_IN_DNSWL_MED,\n\tRCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tUPPERCASE_50_75 autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220782553\"", "From": "chin.liang.see@intel.com", "To": "u-boot@lists.denx.de,\n\tMarek Vasut <marex@denx.de>", "Date": "Tue, 19 Sep 2017 17:22:31 +0800", "Message-Id": "<1505812951-25088-15-git-send-email-chin.liang.see@intel.com>", "X-Mailer": "git-send-email 2.2.2", "In-Reply-To": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "References": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "Cc": "Tien Fong Chee <tien.fong.chee@intel.com>,\n\tChin Liang See <chin.liang.see@intel.com>", "Subject": "[U-Boot] [PATCH 14/14] arm: socfpga: stratix10: Enable Stratix10\n\tSoC build", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Chin Liang See <chin.liang.see@intel.com>\n\nAdd build support for Stratix SoC\n\nSigned-off-by: Chin Liang See <chin.liang.see@intel.com>\n---\n arch/arm/Kconfig | 8 +-\n arch/arm/mach-socfpga/Kconfig | 13 ++\n configs/socfpga_stratix10_defconfig | 39 ++++++\n include/configs/socfpga_stratix10_socdk.h | 216 ++++++++++++++++++++++++++++++\n 4 files changed, 273 insertions(+), 3 deletions(-)\n create mode 100644 configs/socfpga_stratix10_defconfig\n create mode 100644 include/configs/socfpga_stratix10_socdk.h", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex bb64b9c..13dd144 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -655,21 +655,23 @@ config ARCH_SNAPDRAGON\n \n config ARCH_SOCFPGA\n \tbool \"Altera SOCFPGA family\"\n-\tselect CPU_V7\n+\tselect CPU_V7 if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10\n+\tselect ARM64 if TARGET_SOCFPGA_STRATIX10\n \tselect SUPPORT_SPL\n \tselect OF_CONTROL\n \tselect SPL_OF_CONTROL\n \tselect DM\n \tselect DM_SPI_FLASH\n \tselect DM_SPI\n-\tselect ENABLE_ARM_SOC_BOOT0_HOOK\n+\tselect ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10\n \tselect ARCH_EARLY_INIT_R\n \tselect ARCH_MISC_INIT\n \tselect SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION\n-\tselect SYS_THUMB_BUILD\n+\tselect SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10\n \timply CMD_MTDPARTS\n \timply CRC32_VERIFY\n \timply FAT_WRITE\n+\tselect SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10\n \n config ARCH_SUNXI\n \tbool \"Support sunxi (Allwinner) SoCs\"\ndiff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig\nindex 45e5379..03ab956 100644\n--- a/arch/arm/mach-socfpga/Kconfig\n+++ b/arch/arm/mach-socfpga/Kconfig\n@@ -49,6 +49,12 @@ config TARGET_SOCFPGA_GEN5\n \tbool\n \tselect ALTERA_SDRAM\n \n+config TARGET_SOCFPGA_STRATIX10\n+\tbool\n+\tselect ARMV8_MULTIENTRY\n+\tselect ARMV8_SPIN_TABLE\n+\tselect ARMV8_SET_SMPEN\n+\n choice\n \tprompt \"Altera SOCFPGA board select\"\n \toptional\n@@ -86,6 +92,10 @@ config TARGET_SOCFPGA_SR1500\n \tbool \"SR1500 (Cyclone V)\"\n \tselect TARGET_SOCFPGA_CYCLONE5\n \n+config TARGET_SOCFPGA_STRATIX10_SOCDK\n+\tbool \"Intel SOCFPGA SoCDK (Stratix 10)\"\n+\tselect TARGET_SOCFPGA_STRATIX10\n+\n config TARGET_SOCFPGA_TERASIC_DE0_NANO\n \tbool \"Terasic DE0-Nano-Atlas (Cyclone V)\"\n \tselect TARGET_SOCFPGA_CYCLONE5\n@@ -116,12 +126,14 @@ config SYS_BOARD\n \tdefault \"sockit\" if TARGET_SOCFPGA_TERASIC_SOCKIT\n \tdefault \"socrates\" if TARGET_SOCFPGA_EBV_SOCRATES\n \tdefault \"sr1500\" if TARGET_SOCFPGA_SR1500\n+\tdefault \"stratix10-socdk\" if TARGET_SOCFPGA_STRATIX10_SOCDK\n \tdefault \"vining_fpga\" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA\n \n config SYS_VENDOR\n \tdefault \"altera\" if TARGET_SOCFPGA_ARRIA5_SOCDK\n \tdefault \"altera\" if TARGET_SOCFPGA_ARRIA10_SOCDK\n \tdefault \"altera\" if TARGET_SOCFPGA_CYCLONE5_SOCDK\n+\tdefault \"altera\" if TARGET_SOCFPGA_STRATIX10_SOCDK\n \tdefault \"aries\" if TARGET_SOCFPGA_ARIES_MCVEVK\n \tdefault \"ebv\" if TARGET_SOCFPGA_EBV_SOCRATES\n \tdefault \"samtec\" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA\n@@ -145,6 +157,7 @@ config SYS_CONFIG_NAME\n \tdefault \"socfpga_sockit\" if TARGET_SOCFPGA_TERASIC_SOCKIT\n \tdefault \"socfpga_socrates\" if TARGET_SOCFPGA_EBV_SOCRATES\n \tdefault \"socfpga_sr1500\" if TARGET_SOCFPGA_SR1500\n+\tdefault \"socfpga_stratix10_socdk\" if TARGET_SOCFPGA_STRATIX10_SOCDK\n \tdefault \"socfpga_vining_fpga\" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA\n \n endif\ndiff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig\nnew file mode 100644\nindex 0000000..e5a7a69\n--- /dev/null\n+++ b/configs/socfpga_stratix10_defconfig\n@@ -0,0 +1,39 @@\n+CONFIG_ARM=y\n+CONFIG_ARCH_SOCFPGA=y\n+CONFIG_SYS_MALLOC_F_LEN=0x2000\n+CONFIG_SPL_FAT_SUPPORT=y\n+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y\n+CONFIG_IDENT_STRING=\"socfpga_stratix10\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"socfpga_stratix10_socdk\"\n+CONFIG_BOOTDELAY=5\n+CONFIG_SYS_PROMPT=\"SOCFPGA_STRATIX10 # \"\n+CONFIG_CMD_CACHE=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+# CONFIG_CMD_FLASH is not set\n+CONFIG_CMD_FS_GENERIC=y\n+# CONFIG_CMD_IMLS is not set\n+CONFIG_CMD_MEMTEST=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_SF=y\n+CONFIG_SPL=y\n+CONFIG_SPL_DM=y\n+CONFIG_SPL_DM_SEQ_ALIAS=y\n+CONFIG_DM_MMC=y\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_DFU_MMC=y\n+CONFIG_MMC_DW=y\n+CONFIG_SPI_FLASH=y\n+CONFIG_SPI_FLASH_BAR=y\n+CONFIG_SPI_FLASH_SPANSION=y\n+CONFIG_SPI_FLASH_STMICRO=y\n+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set\n+CONFIG_CADENCE_QSPI=y\n+CONFIG_DM_ETH=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_ETH_DESIGNWARE=y\n+CONFIG_SYS_NS16550=y\n+CONFIG_USE_TINY_PRINTF=y\ndiff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h\nnew file mode 100644\nindex 0000000..0d955f8\n--- /dev/null\n+++ b/include/configs/socfpga_stratix10_socdk.h\n@@ -0,0 +1,216 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#ifndef __CONFIG_SOCFGPA_STRATIX10_H__\n+#define __CONFIG_SOCFGPA_STRATIX10_H__\n+\n+#include <asm/arch/base_addr_s10.h>\n+\n+/*\n+ * U-Boot general configurations\n+ */\n+#define CONFIG_SYS_TEXT_BASE\t\t0x1000\n+#define CONFIG_SYS_MONITOR_BASE\t\tCONFIG_SYS_TEXT_BASE\n+#define CONFIG_LOADADDR\t\t\t0x80000\n+#define CONFIG_SYS_LOAD_ADDR\t\tCONFIG_LOADADDR\n+#define CONFIG_REMAKE_ELF\n+#define CPU_RELEASE_ADDR\t\t0x80\n+#define CONFIG_SYS_CACHELINE_SIZE\t64\n+\n+/*\n+ * U-Boot console configurations\n+ */\n+#define CONFIG_SYS_MAXARGS\t\t64\n+#define CONFIG_SYS_CBSIZE\t\t2048\n+#define CONFIG_SYS_PBSIZE\t\t(CONFIG_SYS_CBSIZE + \\\n+\t\t\t\t\tsizeof(CONFIG_SYS_PROMPT) + 16)\n+#define CONFIG_SYS_BARGSIZE\t\tCONFIG_SYS_CBSIZE\n+#define CONFIG_SYS_LONGHELP\n+#define CONFIG_AUTO_COMPLETE\t\t/* Command auto complete */\n+#define CONFIG_CMDLINE_EDITING\t\t/* Command history etc */\n+\n+/* Extend size of kernel image for uncompression */\n+#define CONFIG_SYS_BOOTM_LEN\t\t(32 * 1024 * 1024)\n+\n+/*\n+ * U-Boot run time memory configurations\n+ */\n+#define CONFIG_SYS_INIT_RAM_ADDR\t0xFFE00000\n+#define CONFIG_SYS_INIT_RAM_SIZE\t0x40000\n+#define CONFIG_SYS_INIT_SP_ADDR\t\t(CONFIG_SYS_INIT_RAM_ADDR \\\n+\t\t\t\t\t+ CONFIG_SYS_INIT_RAM_SIZE)\n+#define CONFIG_SYS_INIT_SP_OFFSET\t(CONFIG_SYS_INIT_SP_ADDR)\n+#define CONFIG_SYS_MALLOC_LEN\t\t(5 * 1024 * 1024)\n+\n+/*\n+ * U-Boot display configurations\n+ */\n+#define CONFIG_DISPLAY_BOARDINFO_LATE\n+\n+/*\n+ * U-Boot environment configurations\n+ */\n+#define CONFIG_ENV_SIZE\t\t\t0x1000\n+#define CONFIG_SYS_MMC_ENV_DEV\t\t0\t/* device 0 */\n+#define CONFIG_ENV_OFFSET\t\t512\t/* just after the MBR */\n+\n+/*\n+ * QSPI support\n+ */\n+ #ifdef CONFIG_CADENCE_QSPI\n+/* Enable it if you want to use dual-stacked mode */\n+#undef CONFIG_SF_DUAL_FLASH\n+/*#define CONFIG_QSPI_RBF_ADDR\t\t0x720000*/\n+\n+/* Flash device info */\n+#define CONFIG_SF_DEFAULT_SPEED\t\t(50000000)\n+#define CONFIG_SF_DEFAULT_MODE\t\t(SPI_MODE_3 | SPI_RX_QUAD)\n+#define CONFIG_SF_DEFAULT_BUS\t\t0\n+#define CONFIG_SF_DEFAULT_CS\t\t0\n+\n+/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/\n+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH\n+#undef CONFIG_ENV_OFFSET\n+#undef CONFIG_ENV_SIZE\n+#define CONFIG_ENV_OFFSET\t\t0x710000\n+#define CONFIG_ENV_SIZE\t\t\t(4 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(4 * 1024)\n+#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */\n+\n+/*#define CONFIG_BOOT_FLASH_TYPE\t\t\"qspi\"*/\n+#define CONFIG_CQSPI_DECODER\t\t0\n+\n+#ifndef CONFIG_SPL_BUILD\n+#define CONFIG_MTD_DEVICE\n+#define CONFIG_MTD_PARTITIONS\n+#define MTDIDS_DEFAULT\t\t\t\"nor0=ff705000.spi.0\"\n+#endif /* CONFIG_SPL_BUILD */\n+\n+/* 533MHz, TODO: Get from SDM */\n+#define CONFIG_CQSPI_REF_CLK\t\t400000000\n+\n+#endif /* CONFIG_CADENCE_QSPI */\n+\n+/*\n+ * Boot arguments passed to the boot command. The value of\n+ * CONFIG_BOOTARGS goes into the environment value \"bootargs\".\n+ * Do note the value will overide also the chosen node in FDT blob.\n+ */\n+#define CONFIG_BOOTARGS \"earlycon\"\n+#define CONFIG_BOOTCOMMAND\t\"run mmcload; run mmcboot\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS \\\n+\t\"loadaddr=\" __stringify(CONFIG_SYS_LOAD_ADDR) \"\\0\" \\\n+\t\"bootfile=Image\\0\" \\\n+\t\"fdt_addr=8000000\\0\" \\\n+\t\"fdtimage=socfpga_stratix10_socdk.dtb\\0\" \\\n+\t\"mmcroot=/dev/mmcblk0p2\\0\" \\\n+\t\"mmcboot=setenv bootargs \" CONFIG_BOOTARGS \\\n+\t\t\" root=${mmcroot} rw rootwait;\" \\\n+\t\t\"booti ${loadaddr} - ${fdt_addr}\\0\" \\\n+\t\"mmcload=mmc rescan;\" \\\n+\t\t\"load mmc 0:1 ${loadaddr} ${bootfile};\" \\\n+\t\t\"load mmc 0:1 ${fdt_addr} ${fdtimage}\\0\"\n+\n+/*\n+ * Generic Interrupt Controller Definitions\n+ */\n+#define CONFIG_GICV2\n+\n+/*\n+ * External memory configurations\n+ */\n+#define PHYS_SDRAM_1\t\t\t0x0\n+#define PHYS_SDRAM_1_SIZE\t\t(1 * 1024 * 1024 * 1024)\n+#define CONFIG_SYS_SDRAM_BASE\t\t0\n+#define CONFIG_NR_DRAM_BANKS\t\t1\n+#define CONFIG_SYS_MEMTEST_START\t0\n+#define CONFIG_SYS_MEMTEST_END\t\tPHYS_SDRAM_1_SIZE - 0x200000\n+\n+/*\n+ * SDRAM controller\n+ */\n+#define CONFIG_ALTERA_SDRAM\n+\n+/*\n+ * Serial / UART configurations\n+ */\n+#define CONFIG_SYS_NS16550_SERIAL\n+#define CONFIG_SYS_NS16550_REG_SIZE\t-4\n+#define CONFIG_SYS_NS16550_COM1\t\tSOCFPGA_UART0_ADDRESS\n+#define CONFIG_SYS_NS16550_CLK\t\t100000000\n+#define CONFIG_CONS_INDEX\t\t1\n+#define CONFIG_BAUDRATE\t\t\t115200\n+/* always write in 32 bit manner */\n+#define CONFIG_SYS_NS16550_MEM32\n+#define CONFIG_SYS_NS16550_REG_SIZE\t-4\n+\n+/*\n+ * Timer & watchdog configurations\n+ */\n+#define COUNTER_FREQUENCY\t\t400000000\n+\n+\n+/*\n+ * SDMMC configurations\n+ */\n+#ifdef CONFIG_CMD_MMC\n+#define CONFIG_BOUNCE_BUFFER\n+#define CONFIG_SYS_MMC_MAX_BLK_COUNT\t256\n+#endif\n+/*\n+ * Flash configurations\n+ */\n+#define CONFIG_SYS_MAX_FLASH_BANKS\t1\n+\n+/* Ethernet on SoC (EMAC) */\n+#if defined(CONFIG_CMD_NET)\n+#define CONFIG_PHY_MICREL\n+#define CONFIG_PHY_MICREL_KSZ9031\n+#define CONFIG_DW_ALTDESCRIPTOR\n+#define CONFIG_MII\n+#define CONFIG_AUTONEG_TIMEOUT\t\t(15 * CONFIG_SYS_HZ)\n+#define CONFIG_PHY_GIGE\n+#endif /* CONFIG_CMD_NET */\n+\n+\n+/*\n+ * SPL memory layout\n+ *\n+ * On chip RAM\n+ * 0xFFE0_0000 ...... Start of OCRAM\n+ * SPL code, rwdata\n+ * 0xFFEx_xxxx ...... Top of stack (grows down)\n+ * 0xFFEy_yyyy ...... Global Data\n+ * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)\n+ * 0xFFE3_FFFF ...... End of OCRAM\n+ *\n+ * SDRAM\n+ * 0x0000_0000 ...... Start of SDRAM_1\n+ * unused / empty space for image loading\n+ * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)\n+ * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)\n+ * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)\n+ *\n+ */\n+#define CONFIG_SPL_FRAMEWORK\n+#define CONFIG_SPL_TEXT_BASE\t\tCONFIG_SYS_INIT_RAM_ADDR\n+#define CONFIG_SPL_MAX_SIZE\t\tCONFIG_SYS_INIT_RAM_SIZE\n+#define CONFIG_SPL_STACK\t\tCONFIG_SYS_INIT_SP_ADDR\n+#define CONFIG_SPL_BSS_MAX_SIZE\t\t0x100000\t/* 1 MB */\n+#define CONFIG_SPL_BSS_START_ADDR\t(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \\\n+\t\t\t\t\t- CONFIG_SPL_BSS_MAX_SIZE)\n+#define CONFIG_SYS_SPL_MALLOC_SIZE\t(CONFIG_SYS_MALLOC_LEN)\n+#define CONFIG_SYS_SPL_MALLOC_START\t(CONFIG_SPL_BSS_START_ADDR \\\n+\t\t\t\t\t- CONFIG_SYS_SPL_MALLOC_SIZE)\n+#define CONFIG_SPL_SPI_LOAD\n+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x400000\n+\n+/* SPL SDMMC boot support */\n+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION\t1\n+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME\t\t\"u-boot-dtb.img\"\n+\n+#endif\t/* __CONFIG_H */\n", "prefixes": [ "U-Boot", "14/14" ] }