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GET /api/patches/815364/?format=api
{ "id": 815364, "url": "http://patchwork.ozlabs.org/api/patches/815364/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-8-git-send-email-chin.liang.see@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505812951-25088-8-git-send-email-chin.liang.see@intel.com>", "list_archive_url": null, "date": "2017-09-19T09:22:24", "name": "[U-Boot,07/14] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "7f557781a7225a683e5a4b097de5a616e2a341c7", "submitter": { "id": 70182, "url": "http://patchwork.ozlabs.org/api/people/70182/?format=api", "name": "See, Chin Liang", "email": "chin.liang.see@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-8-git-send-email-chin.liang.see@intel.com/mbox/", "series": [ { "id": 3810, "url": "http://patchwork.ozlabs.org/api/series/3810/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3810", "date": "2017-09-19T09:22:17", "name": "Enable Stratix10 SoC support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3810/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815364/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815364/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHcz3m7Mz9s78\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 19:29:07 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 302B4C21EC4; Tue, 19 Sep 2017 09:28:14 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 329AAC21F09;\n\tTue, 19 Sep 2017 09:24:33 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 5EF94C21EFD; Tue, 19 Sep 2017 09:23:35 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby lists.denx.de (Postfix) with ESMTPS id 21DFCC21EE7\n\tfor <u-boot@lists.denx.de>; Tue, 19 Sep 2017 09:23:30 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:28 -0700", "from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:22:51 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220782306\"", "From": "chin.liang.see@intel.com", "To": "u-boot@lists.denx.de,\n\tMarek Vasut <marex@denx.de>", "Date": "Tue, 19 Sep 2017 17:22:24 +0800", "Message-Id": "<1505812951-25088-8-git-send-email-chin.liang.see@intel.com>", "X-Mailer": "git-send-email 2.2.2", "In-Reply-To": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "References": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "Cc": "Tien Fong Chee <tien.fong.chee@intel.com>,\n\tChin Liang See <chin.liang.see@intel.com>", "Subject": "[U-Boot] [PATCH 07/14] arm: socfpga: stratix10: Add mailbox support\n\tfor Stratix10 SoC", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Chin Liang See <chin.liang.see@intel.com>\n\nAdd mailbox support for Stratix SoC\n\nSigned-off-by: Ley Foon Tan <ley.foon.tan@intel.com>\nSigned-off-by: Chin Liang See <chin.liang.see@intel.com>\n---\n arch/arm/mach-socfpga/Makefile | 1 +\n arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 108 ++++++++++\n arch/arm/mach-socfpga/mailbox_s10.c | 239 +++++++++++++++++++++++\n 3 files changed, 348 insertions(+)\n create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h\n create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c", "diff": "diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile\nindex b253914..43e18d2 100644\n--- a/arch/arm/mach-socfpga/Makefile\n+++ b/arch/arm/mach-socfpga/Makefile\n@@ -32,6 +32,7 @@ endif\n \n ifdef CONFIG_TARGET_SOCFPGA_STRATIX10\n obj-y\t+= clock_manager_s10.o\n+obj-y\t+= mailbox_s10.o\n obj-y\t+= misc_s10.o\n obj-y\t+= reset_manager_s10.o\n obj-y\t+= system_manager_s10.o\ndiff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h\nnew file mode 100644\nindex 0000000..b9bddf6\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h\n@@ -0,0 +1,108 @@\n+/*\n+ * Copyright (C) 2017 Intel Corporation <www.intel.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+#ifndef _MAILBOX_S10_H_\n+#define _MAILBOX_S10_H_\n+\n+/* user define Uboot ID */\n+#define MBOX_CLIENT_ID_UBOOT\t0xB\n+#define MBOX_ID_UBOOT\t\t0x1\n+\n+#define MBOX_MAX_CMD_INDEX\t2047\n+#define MBOX_CMD_BUFFER_SIZE\t32\n+#define MBOX_RESP_BUFFER_SIZE\t16\n+\n+#define MBOX_HDR_CMD_LSB\t0\n+#define MBOX_HDR_CMD_MSK\t(BIT(11) - 1)\n+#define MBOX_HDR_I_LSB\t\t11\n+#define MBOX_HDR_I_MSK\t\tBIT(11)\n+#define MBOX_HDR_LEN_LSB\t12\n+#define MBOX_HDR_LEN_MSK\t0x007FF000\n+#define MBOX_HDR_ID_LSB\t\t24\n+#define MBOX_HDR_ID_MSK\t\t0x0F000000\n+#define MBOX_HDR_CLIENT_LSB\t28\n+#define MBOX_HDR_CLIENT_MSK\t0xF0000000\n+\n+/* Interrupt flags */\n+#define MBOX_FLAGS_INT_COE\tBIT(0)\t/* COUT update interrupt enable */\n+#define MBOX_FLAGS_INT_RIE\tBIT(1)\t/* RIN update interrupt enable */\n+#define MBOX_FLAGS_INT_UAE\tBIT(8)\t/* Urgent ACK interrupt enable */\n+#define MBOX_ALL_INTRS\t\t(MBOX_FLAGS_INT_COE | \\\n+\t\t\t\t MBOX_FLAGS_INT_RIE | \\\n+\t\t\t\t MBOX_FLAGS_INT_UAE)\n+\n+/* Status */\n+#define MBOX_STATUS_UA_MSK\tBIT(8)\n+\n+#define MBOX_CMD_HEADER(client, id, len, cmd)\t\t \\\n+\t(((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \\\n+\t(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \\\n+\t(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)\t | \\\n+\t(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK)\n+\n+#define MBOX_RESP_ERR_GET(resp)\t\t\t\t\\\n+\t(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)\n+#define MBOX_RESP_LEN_GET(resp)\t\t\t\\\n+\t(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)\n+#define MBOX_RESP_ID_GET(resp)\t\t\t\t\\\n+\t(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)\n+#define MBOX_RESP_CLIENT_GET(resp)\t\t\t\\\n+\t(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)\n+\n+/* Response error list */\n+typedef enum {\n+\t/* CMD completed succesfully, but check resp ARGS for any errors */\n+\tMBOX_RESP_STATOK = 0,\n+\t/* CMD is incorrectly formatted in some way */\n+\tMBOX_RESP_INVALID_COMMAND = 1,\n+\t/* BootROM Command code not undesrtood */\n+\tMBOX_RESP_UNKNOWN_BR = 2,\n+\t/* CMD code not recognized by firmware */\n+\tMBOX_RESP_UNKNOWN = 3,\n+\t/* Indicates that the device is not configured */\n+\tMBOX_RESP_NOT_CONFIGURED = 256,\n+\t/* Indicates that the device is busy */\n+\tMBOX_RESP_DEVICE_BUSY = 0x1FF,\n+\t/* Indicates that there is no valid response available */\n+\tMBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,\n+\t/* General Error */\n+\tMBOX_RESP_ERROR = 0x3FF,\n+} ALT_SDM_MBOX_RESP_CODE;\n+\n+/* Mailbox command list */\n+#define MBOX_RESTART\t\t2\n+#define MBOX_QSPI_OPEN\t\t50\n+#define MBOX_QSPI_CLOSE\t\t51\n+#define MBOX_QSPI_DIRECT\t59\n+\n+struct socfpga_mailbox {\n+\tu32 cin;\t\t/* command valid offset */\n+\tu32 rout;\t\t/* response output offset */\n+\tu32 urg;\t\t/* urgent command */\n+\tu32 flags;\t\t/* interrupt enables */\n+\tu32 pad_0x10_0x1f[4];\t/* 0x10 - 0x1F reserved */\n+\tu32 cout;\t\t/* command free offset */\n+\tu32 rin;\t\t/* respond valid offset */\n+\tu32 pad_0x28;\t\t/* 0x28 reserved */\n+\tu32 status;\t\t/* mailbox status */\n+\tu32 pad_0x30_0x3f[4];\t/* 0x30 - 0x3F reserved */\n+\tu32 cmd_buf[MBOX_CMD_BUFFER_SIZE];\t/* 0x40 - 0xBC circular command\n+\t\t\t\t\t\t buffer to SDM */\n+\tu32 resp_buf[MBOX_RESP_BUFFER_SIZE];\t/* 0xC0 - 0xFF circular\n+\t\t\t\t\t\t response buffer */\n+};\n+\n+/* Use define other than put into struct socfpga_mailbox to save spaces */\n+#define MBOX_DOORBELL_TO_SDM_REG\t(SOCFPGA_MAILBOX_ADDRESS + 0x400)\n+#define MBOX_DOORBELL_FROM_SDM_REG\t(SOCFPGA_MAILBOX_ADDRESS + 0x480)\n+\n+int mbox_init(void);\n+\n+#ifdef CONFIG_CADENCE_QSPI\n+int mbox_qspi_close(void);\n+int mbox_qspi_open(void);\n+#endif\n+\n+#endif\t/* _MAILBOX_S10_H_ */\ndiff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c\nnew file mode 100644\nindex 0000000..074940d\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/mailbox_s10.c\n@@ -0,0 +1,239 @@\n+/*\n+ * Copyright (C) 2017 Intel Corporation <www.intel.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#include <common.h>\n+#include <wait_bit.h>\n+#include <asm/io.h>\n+#include <asm/arch/mailbox_s10.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static const struct socfpga_mailbox *mbox_base =\n+\t\t(void *)SOCFPGA_MAILBOX_ADDRESS;\n+\n+#define MBOX_POLL_RESP_TIMEOUT\t\t50 /* ms */\n+\n+static int mbox_polling_resp(u32 rout)\n+{\n+\tu32 rin;\n+\tunsigned long start = get_timer(0);\n+\n+\twhile (1) {\n+\t\trin = readl(&mbox_base->rin);\n+\t\tif (rout != rin)\n+\t\t\treturn 0;\n+\n+\t\tif (get_timer(start) > MBOX_POLL_RESP_TIMEOUT)\n+\t\t\tbreak;\n+\n+\t\tudelay(1);\n+\t}\n+\n+\tdebug(\"mailbox: polling response timeout\\n\");\n+\treturn -ETIMEDOUT;\n+}\n+\n+/* Check for available slot and write to circular buffer.\n+ * It also update command valid offset (cin) register.\n+ */\n+static int mbox_fill_cmd_circular_buff(u32 header, u32 len, u32 *arg)\n+{\n+\tu32 cmd_free_offset;\n+\tu32 i;\n+\n+\t/* checking available command free slot */\n+\tcmd_free_offset = readl(&mbox_base->cout);\n+\tif (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) {\n+\t\terror(\"ERROR: Not enough space, cout %d\\n\", cmd_free_offset);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* write header to circular buffer */\n+\twritel(header, &mbox_base->cmd_buf[cmd_free_offset++]);\n+\t/* wrapping around when it reach the buffer size */\n+\tcmd_free_offset %= MBOX_CMD_BUFFER_SIZE;\n+\n+\t/* write arguments */\n+\tfor (i = 0; i < len; i++) {\n+\t\twritel(arg[i], &mbox_base->cmd_buf[cmd_free_offset++]);\n+\t\t/* wrapping around when it reach the buffer size */\n+\t\tcmd_free_offset %= MBOX_CMD_BUFFER_SIZE;\n+\t}\n+\n+\t/* write command valid offset */\n+\twritel(cmd_free_offset, &mbox_base->cin);\n+\treturn 0;\n+}\n+\n+/* Support one command and up to 31 words argument length only */\n+int mbox_send_cmd(u8 id, u32 cmd, u32 len, u32 *arg, u8 urgent,\n+\t\t\tu32 *resp_buf_len, u32 *resp_buf)\n+{\n+\tu32 header;\n+\tu32 rin;\n+\tu32 resp;\n+\tu32 rout;\n+\tu32 status;\n+\tu32 resp_len;\n+\tu32 buf_len;\n+\tint ret;\n+\n+\t/* Total lenght is command + argument length */\n+\tif ((len + 1) > MBOX_CMD_BUFFER_SIZE) {\n+\t\terror(\"ERROR: command %d arguments too long, max %d\\n\", cmd,\n+\t\t MBOX_CMD_BUFFER_SIZE - 1);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (cmd > MBOX_MAX_CMD_INDEX) {\n+\t\terror(\"ERROR: Unsupported command index %d\\n\", cmd);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\theader = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id , len, cmd);\n+\n+\tret = mbox_fill_cmd_circular_buff(header, len, arg);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (urgent) {\n+\t\t/* Send command as urgent command */\n+\t\twritel(1, &mbox_base->urg);\n+\t}\n+\n+\t/* write doorbell */\n+\twritel(1, MBOX_DOORBELL_TO_SDM_REG);\n+\n+\twhile (1) {\n+\t\t/* Wait for doorbell from SDM */\n+\t\tret = wait_for_bit(__func__,\n+\t\t\t\t (const u32 *)MBOX_DOORBELL_FROM_SDM_REG,\n+\t\t\t\t 1, true, 500000, false);\n+\t\tif (ret) {\n+\t\t\terror(\"mailbox: timeout from SDM\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\t/* clear interrupt */\n+\t\twritel(0, MBOX_DOORBELL_FROM_SDM_REG);\n+\n+\t\tif (urgent) {\n+\t\t\t/* urgent command doesn't has response */\n+\t\t\twritel(0, &mbox_base->urg);\n+\t\t\tstatus = readl(&mbox_base->status);\n+\t\t\tif (status & MBOX_STATUS_UA_MSK)\n+\t\t\t\treturn 0;\n+\n+\t\t\terror(\"mailbox: cmd %d no urgent ACK\\n\", cmd);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\t/* read current response offset */\n+\t\trout = readl(&mbox_base->rout);\n+\n+\t\t/* read response valid offset */\n+\t\trin = readl(&mbox_base->rin);\n+\n+\t\tif (rout != rin) {\n+\t\t\t/* Response received */\n+\t\t\tresp = readl(&mbox_base->resp_buf[rout]);\n+\t\t\trout++;\n+\t\t\t/* wrapping around when it reach the buffer size */\n+\t\t\trout %= MBOX_RESP_BUFFER_SIZE;\n+\t\t\t/* update next ROUT */\n+\t\t\twritel(rout, &mbox_base->rout);\n+\n+\t\t\t/* check client ID and ID */\n+\t\t\tif ((MBOX_RESP_CLIENT_GET(resp) ==\n+\t\t\t MBOX_CLIENT_ID_UBOOT) &&\n+\t\t\t (MBOX_RESP_ID_GET(resp) == id)) {\n+\t\t\t\tret = MBOX_RESP_ERR_GET(resp);\n+\t\t\t\tif (ret) {\n+\t\t\t\t\terror(\"mailbox send command %d error %d\\n\",\n+\t\t\t\t\t cmd, ret);\n+\t\t\t\t\treturn ret;\n+\t\t\t\t}\n+\n+\t\t\t\tif (resp_buf_len) {\n+\t\t\t\t\tbuf_len = *resp_buf_len;\n+\t\t\t\t\t*resp_buf_len = 0;\n+\t\t\t\t} else {\n+\t\t\t\t\tbuf_len = 0;\n+\t\t\t\t}\n+\n+\t\t\t\tresp_len = MBOX_RESP_LEN_GET(resp);\n+\t\t\t\twhile (resp_len) {\n+\t\t\t\t\tret = mbox_polling_resp(rout);\n+\t\t\t\t\tif (ret)\n+\t\t\t\t\t\treturn ret;\n+\t\t\t\t\t/* we need to process response buffer\n+\t\t\t\t\t even caller doesn't need it */\n+\t\t\t\t\tresp = readl(&mbox_base->resp_buf[rout]);\n+\t\t\t\t\trout++;\n+\t\t\t\t\tresp_len--;\n+\t\t\t\t\trout %= MBOX_RESP_BUFFER_SIZE;\n+\t\t\t\t\twritel(rout, &mbox_base->rout);\n+\t\t\t\t\tif (buf_len) {\n+\t\t\t\t\t\t/* copy response to buffer */\n+\t\t\t\t\t\tresp_buf[*resp_buf_len] = resp;\n+\t\t\t\t\t\t(*resp_buf_len)++;\n+\t\t\t\t\t\tbuf_len--;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\t};\n+\n+\treturn -EIO;\n+}\n+\n+int mbox_init(void)\n+{\n+\tint ret;\n+\n+\t/* enable mailbox interrupts */\n+\twritel(MBOX_ALL_INTRS, &mbox_base->flags);\n+\n+\tret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, 0, NULL, 1, 0, NULL);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Renable mailbox interrupts after MBOX_RESTART */\n+\twritel(MBOX_ALL_INTRS, &mbox_base->flags);\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_CADENCE_QSPI\n+int mbox_qspi_close(void)\n+{\n+\treturn mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, 0, NULL, 0, 0,\n+\t\t\t NULL);\n+}\n+\n+int mbox_qspi_open(void)\n+{\n+\tint ret;\n+\n+\tret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, 0, NULL, 0, 0, NULL);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, 0, NULL, 0, 0,\n+\t\t\t NULL);\n+\tif (ret)\n+\t\tgoto error;\n+\n+\treturn ret;\n+\n+error:\n+\tmbox_qspi_close();\n+\n+\treturn ret;\n+}\n+#endif /* CONFIG_CADENCE_QSPI */\n+\n", "prefixes": [ "U-Boot", "07/14" ] }