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GET /api/patches/815363/?format=api
{ "id": 815363, "url": "http://patchwork.ozlabs.org/api/patches/815363/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-10-git-send-email-chin.liang.see@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505812951-25088-10-git-send-email-chin.liang.see@intel.com>", "list_archive_url": null, "date": "2017-09-19T09:22:26", "name": "[U-Boot,09/14] arm: socfpga: Restructure the SPL file", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "ca59926a9a4179d29809814392d106d7161e4ef6", "submitter": { "id": 70182, "url": "http://patchwork.ozlabs.org/api/people/70182/?format=api", "name": "See, Chin Liang", "email": "chin.liang.see@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-10-git-send-email-chin.liang.see@intel.com/mbox/", "series": [ { "id": 3810, "url": "http://patchwork.ozlabs.org/api/series/3810/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3810", "date": "2017-09-19T09:22:17", "name": "Enable Stratix10 SoC support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3810/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815363/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815363/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHc84KtSz9sMN\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 19:28:24 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 51802C21EC9; Tue, 19 Sep 2017 09:26:52 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 98CB8C21F05;\n\tTue, 19 Sep 2017 09:24:14 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 02C34C21F00; Tue, 19 Sep 2017 09:23:39 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby lists.denx.de (Postfix) with ESMTPS id 584F2C21EDE\n\tfor <u-boot@lists.denx.de>; Tue, 19 Sep 2017 09:23:33 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:31 -0700", "from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:22:56 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220782326\"", "From": "chin.liang.see@intel.com", "To": "u-boot@lists.denx.de,\n\tMarek Vasut <marex@denx.de>", "Date": "Tue, 19 Sep 2017 17:22:26 +0800", "Message-Id": "<1505812951-25088-10-git-send-email-chin.liang.see@intel.com>", "X-Mailer": "git-send-email 2.2.2", "In-Reply-To": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "References": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "Cc": "Tien Fong Chee <tien.fong.chee@intel.com>,\n\tChin Liang See <chin.liang.see@intel.com>", "Subject": "[U-Boot] [PATCH 09/14] arm: socfpga: Restructure the SPL file", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Chin Liang See <chin.liang.see@intel.com>\n\nRestructure the SPL so each devices such as CV, A10 and S10\nwill have their own dedicated SPL file. SPL file determine\nthe HW initialization flow which is device specific\n\nSigned-off-by: Chin Liang See <chin.liang.see@intel.com>\n---\n arch/arm/mach-socfpga/Makefile | 5 +-\n arch/arm/mach-socfpga/spl_a10.c | 105 ++++++++++++++++++++++++++++\n arch/arm/mach-socfpga/{spl.c => spl_gen5.c} | 46 ------------\n 3 files changed, 109 insertions(+), 47 deletions(-)\n create mode 100644 arch/arm/mach-socfpga/spl_a10.c\n rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (83%)", "diff": "diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile\nindex 098e5e9..b669d43 100644\n--- a/arch/arm/mach-socfpga/Makefile\n+++ b/arch/arm/mach-socfpga/Makefile\n@@ -41,13 +41,16 @@ obj-y\t+= wrap_pinmux_config_s10.o\n obj-y\t+= wrap_pll_config_s10.o\n endif\n ifdef CONFIG_SPL_BUILD\n-obj-y\t+= spl.o\n ifdef CONFIG_TARGET_SOCFPGA_GEN5\n+obj-y\t+= spl_gen5.o\n obj-y\t+= freeze_controller.o\n obj-y\t+= wrap_iocsr_config.o\n obj-y\t+= wrap_pinmux_config.o\n obj-y\t+= wrap_sdram_config.o\n endif\n+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10\n+obj-y\t+= spl_a10.o\n+endif\n endif\n \n ifdef CONFIG_TARGET_SOCFPGA_GEN5\ndiff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c\nnew file mode 100644\nindex 0000000..e6fc766\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/spl_a10.c\n@@ -0,0 +1,105 @@\n+/*\n+ * Copyright (C) 2012 Altera Corporation <www.altera.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/io.h>\n+#include <asm/pl310.h>\n+#include <asm/u-boot.h>\n+#include <asm/utils.h>\n+#include <image.h>\n+#include <asm/arch/reset_manager.h>\n+#include <spl.h>\n+#include <asm/arch/system_manager.h>\n+#include <asm/arch/freeze_controller.h>\n+#include <asm/arch/clock_manager.h>\n+#include <asm/arch/scan_manager.h>\n+#include <asm/arch/sdram.h>\n+#include <asm/arch/scu.h>\n+#include <asm/arch/nic301.h>\n+#include <asm/sections.h>\n+#include <fdtdec.h>\n+#include <watchdog.h>\n+#include <asm/arch/pinmux.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static const struct socfpga_system_manager *sysmgr_regs =\n+\t(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;\n+\n+u32 spl_boot_device(void)\n+{\n+\tconst u32 bsel = readl(&sysmgr_regs->bootinfo);\n+\n+\tswitch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {\n+\tcase 0x1:\t/* FPGA (HPS2FPGA Bridge) */\n+\t\treturn BOOT_DEVICE_RAM;\n+\tcase 0x2:\t/* NAND Flash (1.8V) */\n+\tcase 0x3:\t/* NAND Flash (3.0V) */\n+\t\tsocfpga_per_reset(SOCFPGA_RESET(NAND), 0);\n+\t\treturn BOOT_DEVICE_NAND;\n+\tcase 0x4:\t/* SD/MMC External Transceiver (1.8V) */\n+\tcase 0x5:\t/* SD/MMC Internal Transceiver (3.0V) */\n+\t\tsocfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);\n+\t\tsocfpga_per_reset(SOCFPGA_RESET(DMA), 0);\n+\t\treturn BOOT_DEVICE_MMC1;\n+\tcase 0x6:\t/* QSPI Flash (1.8V) */\n+\tcase 0x7:\t/* QSPI Flash (3.0V) */\n+\t\tsocfpga_per_reset(SOCFPGA_RESET(QSPI), 0);\n+\t\treturn BOOT_DEVICE_SPI;\n+\tdefault:\n+\t\tprintf(\"Invalid boot device (bsel=%08x)!\\n\", bsel);\n+\t\thang();\n+\t}\n+}\n+\n+#ifdef CONFIG_SPL_MMC_SUPPORT\n+u32 spl_boot_mode(const u32 boot_device)\n+{\n+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)\n+\treturn MMCSD_MODE_FS;\n+#else\n+\treturn MMCSD_MODE_RAW;\n+#endif\n+}\n+#endif\n+\n+void spl_board_init(void)\n+{\n+\t/* configuring the clock based on handoff */\n+\tcm_basic_init(gd->fdt_blob);\n+\tWATCHDOG_RESET();\n+\n+\tconfig_dedicated_pins(gd->fdt_blob);\n+\tWATCHDOG_RESET();\n+\n+\t/* Release UART from reset */\n+\tsocfpga_reset_uart(0);\n+\n+\t/* enable console uart printing */\n+\tpreloader_console_init();\n+}\n+\n+void board_init_f(ulong dummy)\n+{\n+\t/*\n+\t * Configure Clock Manager to use intosc clock instead external osc to\n+\t * ensure success watchdog operation. We do it as early as possible.\n+\t */\n+\tcm_use_intosc();\n+\n+\tsocfpga_watchdog_disable();\n+\n+\tarch_early_init_r();\n+\n+#ifdef CONFIG_HW_WATCHDOG\n+\t/* release osc1 watchdog timer 0 from reset */\n+\tsocfpga_reset_deassert_osc1wd0();\n+\n+\t/* reconfigure and enable the watchdog */\n+\thw_watchdog_init();\n+\tWATCHDOG_RESET();\n+#endif /* CONFIG_HW_WATCHDOG */\n+}\ndiff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl_gen5.c\nsimilarity index 83%\nrename from arch/arm/mach-socfpga/spl.c\nrename to arch/arm/mach-socfpga/spl_gen5.c\nindex 71bae82..9864082 100644\n--- a/arch/arm/mach-socfpga/spl.c\n+++ b/arch/arm/mach-socfpga/spl_gen5.c\n@@ -22,21 +22,15 @@\n #include <asm/sections.h>\n #include <fdtdec.h>\n #include <watchdog.h>\n-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n-#include <asm/arch/pinmux.h>\n-#endif\n \n DECLARE_GLOBAL_DATA_PTR;\n \n-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n static struct pl310_regs *const pl310 =\n \t(struct pl310_regs *)CONFIG_SYS_PL310_BASE;\n static struct scu_registers *scu_regs =\n \t(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;\n static struct nic301_registers *nic301_regs =\n \t(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;\n-#endif\n-\n static const struct socfpga_system_manager *sysmgr_regs =\n \t(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;\n \n@@ -77,7 +71,6 @@ u32 spl_boot_mode(const u32 boot_device)\n }\n #endif\n \n-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n static void socfpga_nic301_slave_ns(void)\n {\n \twritel(0x1, &nic301_regs->lwhps2fpgaregs);\n@@ -193,42 +186,3 @@ void board_init_f(ulong dummy)\n \t/* Configure simple malloc base pointer into RAM. */\n \tgd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);\n }\n-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n-void spl_board_init(void)\n-{\n-\t/* configuring the clock based on handoff */\n-\tcm_basic_init(gd->fdt_blob);\n-\tWATCHDOG_RESET();\n-\n-\tconfig_dedicated_pins(gd->fdt_blob);\n-\tWATCHDOG_RESET();\n-\n-\t/* Release UART from reset */\n-\tsocfpga_reset_uart(0);\n-\n-\t/* enable console uart printing */\n-\tpreloader_console_init();\n-}\n-\n-void board_init_f(ulong dummy)\n-{\n-\t/*\n-\t * Configure Clock Manager to use intosc clock instead external osc to\n-\t * ensure success watchdog operation. We do it as early as possible.\n-\t */\n-\tcm_use_intosc();\n-\n-\tsocfpga_watchdog_disable();\n-\n-\tarch_early_init_r();\n-\n-#ifdef CONFIG_HW_WATCHDOG\n-\t/* release osc1 watchdog timer 0 from reset */\n-\tsocfpga_reset_deassert_osc1wd0();\n-\n-\t/* reconfigure and enable the watchdog */\n-\thw_watchdog_init();\n-\tWATCHDOG_RESET();\n-#endif /* CONFIG_HW_WATCHDOG */\n-}\n-#endif\n", "prefixes": [ "U-Boot", "09/14" ] }