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GET /api/patches/815235/?format=api
{ "id": 815235, "url": "http://patchwork.ozlabs.org/api/patches/815235/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170919010000.32072-4-opendmb@gmail.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170919010000.32072-4-opendmb@gmail.com>", "list_archive_url": null, "date": "2017-09-19T01:00:00", "name": "[v4,3/3] irqchip: brcmstb-l2: Add support for the BCM7271 L2 controller", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "a5a945b1337a7aa8574f55f7684a645f3792e314", "submitter": { "id": 71144, "url": "http://patchwork.ozlabs.org/api/people/71144/?format=api", "name": "Doug Berger", "email": "opendmb@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170919010000.32072-4-opendmb@gmail.com/mbox/", "series": [ { "id": 3762, "url": "http://patchwork.ozlabs.org/api/series/3762/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=3762", "date": "2017-09-19T00:59:57", "name": "Add support for BCM7271 style interrupt controller", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/3762/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815235/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815235/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"qFvHb5wc\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xx4LP64dRz9s78\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 11:00:45 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751306AbdISBAa (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tMon, 18 Sep 2017 21:00:30 -0400", "from mail-qt0-f195.google.com ([209.85.216.195]:34059 \"EHLO\n\tmail-qt0-f195.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751471AbdISBAZ (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Mon, 18 Sep 2017 21:00:25 -0400", "by mail-qt0-f195.google.com with SMTP id q8so1435168qtb.1;\n\tMon, 18 Sep 2017 18:00:25 -0700 (PDT)", "from stb-bld-02.irv.broadcom.com ([192.19.255.250])\n\tby smtp.gmail.com with ESMTPSA id\n\tx39sm6113273qtc.93.2017.09.18.18.00.22\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 18 Sep 2017 18:00:23 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=47VLoFVfcT2CJeQ5++WDmMldt86rKmTC1LUYRtnBxrU=;\n\tb=qFvHb5wcCd29wlCfw6pvqocMVG+FKqUGmhsXZaDvFDonQaBhTHkjbmZ/aspCUIAsIl\n\t2CUlwA1ESmkY2CLu+pSyb2R8zLWROBOYieSLWFKw+mL4Z8YF+S6XLSWFM9CXSzeKHbFX\n\twuWdDdglvaOHEu6UxfhylZrpROXsaOj5xToLsz9QgyzeAGyNFtsu8OyaobkrJdkXSkAQ\n\tpSrWoMP4GElFkediYdD2IPEa8uFvuOOLqPuvHHJcvTRa/2OKOk6RN5nFG7V/Lgn3JT23\n\t7MRHNDnTHnnQbrTjn2UV2mr4wLL8+a/W4MZEIU5QqmYwAs5m47sIXcqdNC78g6DGiXxa\n\tYxIg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=47VLoFVfcT2CJeQ5++WDmMldt86rKmTC1LUYRtnBxrU=;\n\tb=EV7ZoxqYnIW4Vclsg+DS36J0YDX6J181YcpfVB2qypuqtqyjf5NCvyX/6aBn1hJfTn\n\t1V7VA7cvpXcn92I0zEwCMEMmD++XzvD6BzlpXGjGFQ2fY5yt93erwWoX0f64Dx6OsXAw\n\tV5+hrZwfKK2nTIrVeaJiXIdeA2Fq0HY+dYQ0C+ND4lQLO0nyKOXpV59StXJg5QqqJnQp\n\tjtb/z1x3ezxKhK1OOse/+hPEWR03WbPBthIK9M4HK4jAEMyFwkFv7sI0SMypq/4fPfTB\n\th9lqtYCyzp7+nzPq2H8QGwL9GA5xQ43zqqwNOomVhNtQuYeOwbzM3exop3UvAKcc05JN\n\t/pgw==", "X-Gm-Message-State": "AHPjjUgazh7mwwXi/JlXUIqH+Pd0N4BZtOuZgzKMBN/1UQLnvpykd11k\n\t/JOqtIgY1cWnKQ==", "X-Google-Smtp-Source": "AOwi7QB6aB72ySjszYPFuI1ZbiBK3PeWjlrBiTFSOYNM2VoGYUM451CoyQxSBpj1mReldwswNcsdcg==", "X-Received": "by 10.200.41.232 with SMTP id 37mr5462874qtt.47.1505782824489;\n\tMon, 18 Sep 2017 18:00:24 -0700 (PDT)", "From": "Doug Berger <opendmb@gmail.com>", "To": "Thomas Gleixner <tglx@linutronix.de>", "Cc": "Doug Berger <opendmb@gmail.com>, Jason Cooper <jason@lakedaemon.net>,\n\tMarc Zyngier <marc.zyngier@arm.com>, Rob Herring <robh+dt@kernel.org>,\n\tMark Rutland <mark.rutland@arm.com>,\n\tKevin Cernekee <cernekee@gmail.com>, \n\tFlorian Fainelli <f.fainelli@gmail.com>,\n\tBrian Norris <computersforpeace@gmail.com>,\n\tGregory Fong <gregory.0xf0@gmail.com>,\n\tbcm-kernel-feedback-list@broadcom.com,\n\tMarc Gonzalez <marc_gonzalez@sigmadesigns.com>,\n\tMans Rullgard <mans@mansr.com>, Mason <slash.tmp@free.fr>,\n\tBartosz Golaszewski <brgl@bgdev.pl>, Sebastian Frias <sf84@laposte.net>, \n\tBoris Brezillon <boris.brezillon@free-electrons.com>,\n\tlinux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-mips@linux-mips.org, linux-arm-kernel@lists.infradead.org", "Subject": "[PATCH v4 3/3] irqchip: brcmstb-l2: Add support for the BCM7271 L2\n\tcontroller", "Date": "Mon, 18 Sep 2017 18:00:00 -0700", "Message-Id": "<20170919010000.32072-4-opendmb@gmail.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170919010000.32072-1-opendmb@gmail.com>", "References": "<20170919010000.32072-1-opendmb@gmail.com>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Add the initialization of the generic irq chip for the BCM7271 L2\ninterrupt controller. This controller only supports level\ninterrupts and uses the \"brcm,bcm7271-l2-intc\" compatibility\nstring.\n\nAcked-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Doug Berger <opendmb@gmail.com>\n---\n .../bindings/interrupt-controller/brcm,l2-intc.txt | 3 +-\n drivers/irqchip/irq-brcmstb-l2.c | 86 ++++++++++++++++------\n 2 files changed, 66 insertions(+), 23 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt\nindex 448273a30a11..36df06c5c567 100644\n--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt\n+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt\n@@ -2,7 +2,8 @@ Broadcom Generic Level 2 Interrupt Controller\n \n Required properties:\n \n-- compatible: should be \"brcm,l2-intc\"\n+- compatible: should be \"brcm,l2-intc\" for latched interrupt controllers\n+ should be \"brcm,bcm7271-l2-intc\" for level interrupt controllers\n - reg: specifies the base physical address and size of the registers\n - interrupt-controller: identifies the node as an interrupt controller\n - #interrupt-cells: specifies the number of cells needed to encode an\ndiff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c\nindex 8d54cd7a090d..691d20eb0bec 100644\n--- a/drivers/irqchip/irq-brcmstb-l2.c\n+++ b/drivers/irqchip/irq-brcmstb-l2.c\n@@ -31,13 +31,34 @@\n #include <linux/irqchip.h>\n #include <linux/irqchip/chained_irq.h>\n \n-/* Register offsets in the L2 interrupt controller */\n-#define CPU_STATUS\t0x00\n-#define CPU_SET\t\t0x04\n-#define CPU_CLEAR\t0x08\n-#define CPU_MASK_STATUS\t0x0c\n-#define CPU_MASK_SET\t0x10\n-#define CPU_MASK_CLEAR\t0x14\n+struct brcmstb_intc_init_params {\n+\tirq_flow_handler_t handler;\n+\tint cpu_status;\n+\tint cpu_clear;\n+\tint cpu_mask_status;\n+\tint cpu_mask_set;\n+\tint cpu_mask_clear;\n+};\n+\n+/* Register offsets in the L2 latched interrupt controller */\n+static const struct brcmstb_intc_init_params l2_edge_intc_init = {\n+\t.handler\t\t= handle_edge_irq,\n+\t.cpu_status\t\t= 0x00,\n+\t.cpu_clear\t\t= 0x08,\n+\t.cpu_mask_status\t= 0x0c,\n+\t.cpu_mask_set\t\t= 0x10,\n+\t.cpu_mask_clear\t\t= 0x14\n+};\n+\n+/* Register offsets in the L2 level interrupt controller */\n+static const struct brcmstb_intc_init_params l2_lvl_intc_init = {\n+\t.handler\t\t= handle_level_irq,\n+\t.cpu_status\t\t= 0x00,\n+\t.cpu_clear\t\t= -1, /* Register not present */\n+\t.cpu_mask_status\t= 0x04,\n+\t.cpu_mask_set\t\t= 0x08,\n+\t.cpu_mask_clear\t\t= 0x0C\n+};\n \n /* L2 intc private data structure */\n struct brcmstb_l2_intc_data {\n@@ -128,7 +149,7 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)\n \tstruct brcmstb_l2_intc_data *b = gc->private;\n \n \tirq_gc_lock(gc);\n-\tif (ct->chip.irq_ack != irq_gc_noop) {\n+\tif (ct->chip.irq_ack) {\n \t\t/* Clear unmasked non-wakeup interrupts */\n \t\tirq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,\n \t\t\t\tct->regs.ack);\n@@ -141,7 +162,9 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)\n }\n \n static int __init brcmstb_l2_intc_of_init(struct device_node *np,\n-\t\t\t\t\t struct device_node *parent)\n+\t\t\t\t\t struct device_node *parent,\n+\t\t\t\t\t const struct brcmstb_intc_init_params\n+\t\t\t\t\t *init_params)\n {\n \tunsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;\n \tstruct brcmstb_l2_intc_data *data;\n@@ -163,12 +186,12 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,\n \t}\n \n \t/* Disable all interrupts by default */\n-\twritel(0xffffffff, base + CPU_MASK_SET);\n+\twritel(0xffffffff, base + init_params->cpu_mask_set);\n \n \t/* Wakeup interrupts may be retained from S5 (cold boot) */\n \tdata->can_wake = of_property_read_bool(np, \"brcm,irq-can-wake\");\n-\tif (!data->can_wake)\n-\t\twritel(0xffffffff, base + CPU_CLEAR);\n+\tif (!data->can_wake && (init_params->cpu_clear >= 0))\n+\t\twritel(0xffffffff, base + init_params->cpu_clear);\n \n \tparent_irq = irq_of_parse_and_map(np, 0);\n \tif (!parent_irq) {\n@@ -193,7 +216,7 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,\n \n \t/* Allocate a single Generic IRQ chip for this node */\n \tret = irq_alloc_domain_generic_chips(data->domain, 32, 1,\n-\t\t\t\tnp->full_name, handle_edge_irq, clr, 0, flags);\n+\t\t\tnp->full_name, init_params->handler, clr, 0, flags);\n \tif (ret) {\n \t\tpr_err(\"failed to allocate generic irq chip\\n\");\n \t\tgoto out_free_domain;\n@@ -206,21 +229,26 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,\n \tdata->gc = irq_get_domain_generic_chip(data->domain, 0);\n \tdata->gc->reg_base = base;\n \tdata->gc->private = data;\n-\tdata->status_offset = CPU_STATUS;\n-\tdata->mask_offset = CPU_MASK_STATUS;\n+\tdata->status_offset = init_params->cpu_status;\n+\tdata->mask_offset = init_params->cpu_mask_status;\n \n \tct = data->gc->chip_types;\n \n-\tct->chip.irq_ack = irq_gc_ack_set_bit;\n-\tct->regs.ack = CPU_CLEAR;\n+\tif (init_params->cpu_clear >= 0) {\n+\t\tct->regs.ack = init_params->cpu_clear;\n+\t\tct->chip.irq_ack = irq_gc_ack_set_bit;\n+\t\tct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;\n+\t} else {\n+\t\t/* No Ack - but still slightly more efficient to define this */\n+\t\tct->chip.irq_mask_ack = irq_gc_mask_disable_reg;\n+\t}\n \n \tct->chip.irq_mask = irq_gc_mask_disable_reg;\n-\tct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;\n-\tct->regs.disable = CPU_MASK_SET;\n-\tct->regs.mask = CPU_MASK_STATUS;\n+\tct->regs.disable = init_params->cpu_mask_set;\n+\tct->regs.mask = init_params->cpu_mask_status;\n \n \tct->chip.irq_unmask = irq_gc_unmask_enable_reg;\n-\tct->regs.enable = CPU_MASK_CLEAR;\n+\tct->regs.enable = init_params->cpu_mask_clear;\n \n \tct->chip.irq_suspend = brcmstb_l2_intc_suspend;\n \tct->chip.irq_resume = brcmstb_l2_intc_resume;\n@@ -247,4 +275,18 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,\n \tkfree(data);\n \treturn ret;\n }\n-IRQCHIP_DECLARE(brcmstb_l2_intc, \"brcm,l2-intc\", brcmstb_l2_intc_of_init);\n+\n+int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,\n+\tstruct device_node *parent)\n+{\n+\treturn brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);\n+}\n+IRQCHIP_DECLARE(brcmstb_l2_intc, \"brcm,l2-intc\", brcmstb_l2_edge_intc_of_init);\n+\n+int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,\n+\tstruct device_node *parent)\n+{\n+\treturn brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);\n+}\n+IRQCHIP_DECLARE(bcm7271_l2_intc, \"brcm,bcm7271-l2-intc\",\n+\tbrcmstb_l2_lvl_intc_of_init);\n", "prefixes": [ "v4", "3/3" ] }