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GET /api/patches/815168/?format=api
{ "id": 815168, "url": "http://patchwork.ozlabs.org/api/patches/815168/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1505767187-4596-11-git-send-email-roy.pledge@nxp.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1505767187-4596-11-git-send-email-roy.pledge@nxp.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1505767187-4596-11-git-send-email-roy.pledge@nxp.com/", "date": "2017-09-18T20:39:45", "name": "[v5,10/12] soc/fsl/qbman: different register offsets on ARM", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "b3ac2c4e1f714e9f6cec55cbe9118dda4efbd4c6", "submitter": { "id": 70252, "url": "http://patchwork.ozlabs.org/api/people/70252/?format=api", "name": "Roy Pledge", "email": "roy.pledge@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1505767187-4596-11-git-send-email-roy.pledge@nxp.com/mbox/", "series": [ { "id": 3731, "url": "http://patchwork.ozlabs.org/api/series/3731/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=3731", "date": "2017-09-18T20:39:38", "name": "soc/fsl/qbman: Enable QBMan on ARM Platforms", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/3731/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815168/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815168/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwyxw2LtFz9s7m\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 19 Sep 2017 06:57:40 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xwyxw1SyhzDrJR\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 19 Sep 2017 06:57:40 +1000 (AEST)", "from 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\n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Roy Pledge <roy.pledge@nxp.com>", "To": "<leoyang.li@nxp.com>, <linuxppc-dev@lists.ozlabs.org>,\n\t<linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>", "Subject": "[v5 10/12] soc/fsl/qbman: different register offsets on ARM", "Date": "Mon, 18 Sep 2017 16:39:45 -0400", "Message-ID": "<1505767187-4596-11-git-send-email-roy.pledge@nxp.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505767187-4596-1-git-send-email-roy.pledge@nxp.com>", "References": "<1505767187-4596-1-git-send-email-roy.pledge@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131502408006517762;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(336005)(39860400002)(39380400002)(346002)(376002)(2980300002)(1110001)(1109001)(339900001)(189002)(199003)(105606002)(97736004)(106466001)(36756003)(189998001)(50466002)(5660300001)(6666003)(7416002)(77096006)(86362001)(50226002)(2201001)(316002)(4326008)(5003940100001)(16586007)(3450700001)(33646002)(85426001)(48376002)(54906002)(356003)(43066003)(8936002)(498600001)(68736007)(81156014)(81166006)(8676002)(8656003)(2950100002)(53936002)(2906002)(50986999)(104016004)(305945005)(76176999)(47776003)(110136005)(2101003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR03MB2703;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; ", "X-Microsoft-Exchange-Diagnostics": [ "1; BY2FFO11OLC003;\n\t1:npokkwdsQvw/jyTHzUBbnF6vIfa3lXS0XQSNbbpIfCPp5NpaXfYUzd5w7mpwNr9GiWnzVIR3csHVZuEJRAIoBo45MBNhwIwrYKp8tCyXj1W/WLQNUCaE1TkkNcXEAYct", "1; MWHPR03MB2703;\n\t3:4u7c3POpMW42PVcDCWrKKqVQAH9kGcFTs2vl57ZWRQtr5vDzDQ1jf5i4cLCvyJPkSSTmdlJU5bddNwlXL3neGuhxK28RS51Vc/O0NR6ra8OO8EchhF8RwwbFTKaOPEEs7N8z0UImtQItYpDmzjiP4YhckxYpctWrp/NyuisWJUSAUXW276MXxG8Tajs+tQPSXBqtIJv6ThtB/NUq5AiP/ipxwTcU6W2GXGl+ojoo89zrav561+Q05kPuCzQhalOz4gfjECOesI/crW0aCwd0Ir8cu6PG9BJ27pm+oEF8Bm2MjMzyw57BGo+PTdf+taRWxeivV/VbDp9ABwBcKd93Wd+UQphwAGwf1dE+gk0g714=;\n\t25:mPa7PYGh1TBGBNnE8OGfdaR9W8s2NImBm79JK146MjCUwFLhUA+nJzCvCJLCUNqEo70f/Xatz2b8DL+CeiH3SBSBvaRaEb3Cori87AV05c1zbZOCe0yjLSyzj5bjkV3pnPmjeC0xn2KmbQPrHsVDNFjRyuxoTnPhYLF/dVw1d2KtqrHa2Vyij5fOpAS4jrDfGPDohssSw3l/WkmSH+MCuklDKVNycIPT3U4kU3QdSKmRiyu3Cn+KXJMkcz7qz2lN4ujqUE6V1namdE4OJZCrgSktt2dLmk8nJoq421zrjj0KLuIzIvteFcs+2J9MM/uvWeH/r+joNYL/MoRwHWRzgQ==", "1; MWHPR03MB2703;\n\t31:7g7/C1m1x77qRPjJL5WENzt8D2WgRehvQZe0WKajq8wjRKD2CdMDxfd7cV0JOKqXnJbxSSj/z2UAFmDoUHhliC/mfemthQrMz/hE/yRM/BrdBKicpfNljY38rqCKnr6PDJOBNaVO8rZ4Qci93rCewpEZcCNYUKn3WGZNoR4Ll0OcC5wfkIetRBKFITYo70VEpDCdQuI1FltBpUDuU4slJCWhCahn/m7Nvdi8pZ0Uabk=;\n\t4:FmlL+7ODHku7ywmMGZeysgW9jdMKp7t5NxiVOSmrjqaW1NfkybU5s1B2V5QCEDUCuy/GmCzVCqpO8M1vp1pjVfeDNobl0l28ubHgqt8LmO+dAoMTTBcVcDjlGcn4g+ZmEG3KNpEy0MAMbsWKQfuQDVXory13rnNEMs0K6Mtq3Tji7h8uxNf+Wr8aZ3HXccnvBOffw93byi6j0MLUol3lb03PT03+KsPxW6uoY8EESjLAjACugr+Fhenwxx9tcaVyh5ZWLf31PADja32dYmQXcR6kNSJBd+wD0WlZWfw8dtqcH5p5xuRUTdmf5XKBDm4zyxnxF6WYcqZm2MWIo8B4VQ==", "=?us-ascii?Q?1; MWHPR03MB2703;\n\t23:NDJFe1OZauqCKfT8LywnhYB5KMmxN+dFXY0WhI5q3?=\n\tUi+T9Pel4oMZafrGaklCc0UqqfccE2zC6SUktIGYPzArz6luYSVDyr8o+OWN5BRv+YC7r2oiDcMsVEabmkc9l5P2VODqRwpde2a+j4vsTB34YTYTj3xv0eAQHk6Xj12r4oV2NwDQU/9bYJdV0EOXkBR/AdCxlkrJc5hP6WiDHbEsSiGxEE0KvXP7MRDf0Nc1NrplnEsphhDWNFip42aGenG48BZgtdCyqV7hCtKryzjAFijusawtLlY8lA2TCNq9/XzbASfUnolieaOzekSWlgY/1tdwGLcLbQJoOrk6/6bMR9Ny6vGGHdsutp8k7jV4jJ592qodeB4lrsLduyudUJadpssObfMGxKXu/dP1KW8YszsR+mj47NovVJ8R7sZ057XrHBvVp06pmod99obM1d1CR9CZcFIqcutHkzhn5Z52cBSf+M8UdBLXZvAVz2QZnkIHiqJDGa6loBAn1EFDBwk2QmnJzmzdStHlD8ZYBvjT4lq6hCRCB+/uqxnRnZ7f1QkjRo+HdIH2tlAmpRPGpa4ucDhfpM6FQF/q4cku5nVvbKnHx5rhLLI+VDsi5rFbZ5j+QdqdQ8y9vTWZNaIqeWsRemNKxLD0RgYbb5nY2oRYrSn8Ia6wjCGNxl3HZxCsjUNayFqOrN+4Ys70R9u3V1Kww/pYsHOBXTnkeUTMpEJ/G76MwKX1p0ITJJyHyTUx2RTilLFLE5rT+MM/0qA9L5qqVhU6TKw4Yv/TWJhw9uvQW8BKhiM2TsQ/aFNjP7uhhbTqZX/vQv90Qf/AZWlZc+qlzD03SG0p0ll0/Qqb0n9cyfSEYZg7kotIp/xM5CQCwx2e5RRajEwiV2N0efdlU404JvDbxDHBiLUgNKGO8KHnv2BEX5sqsE1nhoyZCKRk29fn4PKimMqLap47x6l0PoAzbSNg6iTdupZm0D98OdnvLrnY++27REmpgVg+meVA3aeV7efCjR89fF0CAaxhcRkn6ywIafZtbfRqECSfvpLTvV1u6IX1CsP9xseF+RkwQCG/pPmAZItwIzGyyvYkwrUYDIu/MqHtEjZV3Y219pxZ4V2e40lB0MRmQNV68KmfHIeAuB+jeqnrhbQOAmKkvzX48MHMqFKnj3UzftX70wAFBZiJWS9DqKZYVe1ffQSBPIxjU2trb/a0YrGA6cA8hHcfsUeprYFLRYrGmuUAXgbUwBYqRZSDR5f+PFcSr3XMBw=", "1; MWHPR03MB2703;\n\t6:0UpRs2uaKBTVDY5hFBmMD6JlJX8vKOnX5Ivs8+UoDRfKwxVKuGBNIbVSe3gCUn93ByqcD6GBT4X9MYjmpEV5vGOiIMqY3Rk//5tk2/fFAgRwwXEgPezpbG8rBECkq7EUWsIkOhrxfRiNQ3yDYf5rKNwy7MK6zcgALdLC1hrcOsFK+hjdXOruhn4oGlrh4I5jf5E4abo8sO5KEKUdn54m4KcM9zG5ja4q4qh0MIzlLIKjtNDX6lRrfaqz9KPDXEc4iMpQX7J8qVSlITATfGNYUn62qJciA14xlaJicNYdjlSbkBDnxn+NaZ21VHUA3h6ItlNQGTSaITt8naAZOLlP9w==;\n\t5:614vyv9PXPMlM79thxvXIDDi1cKR57HoufKC8fG+OR8jBnHTx2IY8h3y32yTnNCsFmaU8nsyhKHaMwqYxbYj01S52QJlhlzt/DC7dfiwAxlMP1J9NcONRVkTQf8m/Gc58i8kXd62uHossQ3HlJnEuQ==;\n\t24:fK/FmW7C2UYsO/I75Gg3BDcj0SAjYoRrQF2KjgXZhZSkO/NX1+VGSj0tm+bNaoVgG3d53x8z/3G645LPAiv0NSi+RDUpH6jAnIncXNtRVao=;\n\t7:NoOKHklhCLK7L8gpSxSSd+Vo3azdRPct7hO+NQEvRe/wVfzjzpHYrWryfDlszxFZoCBkLJ4/qcx//RMjbrw0v4ijFhf+/Z/lZhpSI0KWacGwlmofmEKPTayCTGO70316yXCVt1WuhTNiyIqjH7DFPkjthSpIKFWPHPsV+W2IX7MdMEm0QpsJ/aTLThrAmMv64fb4dHP5D/IMmbqCWcYVqNW+FMOl/iQnd+4+690JEU8=" ], "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b47d7d99-77d7-40e5-4402-08d4fed56ecd", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(300000503095)(300135400095)(2017052603199)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:MWHPR03MB2703; ", "X-MS-TrafficTypeDiagnostic": "MWHPR03MB2703:", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197)(275809806118684); ", "X-Microsoft-Antispam-PRVS": "<MWHPR03MB2703AA2D06D1A6626D9FAB1C86630@MWHPR03MB2703.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(2401047)(8121501046)(5005006)(93006095)(93001095)(10201501046)(100000703101)(100105400095)(3002001)(6055026)(6096035)(20161123561025)(20161123556025)(20161123559100)(20161123565025)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(20161123563025)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:MWHPR03MB2703; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:MWHPR03MB2703; ", "X-Forefront-PRVS": "04347F8039", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Sep 2017 20:40:00.4489\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR03MB2703", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Reply-To": "roy.pledge@nxp.com", "Cc": "mark.rutland@arm.com, arnd@arndb.de, madalin.bucur@nxp.com,\n\tcatalin.marinas@arm.com, Roy Pledge <roy.pledge@nxp.com>,\n\tlinux@armlinux.org.uk, oss@buserror.net,\n\tClaudiu Manoil <claudiu.manoil@nxp.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "From: Madalin Bucur <madalin.bucur@nxp.com>\n\nSigned-off-by: Madalin Bucur <madalin.bucur@nxp.com>\nSigned-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>\nSigned-off-by: Roy Pledge <roy.pledge@nxp.com>\n---\n drivers/soc/fsl/qbman/bman.c | 22 ++++++++++++++++++++++\n drivers/soc/fsl/qbman/qman.c | 38 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 60 insertions(+)", "diff": "diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c\nindex 5dbb5cc..2e6e682 100644\n--- a/drivers/soc/fsl/qbman/bman.c\n+++ b/drivers/soc/fsl/qbman/bman.c\n@@ -35,6 +35,27 @@\n \n /* Portal register assists */\n \n+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)\n+/* Cache-inhibited register offsets */\n+#define BM_REG_RCR_PI_CINH\t0x3000\n+#define BM_REG_RCR_CI_CINH\t0x3100\n+#define BM_REG_RCR_ITR\t\t0x3200\n+#define BM_REG_CFG\t\t0x3300\n+#define BM_REG_SCN(n)\t\t(0x3400 + ((n) << 6))\n+#define BM_REG_ISR\t\t0x3e00\n+#define BM_REG_IER\t\t0x3e40\n+#define BM_REG_ISDR\t\t0x3e80\n+#define BM_REG_IIR\t\t0x3ec0\n+\n+/* Cache-enabled register offsets */\n+#define BM_CL_CR\t\t0x0000\n+#define BM_CL_RR0\t\t0x0100\n+#define BM_CL_RR1\t\t0x0140\n+#define BM_CL_RCR\t\t0x1000\n+#define BM_CL_RCR_PI_CENA\t0x3000\n+#define BM_CL_RCR_CI_CENA\t0x3100\n+\n+#else\n /* Cache-inhibited register offsets */\n #define BM_REG_RCR_PI_CINH\t0x0000\n #define BM_REG_RCR_CI_CINH\t0x0004\n@@ -53,6 +74,7 @@\n #define BM_CL_RCR\t\t0x1000\n #define BM_CL_RCR_PI_CENA\t0x3000\n #define BM_CL_RCR_CI_CENA\t0x3100\n+#endif\n \n /*\n * Portal modes.\ndiff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c\nindex 8934c27..7cb7bad 100644\n--- a/drivers/soc/fsl/qbman/qman.c\n+++ b/drivers/soc/fsl/qbman/qman.c\n@@ -41,6 +41,43 @@\n \n /* Portal register assists */\n \n+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)\n+/* Cache-inhibited register offsets */\n+#define QM_REG_EQCR_PI_CINH\t0x3000\n+#define QM_REG_EQCR_CI_CINH\t0x3040\n+#define QM_REG_EQCR_ITR\t\t0x3080\n+#define QM_REG_DQRR_PI_CINH\t0x3100\n+#define QM_REG_DQRR_CI_CINH\t0x3140\n+#define QM_REG_DQRR_ITR\t\t0x3180\n+#define QM_REG_DQRR_DCAP\t0x31C0\n+#define QM_REG_DQRR_SDQCR\t0x3200\n+#define QM_REG_DQRR_VDQCR\t0x3240\n+#define QM_REG_DQRR_PDQCR\t0x3280\n+#define QM_REG_MR_PI_CINH\t0x3300\n+#define QM_REG_MR_CI_CINH\t0x3340\n+#define QM_REG_MR_ITR\t\t0x3380\n+#define QM_REG_CFG\t\t0x3500\n+#define QM_REG_ISR\t\t0x3600\n+#define QM_REG_IER\t\t0x3640\n+#define QM_REG_ISDR\t\t0x3680\n+#define QM_REG_IIR\t\t0x36C0\n+#define QM_REG_ITPR\t\t0x3740\n+\n+/* Cache-enabled register offsets */\n+#define QM_CL_EQCR\t\t0x0000\n+#define QM_CL_DQRR\t\t0x1000\n+#define QM_CL_MR\t\t0x2000\n+#define QM_CL_EQCR_PI_CENA\t0x3000\n+#define QM_CL_EQCR_CI_CENA\t0x3040\n+#define QM_CL_DQRR_PI_CENA\t0x3100\n+#define QM_CL_DQRR_CI_CENA\t0x3140\n+#define QM_CL_MR_PI_CENA\t0x3300\n+#define QM_CL_MR_CI_CENA\t0x3340\n+#define QM_CL_CR\t\t0x3800\n+#define QM_CL_RR0\t\t0x3900\n+#define QM_CL_RR1\t\t0x3940\n+\n+#else\n /* Cache-inhibited register offsets */\n #define QM_REG_EQCR_PI_CINH\t0x0000\n #define QM_REG_EQCR_CI_CINH\t0x0004\n@@ -75,6 +112,7 @@\n #define QM_CL_CR\t\t0x3800\n #define QM_CL_RR0\t\t0x3900\n #define QM_CL_RR1\t\t0x3940\n+#endif\n \n /*\n * BTW, the drivers (and h/w programming model) already obtain the required\n", "prefixes": [ "v5", "10/12" ] }