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{
    "id": 814943,
    "url": "http://patchwork.ozlabs.org/api/patches/814943/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170918134610.17743-3-jbrunet@baylibre.com/",
    "project": {
        "id": 37,
        "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api",
        "name": "Devicetree Bindings",
        "link_name": "devicetree-bindings",
        "list_id": "devicetree.vger.kernel.org",
        "list_email": "devicetree@vger.kernel.org",
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    "msgid": "<20170918134610.17743-3-jbrunet@baylibre.com>",
    "list_archive_url": null,
    "date": "2017-09-18T13:46:09",
    "name": "[v4,1/2] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller",
    "commit_ref": null,
    "pull_url": null,
    "state": "not-applicable",
    "archived": true,
    "hash": "98422ce3c4ac6274e58a23a15596e70eb97e7662",
    "submitter": {
        "id": 69839,
        "url": "http://patchwork.ozlabs.org/api/people/69839/?format=api",
        "name": "Jerome Brunet",
        "email": "jbrunet@baylibre.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170918134610.17743-3-jbrunet@baylibre.com/mbox/",
    "series": [
        {
            "id": 3650,
            "url": "http://patchwork.ozlabs.org/api/series/3650/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=3650",
            "date": "2017-09-18T13:46:07",
            "name": "irqchip: meson: add support for the gpio interrupt controller",
            "version": 4,
            "mbox": "http://patchwork.ozlabs.org/series/3650/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/814943/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/814943/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "X-Received": "by 10.223.161.137 with SMTP id u9mr14967752wru.280.1505742376200;\n\tMon, 18 Sep 2017 06:46:16 -0700 (PDT)",
        "From": "Jerome Brunet <jbrunet@baylibre.com>",
        "To": "Marc Zyngier <marc.zyngier@arm.com>, Thomas Gleixner <tglx@linutronix.de>,\n\tJason Cooper <jason@lakedaemon.net>,\n\tHeiner Kallweit <hkallweit1@gmail.com>",
        "Cc": "Jerome Brunet <jbrunet@baylibre.com>, Kevin Hilman <khilman@baylibre.com>,\n\tCarlo Caione <carlo@caione.org>, linux-amlogic@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org",
        "Subject": "[PATCH v4 1/2] dt-bindings: interrupt-controller: add DT binding for\n\tmeson GPIO interrupt controller",
        "Date": "Mon, 18 Sep 2017 15:46:09 +0200",
        "Message-Id": "<20170918134610.17743-3-jbrunet@baylibre.com>",
        "X-Mailer": "git-send-email 2.13.5",
        "In-Reply-To": "<20170918134610.17743-1-jbrunet@baylibre.com>",
        "References": "<20170918134610.17743-1-jbrunet@baylibre.com>",
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        "Content-Type": "text/plain; charset=UTF-8",
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        "Sender": "devicetree-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<devicetree.vger.kernel.org>",
        "X-Mailing-List": "devicetree@vger.kernel.org"
    },
    "content": "This commit adds the device tree bindings description for Amlogic's GPIO\ninterrupt controller available on the meson8b, gxbb and gxl SoC families\n\nCc: Heiner Kallweit <hkallweit1@gmail.com>\nSigned-off-by: Jerome Brunet <jbrunet@baylibre.com>\n---\n .../amlogic,meson-gpio-intc.txt                    | 35 ++++++++++++++++++++++\n 1 file changed, 35 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt",
    "diff": "diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt\nnew file mode 100644\nindex 000000000000..633e21ce4b17\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt\n@@ -0,0 +1,35 @@\n+Amlogic meson GPIO interrupt controller\n+\n+Meson SoCs contains an interrupt controller which is able to watch the SoC\n+pads and generate an interrupt on edge or level. The controller is essentially\n+a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge\n+or level and polarity. It does not expose all 256 mux inputs because the\n+documentation shows that the upper part is not mapped to any pad. The actual\n+number of interrupt exposed depends on the SoC.\n+\n+Required properties:\n+\n+- compatible : must have \"amlogic,meson8-gpio-intc” and either\n+   “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or\n+   “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or\n+   “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)\n+- interrupt-parent : a phandle to the GIC the interrupts are routed to.\n+   Usually this is provided at the root level of the device tree as it is\n+   common to most of the SoC.\n+- reg : Specifies base physical address and size of the registers.\n+- interrupt-controller : Identifies the node as an interrupt controller.\n+- #interrupt-cells : Specifies the number of cells needed to encode an\n+   interrupt source. The value must be 2.\n+- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These\n+   are the hwirqs used on the parent interrupt controller.\n+\n+Example:\n+\n+gpio_interrupt: interrupt-controller@9880 {\n+\tcompatible = \"amlogic,meson-gxbb-gpio-intc\",\n+\t\t     \"amlogic,meson-gpio-intc\";\n+\treg = <0x0 0x9880 0x0 0x10>;\n+\tinterrupt-controller;\n+\t#interrupt-cells = <2>;\n+\tmeson,channel-interrupts = <64 65 66 67 68 69 70 71>;\n+};\n",
    "prefixes": [
        "v4",
        "1/2"
    ]
}