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GET /api/patches/814823/?format=api
{ "id": 814823, "url": "http://patchwork.ozlabs.org/api/patches/814823/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170918082706.6485-6-npiggin@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20170918082706.6485-6-npiggin@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20170918082706.6485-6-npiggin@gmail.com/", "date": "2017-09-18T08:27:06", "name": "[5/5] powerpc/powernv: implement NMI IPI with OPAL_SIGNAL_SYSTEM_RESET", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8d8589b1c4434d8aa5a68991f72a058de8c517be", "submitter": { "id": 69518, "url": "http://patchwork.ozlabs.org/api/people/69518/?format=api", "name": "Nicholas Piggin", "email": "npiggin@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170918082706.6485-6-npiggin@gmail.com/mbox/", "series": [ { "id": 3584, "url": "http://patchwork.ozlabs.org/api/series/3584/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=3584", "date": "2017-09-18T08:27:01", "name": "More NMI IPI enablement work", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3584/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/814823/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/814823/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwfXh2qxMz9rxm\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 18 Sep 2017 18:38:12 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xwfXh1LwrzDrTW\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 18 Sep 2017 18:38:12 +1000 (AEST)", "from mail-pf0-x243.google.com (mail-pf0-x243.google.com\n\t[IPv6:2607:f8b0:400e:c00::243])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xwfJR1LXqzDrXy\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tMon, 18 Sep 2017 18:27:35 +1000 (AEST)", "by mail-pf0-x243.google.com with SMTP id q76so4300076pfq.5\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tMon, 18 Sep 2017 01:27:35 -0700 (PDT)", "from roar.au.ibm.com ([210.185.119.235])\n\tby smtp.gmail.com with ESMTPSA id\n\td18sm14293750pfk.11.2017.09.18.01.27.30\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 18 Sep 2017 01:27:31 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"MzvtdpLW\"; dkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"MzvtdpLW\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400e:c00::243; helo=mail-pf0-x243.google.com;\n\tenvelope-from=npiggin@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"MzvtdpLW\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=Lv5giSmNaUdIp9hbqRVYskoNVEFbWgsgbXgua3fA7Ng=;\n\tb=MzvtdpLWz1VwDgPsQyWzWNcfTsqKtvyN6QpFmIr9PLV+7FzZpqKhfEsDMT5w6bJdph\n\tEc7lqJbgCoiTmTlXToMrPITdfxsdVYwnBiO84NO9xgR+rMLlntPnu4qcuy1u7tNhN7JA\n\tKJUQWoImmaRQGaGOb1lE2aZfHNF48srZiTTEtZg0QeTmXDIFTLfStgjohiqa/NpfebpR\n\tGfQd0OpuEeOz0mkAZ6exz2wS59Isq4PZfFkJIivrt3xfdT/gpbADYfhV9ZVgnChaSfu0\n\tJKB6Dc1fq9lWFt5qpz51Ax5nX30BmIsWxh7ilId2p+IDCWrjVdZvRJJ3esECUWzTjeYy\n\tyftA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; 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5/5] powerpc/powernv: implement NMI IPI with\n\tOPAL_SIGNAL_SYSTEM_RESET", "Date": "Mon, 18 Sep 2017 18:27:06 +1000", "Message-Id": "<20170918082706.6485-6-npiggin@gmail.com>", "X-Mailer": "git-send-email 2.13.3", "In-Reply-To": "<20170918082706.6485-1-npiggin@gmail.com>", "References": "<20170918082706.6485-1-npiggin@gmail.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Nicholas Piggin <npiggin@gmail.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "This allows MSR[EE]=0 lockups to be detected on an OPAL (bare metal)\nsystem similarly to the hcall NMI IPI on pseries guests, when the\nplatform/firmware supports it.\n\nThis is an example of CPU10 spinning with interrupts hard disabled:\n\nWatchdog CPU:32 detected Hard LOCKUP other CPUS:10\nWatchdog CPU:10 Hard LOCKUP\nCPU: 10 PID: 4410 Comm: bash Not tainted 4.13.0-rc7-00074-ge89ce1f89f62-dirty #34\ntask: c0000003a82b4400 task.stack: c0000003af55c000\nNIP: c0000000000a7b38 LR: c000000000659044 CTR: c0000000000a7b00\nREGS: c00000000fd23d80 TRAP: 0100 Not tainted (4.13.0-rc7-00074-ge89ce1f89f62-dirty)\nMSR: 90000000000c1033 <SF,HV,ME,IR,DR,RI,LE>\nCR: 28422222 XER: 20000000\nCFAR: c0000000000a7b38 SOFTE: 0\nGPR00: c000000000659044 c0000003af55fbb0 c000000001072a00 0000000000000078\nGPR04: c0000003c81b5c80 c0000003c81cc7e8 9000000000009033 0000000000000000\nGPR08: 0000000000000000 c0000000000a7b00 0000000000000001 9000000000001003\nGPR12: c0000000000a7b00 c00000000fd83200 0000000010180df8 0000000010189e60\nGPR16: 0000000010189ed8 0000000010151270 000000001018bd88 000000001018de78\nGPR20: 00000000370a0668 0000000000000001 00000000101645e0 0000000010163c10\nGPR24: 00007fffd14d6294 00007fffd14d6290 c000000000fba6f0 0000000000000004\nGPR28: c000000000f351d8 0000000000000078 c000000000f4095c 0000000000000000\nNIP [c0000000000a7b38] sysrq_handle_xmon+0x38/0x40\nLR [c000000000659044] __handle_sysrq+0xe4/0x270\nCall Trace:\n[c0000003af55fbd0] [c000000000659044] __handle_sysrq+0xe4/0x270\n[c0000003af55fc70] [c000000000659810] write_sysrq_trigger+0x70/0xa0\n[c0000003af55fca0] [c0000000003da650] proc_reg_write+0xb0/0x110\n[c0000003af55fcf0] [c0000000003423bc] __vfs_write+0x6c/0x1b0\n[c0000003af55fd90] [c000000000344398] vfs_write+0xd8/0x240\n[c0000003af55fde0] [c00000000034632c] SyS_write+0x6c/0x110\n[c0000003af55fe30] [c00000000000b220] system_call+0x58/0x6c\n\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>\n---\n arch/powerpc/include/asm/opal-api.h | 1 +\n arch/powerpc/include/asm/opal.h | 2 ++\n arch/powerpc/kernel/irq.c | 43 +++++++++++++++++++---\n arch/powerpc/platforms/powernv/opal-wrappers.S | 1 +\n arch/powerpc/platforms/powernv/powernv.h | 1 +\n arch/powerpc/platforms/powernv/setup.c | 3 ++\n arch/powerpc/platforms/powernv/smp.c | 50 ++++++++++++++++++++++++++\n 7 files changed, 97 insertions(+), 4 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h\nindex 450a60b81d2a..9d191ebea706 100644\n--- a/arch/powerpc/include/asm/opal-api.h\n+++ b/arch/powerpc/include/asm/opal-api.h\n@@ -188,6 +188,7 @@\n #define OPAL_XIVE_DUMP\t\t\t\t142\n #define OPAL_XIVE_RESERVED3\t\t\t143\n #define OPAL_XIVE_RESERVED4\t\t\t144\n+#define OPAL_SIGNAL_SYSTEM_RESET\t\t145\n #define OPAL_NPU_INIT_CONTEXT\t\t\t146\n #define OPAL_NPU_DESTROY_CONTEXT\t\t147\n #define OPAL_NPU_MAP_LPAR\t\t\t148\ndiff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h\nindex 726c23304a57..7d7613c49f2b 100644\n--- a/arch/powerpc/include/asm/opal.h\n+++ b/arch/powerpc/include/asm/opal.h\n@@ -281,6 +281,8 @@ int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);\n int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);\n int opal_sensor_group_clear(u32 group_hndl, int token);\n \n+int64_t opal_signal_system_reset(int32_t cpu);\n+\n /* Internal functions */\n extern int early_init_dt_scan_opal(unsigned long node, const char *uname,\n \t\t\t\t int depth, void *data);\ndiff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c\nindex 4e65bf82f5e0..472d294d0df5 100644\n--- a/arch/powerpc/kernel/irq.c\n+++ b/arch/powerpc/kernel/irq.c\n@@ -394,11 +394,21 @@ bool prep_irq_for_idle_irqsoff(void)\n /*\n * Take the SRR1 wakeup reason, index into this table to find the\n * appropriate irq_happened bit.\n+ *\n+ * Sytem reset exceptions taken in idle state also come through here,\n+ * but they are NMI interrupts so do not need to wait for IRQs to be\n+ * restored, and should be taken as early as practical. These are marked\n+ * with 0xff in the table. The Power ISA specifies 0100b as the system\n+ * reset interrupt reason, but POWER9 DD1 can set 0010b.\n */\n+#define IRQ_SYSTEM_RESET\t0xff\n+\n static const u8 srr1_to_lazyirq[0x10] = {\n-\t0, 0, 0,\n-\tPACA_IRQ_DBELL,\n \t0,\n+\t0,\n+\tIRQ_SYSTEM_RESET,\n+\tPACA_IRQ_DBELL,\n+\tIRQ_SYSTEM_RESET,\n \tPACA_IRQ_DBELL,\n \tPACA_IRQ_DEC,\n \t0,\n@@ -407,15 +417,40 @@ static const u8 srr1_to_lazyirq[0x10] = {\n \tPACA_IRQ_HMI,\n \t0, 0, 0, 0, 0 };\n \n+static noinline void replay_system_reset(void)\n+{\n+\tstruct pt_regs regs;\n+\n+\tppc_save_regs(®s);\n+\tregs.trap = 0x100;\n+\tget_paca()->in_nmi = 1;\n+\tsystem_reset_exception(®s);\n+\tget_paca()->in_nmi = 0;\n+}\n+\n void irq_set_pending_from_srr1(unsigned long srr1)\n {\n \tunsigned int idx = (srr1 & SRR1_WAKEMASK_P8) >> 18;\n+\tu8 reason = srr1_to_lazyirq[idx];\n+\n+\t/*\n+\t * Take the system reset now, which is immediately after registers\n+\t * are restored from idle. It's an NMI, so interrupts need not be\n+\t * re-enabled when it's taken.\n+\t */\n+\tif (unlikely(reason == IRQ_SYSTEM_RESET)) {\n+\t\treplay_system_reset();\n+\t\treturn;\n+\t}\n \n \t/*\n \t * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0,\n-\t * so this can be called unconditionally with srr1 wake reason.\n+\t * so this can be called unconditionally with the SRR1 wake\n+\t * reason as returned by the idle code. If a future CPU was to\n+\t * designate this as an interrupt reason, then a new index for\n+\t * no interrupt must be assigned.\n \t */\n-\tlocal_paca->irq_happened |= srr1_to_lazyirq[idx];\n+\tlocal_paca->irq_happened |= reason;\n }\n #endif /* CONFIG_PPC_BOOK3S */\n \ndiff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S\nindex 8c1ede2d3f7e..37cd170201a2 100644\n--- a/arch/powerpc/platforms/powernv/opal-wrappers.S\n+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S\n@@ -307,6 +307,7 @@ OPAL_CALL(opal_xive_get_vp_info,\t\tOPAL_XIVE_GET_VP_INFO);\n OPAL_CALL(opal_xive_set_vp_info,\t\tOPAL_XIVE_SET_VP_INFO);\n OPAL_CALL(opal_xive_sync,\t\t\tOPAL_XIVE_SYNC);\n OPAL_CALL(opal_xive_dump,\t\t\tOPAL_XIVE_DUMP);\n+OPAL_CALL(opal_signal_system_reset,\t\tOPAL_SIGNAL_SYSTEM_RESET);\n OPAL_CALL(opal_npu_init_context,\t\tOPAL_NPU_INIT_CONTEXT);\n OPAL_CALL(opal_npu_destroy_context,\t\tOPAL_NPU_DESTROY_CONTEXT);\n OPAL_CALL(opal_npu_map_lpar,\t\t\tOPAL_NPU_MAP_LPAR);\ndiff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h\nindex a159d48573d7..49add2037e0d 100644\n--- a/arch/powerpc/platforms/powernv/powernv.h\n+++ b/arch/powerpc/platforms/powernv/powernv.h\n@@ -3,6 +3,7 @@\n \n #ifdef CONFIG_SMP\n extern void pnv_smp_init(void);\n+extern int pnv_system_reset_exception(struct pt_regs *regs);\n #else\n static inline void pnv_smp_init(void) { }\n #endif\ndiff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c\nindex 897aa1400eb8..4fdaa1d7c4cd 100644\n--- a/arch/powerpc/platforms/powernv/setup.c\n+++ b/arch/powerpc/platforms/powernv/setup.c\n@@ -282,6 +282,9 @@ static void __init pnv_setup_machdep_opal(void)\n \tppc_md.restart = pnv_restart;\n \tpm_power_off = pnv_power_off;\n \tppc_md.halt = pnv_halt;\n+#ifdef CONFIG_SMP\n+\tppc_md.system_reset_exception = pnv_system_reset_exception;\n+#endif\n \tppc_md.machine_check_exception = opal_machine_check;\n \tppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;\n \tppc_md.hmi_exception_early = opal_hmi_exception_early;\ndiff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c\nindex c17f81e433f7..23da03eda954 100644\n--- a/arch/powerpc/platforms/powernv/smp.c\n+++ b/arch/powerpc/platforms/powernv/smp.c\n@@ -290,6 +290,54 @@ static void __init pnv_smp_probe(void)\n \t}\n }\n \n+int pnv_system_reset_exception(struct pt_regs *regs)\n+{\n+\tif (smp_handle_nmi_ipi(regs))\n+\t\treturn 1;\n+\treturn 0;\n+}\n+\n+static int pnv_cause_nmi_ipi(int cpu)\n+{\n+\tint64_t rc;\n+\n+\tif (cpu >= 0) {\n+\t\trc = opal_signal_system_reset(get_hard_smp_processor_id(cpu));\n+\t\tif (rc != OPAL_SUCCESS)\n+\t\t\treturn 0;\n+\t\treturn 1;\n+\n+\t} else if (cpu == NMI_IPI_ALL_OTHERS) {\n+\t\tbool success = true;\n+\t\tint c;\n+\n+\n+\t\t/*\n+\t\t * We do not use broadcasts (yet), because it's not clear\n+\t\t * exactly what semantics Linux wants or the firmware should\n+\t\t * provide.\n+\t\t */\n+\t\tfor_each_online_cpu(c) {\n+\t\t\tif (c == smp_processor_id())\n+\t\t\t\tcontinue;\n+\n+\t\t\trc = opal_signal_system_reset(\n+\t\t\t\t\t\tget_hard_smp_processor_id(c));\n+\t\t\tif (rc != OPAL_SUCCESS)\n+\t\t\t\tsuccess = false;\n+\t\t}\n+\t\tif (success)\n+\t\t\treturn 1;\n+\n+\t\t/*\n+\t\t * Caller will fall back to doorbells, which may pick\n+\t\t * up the remainders.\n+\t\t */\n+\t}\n+\n+\treturn 0;\n+}\n+\n static struct smp_ops_t pnv_smp_ops = {\n \t.message_pass\t= NULL, /* Use smp_muxed_ipi_message_pass */\n \t.cause_ipi\t= NULL,\t/* Filled at runtime by pnv_smp_probe() */\n@@ -308,6 +356,8 @@ static struct smp_ops_t pnv_smp_ops = {\n /* This is called very early during platform setup_arch */\n void __init pnv_smp_init(void)\n {\n+\tif (opal_check_token(OPAL_SIGNAL_SYSTEM_RESET))\n+\t\tpnv_smp_ops.cause_nmi_ipi = pnv_cause_nmi_ipi;\n \tsmp_ops = &pnv_smp_ops;\n \n #ifdef CONFIG_HOTPLUG_CPU\n", "prefixes": [ "5/5" ] }