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GET /api/patches/814711/?format=api
{ "id": 814711, "url": "http://patchwork.ozlabs.org/api/patches/814711/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170917232010.14183-3-f4bug@amsat.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170917232010.14183-3-f4bug@amsat.org>", "list_archive_url": null, "date": "2017-09-17T23:20:06", "name": "[v3,2/6] mips: introduce internal.h and cleanup cpu.h", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "724ad46dab6eb98c1f0207e9e6eca29990f74bdf", "submitter": { "id": 70924, "url": "http://patchwork.ozlabs.org/api/people/70924/?format=api", "name": "Philippe Mathieu-Daudé", "email": "f4bug@amsat.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170917232010.14183-3-f4bug@amsat.org/mbox/", "series": [ { "id": 3548, "url": "http://patchwork.ozlabs.org/api/series/3548/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3548", "date": "2017-09-17T23:20:04", "name": "QOMify MIPS cpu", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/3548/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/814711/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/814711/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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<imammedo@redhat.com>,\n\tEduardo Habkost <ehabkost@redhat.com>, \n\tAurelien Jarno <aurelien@aurel32.net>,\n\tYongbok Kim <yongbok.kim@imgtec.com>,\n\tMarcel Apfelbaum <marcel@redhat.com>", "Date": "Sun, 17 Sep 2017 20:20:06 -0300", "Message-Id": "<20170917232010.14183-3-f4bug@amsat.org>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170917232010.14183-1-f4bug@amsat.org>", "References": "<20170917232010.14183-1-f4bug@amsat.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400d:c09::241", "Subject": "[Qemu-devel] [PATCH v3 2/6] mips: introduce internal.h and cleanup\n\tcpu.h", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Thomas Huth <thuth@redhat.com>, James Hogan <james.hogan@imgtec.com>,\n\t=?utf-8?q?Herv=C3=A9_Poussineau?= <hpoussin@reactos.org>,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>,\n\tqemu-devel@nongnu.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "no logical change, only code movement (and fix a comment typo).\n\nSigned-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nTested-by: Igor Mammedov <imammedo@redhat.com>\nTested-by: James Hogan <james.hogan@imgtec.com>\nAcked-by: Eduardo Habkost <ehabkost@redhat.com>\n---\nThis patch triggers 3 positive falses from checkpatch:\n\nERROR: space prohibited after that '&' (ctx:WxW)\n#664: FILE: target/mips/internal.h:230:\n+ if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {\n ^\n#672: FILE: target/mips/internal.h:238:\n+ ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {\n ^\n#692: FILE: target/mips/internal.h:258:\n+ env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;\n ^\ntotal: 3 errors, 0 warnings, 842 lines checked\n\nThis is a \"binary vs unary operators\" confusion.\n\n target/mips/cpu.h | 354 +--------------------------------------------\n target/mips/internal.h | 362 +++++++++++++++++++++++++++++++++++++++++++++++\n target/mips/cp0_timer.c | 1 +\n target/mips/cpu.c | 1 +\n target/mips/gdbstub.c | 1 +\n target/mips/helper.c | 1 +\n target/mips/kvm.c | 1 +\n target/mips/machine.c | 1 +\n target/mips/msa_helper.c | 1 +\n target/mips/op_helper.c | 1 +\n target/mips/translate.c | 1 +\n 11 files changed, 372 insertions(+), 353 deletions(-)\n create mode 100644 target/mips/internal.h", "diff": "diff --git a/target/mips/cpu.h b/target/mips/cpu.h\nindex 74f6a5b098..2f81e0f950 100644\n--- a/target/mips/cpu.h\n+++ b/target/mips/cpu.h\n@@ -1,8 +1,6 @@\n #ifndef MIPS_CPU_H\n #define MIPS_CPU_H\n \n-//#define DEBUG_OP\n-\n #define ALIGNED_ONLY\n \n #define CPUArchState struct CPUMIPSState\n@@ -15,56 +13,11 @@\n \n struct CPUMIPSState;\n \n-typedef struct r4k_tlb_t r4k_tlb_t;\n-struct r4k_tlb_t {\n- target_ulong VPN;\n- uint32_t PageMask;\n- uint16_t ASID;\n- unsigned int G:1;\n- unsigned int C0:3;\n- unsigned int C1:3;\n- unsigned int V0:1;\n- unsigned int V1:1;\n- unsigned int D0:1;\n- unsigned int D1:1;\n- unsigned int XI0:1;\n- unsigned int XI1:1;\n- unsigned int RI0:1;\n- unsigned int RI1:1;\n- unsigned int EHINV:1;\n- uint64_t PFN[2];\n-};\n-\n-#if !defined(CONFIG_USER_ONLY)\n typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;\n-struct CPUMIPSTLBContext {\n- uint32_t nb_tlb;\n- uint32_t tlb_in_use;\n- int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);\n- void (*helper_tlbwi)(struct CPUMIPSState *env);\n- void (*helper_tlbwr)(struct CPUMIPSState *env);\n- void (*helper_tlbp)(struct CPUMIPSState *env);\n- void (*helper_tlbr)(struct CPUMIPSState *env);\n- void (*helper_tlbinv)(struct CPUMIPSState *env);\n- void (*helper_tlbinvf)(struct CPUMIPSState *env);\n- union {\n- struct {\n- r4k_tlb_t tlb[MIPS_TLB_MAX];\n- } r4k;\n- } mmu;\n-};\n-#endif\n \n /* MSA Context */\n #define MSA_WRLEN (128)\n \n-enum CPUMIPSMSADataFormat {\n- DF_BYTE = 0,\n- DF_HALF,\n- DF_WORD,\n- DF_DOUBLE\n-};\n-\n typedef union wr_t wr_t;\n union wr_t {\n int8_t b[MSA_WRLEN/8];\n@@ -682,40 +635,6 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)\n \n #define ENV_OFFSET offsetof(MIPSCPU, env)\n \n-#ifndef CONFIG_USER_ONLY\n-extern const struct VMStateDescription vmstate_mips_cpu;\n-#endif\n-\n-void mips_cpu_do_interrupt(CPUState *cpu);\n-bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);\n-void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,\n- int flags);\n-hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n-int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);\n-int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\n-void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,\n- MMUAccessType access_type,\n- int mmu_idx, uintptr_t retaddr);\n-\n-#if !defined(CONFIG_USER_ONLY)\n-int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,\n- target_ulong address, int rw, int access_type);\n-int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,\n- target_ulong address, int rw, int access_type);\n-int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,\n- target_ulong address, int rw, int access_type);\n-void r4k_helper_tlbwi(CPUMIPSState *env);\n-void r4k_helper_tlbwr(CPUMIPSState *env);\n-void r4k_helper_tlbp(CPUMIPSState *env);\n-void r4k_helper_tlbr(CPUMIPSState *env);\n-void r4k_helper_tlbinv(CPUMIPSState *env);\n-void r4k_helper_tlbinvf(CPUMIPSState *env);\n-\n-void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,\n- bool is_write, bool is_exec, int unused,\n- unsigned size);\n-#endif\n-\n void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);\n \n #define cpu_signal_handler cpu_mips_signal_handler\n@@ -746,42 +665,6 @@ static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)\n return hflags_mmu_index(env->hflags);\n }\n \n-static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)\n-{\n- return (env->CP0_Status & (1 << CP0St_IE)) &&\n- !(env->CP0_Status & (1 << CP0St_EXL)) &&\n- !(env->CP0_Status & (1 << CP0St_ERL)) &&\n- !(env->hflags & MIPS_HFLAG_DM) &&\n- /* Note that the TCStatus IXMT field is initialized to zero,\n- and only MT capable cores can set it to one. So we don't\n- need to check for MT capabilities here. */\n- !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));\n-}\n-\n-/* Check if there is pending and not masked out interrupt */\n-static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)\n-{\n- int32_t pending;\n- int32_t status;\n- bool r;\n-\n- pending = env->CP0_Cause & CP0Ca_IP_mask;\n- status = env->CP0_Status & CP0Ca_IP_mask;\n-\n- if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {\n- /* A MIPS configured with a vectorizing external interrupt controller\n- will feed a vector into the Cause pending lines. The core treats\n- the status lines as a vector level, not as indiviual masks. */\n- r = pending > status;\n- } else {\n- /* A MIPS configured with compatibility or VInt (Vectored Interrupts)\n- treats the pending lines as individual interrupt lines, the status\n- lines are individual masks. */\n- r = (pending & status) != 0;\n- }\n- return r;\n-}\n-\n #include \"exec/cpu-all.h\"\n \n /* Memory access type :\n@@ -847,14 +730,13 @@ enum {\n #define EXCP_SC 0x100\n \n /*\n- * This is an interrnally generated WAKE request line.\n+ * This is an internally generated WAKE request line.\n * It is driven by the CPU itself. Raised when the MT\n * block wants to wake a VPE from an inactive state and\n * cleared when VPE goes from active to inactive.\n */\n #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0\n \n-void mips_tcg_init(void);\n MIPSCPU *cpu_mips_init(const char *cpu_model);\n int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);\n \n@@ -863,84 +745,18 @@ bool cpu_supports_cps_smp(const char *cpu_model);\n bool cpu_supports_isa(const char *cpu_model, unsigned int isa);\n void cpu_set_exception_base(int vp_index, target_ulong address);\n \n-/* TODO QOM'ify CPU reset and remove */\n-void cpu_state_reset(CPUMIPSState *s);\n-\n-/* mips_timer.c */\n-uint32_t cpu_mips_get_random (CPUMIPSState *env);\n-uint32_t cpu_mips_get_count (CPUMIPSState *env);\n-void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);\n-void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);\n-void cpu_mips_start_count(CPUMIPSState *env);\n-void cpu_mips_stop_count(CPUMIPSState *env);\n-\n /* mips_int.c */\n void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);\n \n /* helper.c */\n-int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,\n- int mmu_idx);\n-\n-/* op_helper.c */\n-uint32_t float_class_s(uint32_t arg, float_status *fst);\n-uint64_t float_class_d(uint64_t arg, float_status *fst);\n-\n-#if !defined(CONFIG_USER_ONLY)\n-void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);\n-hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,\n-\t\t int rw);\n-#endif\n target_ulong exception_resume_pc (CPUMIPSState *env);\n \n-/* op_helper.c */\n-extern unsigned int ieee_rm[];\n-int ieee_ex_to_mips(int xcpt);\n-\n-static inline void restore_rounding_mode(CPUMIPSState *env)\n-{\n- set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],\n- &env->active_fpu.fp_status);\n-}\n-\n-static inline void restore_flush_mode(CPUMIPSState *env)\n-{\n- set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,\n- &env->active_fpu.fp_status);\n-}\n-\n static inline void restore_snan_bit_mode(CPUMIPSState *env)\n {\n set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,\n &env->active_fpu.fp_status);\n }\n \n-static inline void restore_fp_status(CPUMIPSState *env)\n-{\n- restore_rounding_mode(env);\n- restore_flush_mode(env);\n- restore_snan_bit_mode(env);\n-}\n-\n-static inline void restore_msa_fp_status(CPUMIPSState *env)\n-{\n- float_status *status = &env->active_tc.msa_fp_status;\n- int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;\n- bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;\n-\n- set_float_rounding_mode(ieee_rm[rounding_mode], status);\n- set_flush_to_zero(flush_to_zero, status);\n- set_flush_inputs_to_zero(flush_to_zero, status);\n-}\n-\n-static inline void restore_pamask(CPUMIPSState *env)\n-{\n- if (env->hflags & MIPS_HFLAG_ELPA) {\n- env->PAMask = (1ULL << env->PABITS) - 1;\n- } else {\n- env->PAMask = PAMASK_BASE;\n- }\n-}\n-\n static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,\n target_ulong *cs_base, uint32_t *flags)\n {\n@@ -950,172 +766,4 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,\n MIPS_HFLAG_HWRENA_ULR);\n }\n \n-static inline int mips_vpe_active(CPUMIPSState *env)\n-{\n- int active = 1;\n-\n- /* Check that the VPE is enabled. */\n- if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {\n- active = 0;\n- }\n- /* Check that the VPE is activated. */\n- if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {\n- active = 0;\n- }\n-\n- /* Now verify that there are active thread contexts in the VPE.\n-\n- This assumes the CPU model will internally reschedule threads\n- if the active one goes to sleep. If there are no threads available\n- the active one will be in a sleeping state, and we can turn off\n- the entire VPE. */\n- if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {\n- /* TC is not activated. */\n- active = 0;\n- }\n- if (env->active_tc.CP0_TCHalt & 1) {\n- /* TC is in halt state. */\n- active = 0;\n- }\n-\n- return active;\n-}\n-\n-static inline int mips_vp_active(CPUMIPSState *env)\n-{\n- CPUState *other_cs = first_cpu;\n-\n- /* Check if the VP disabled other VPs (which means the VP is enabled) */\n- if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {\n- return 1;\n- }\n-\n- /* Check if the virtual processor is disabled due to a DVP */\n- CPU_FOREACH(other_cs) {\n- MIPSCPU *other_cpu = MIPS_CPU(other_cs);\n- if ((&other_cpu->env != env) &&\n- ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {\n- return 0;\n- }\n- }\n- return 1;\n-}\n-\n-static inline void compute_hflags(CPUMIPSState *env)\n-{\n- env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |\n- MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |\n- MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |\n- MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |\n- MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);\n- if (env->CP0_Status & (1 << CP0St_ERL)) {\n- env->hflags |= MIPS_HFLAG_ERL;\n- }\n- if (!(env->CP0_Status & (1 << CP0St_EXL)) &&\n- !(env->CP0_Status & (1 << CP0St_ERL)) &&\n- !(env->hflags & MIPS_HFLAG_DM)) {\n- env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;\n- }\n-#if defined(TARGET_MIPS64)\n- if ((env->insn_flags & ISA_MIPS3) &&\n- (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||\n- (env->CP0_Status & (1 << CP0St_PX)) ||\n- (env->CP0_Status & (1 << CP0St_UX)))) {\n- env->hflags |= MIPS_HFLAG_64;\n- }\n-\n- if (!(env->insn_flags & ISA_MIPS3)) {\n- env->hflags |= MIPS_HFLAG_AWRAP;\n- } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&\n- !(env->CP0_Status & (1 << CP0St_UX))) {\n- env->hflags |= MIPS_HFLAG_AWRAP;\n- } else if (env->insn_flags & ISA_MIPS64R6) {\n- /* Address wrapping for Supervisor and Kernel is specified in R6 */\n- if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&\n- !(env->CP0_Status & (1 << CP0St_SX))) ||\n- (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&\n- !(env->CP0_Status & (1 << CP0St_KX)))) {\n- env->hflags |= MIPS_HFLAG_AWRAP;\n- }\n- }\n-#endif\n- if (((env->CP0_Status & (1 << CP0St_CU0)) &&\n- !(env->insn_flags & ISA_MIPS32R6)) ||\n- !(env->hflags & MIPS_HFLAG_KSU)) {\n- env->hflags |= MIPS_HFLAG_CP0;\n- }\n- if (env->CP0_Status & (1 << CP0St_CU1)) {\n- env->hflags |= MIPS_HFLAG_FPU;\n- }\n- if (env->CP0_Status & (1 << CP0St_FR)) {\n- env->hflags |= MIPS_HFLAG_F64;\n- }\n- if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&\n- (env->CP0_Config5 & (1 << CP0C5_SBRI))) {\n- env->hflags |= MIPS_HFLAG_SBRI;\n- }\n- if (env->insn_flags & ASE_DSPR2) {\n- /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,\n- so enable to access DSPR2 resources. */\n- if (env->CP0_Status & (1 << CP0St_MX)) {\n- env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;\n- }\n-\n- } else if (env->insn_flags & ASE_DSP) {\n- /* Enables access MIPS DSP resources, now our cpu is DSP ASE,\n- so enable to access DSP resources. */\n- if (env->CP0_Status & (1 << CP0St_MX)) {\n- env->hflags |= MIPS_HFLAG_DSP;\n- }\n-\n- }\n- if (env->insn_flags & ISA_MIPS32R2) {\n- if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {\n- env->hflags |= MIPS_HFLAG_COP1X;\n- }\n- } else if (env->insn_flags & ISA_MIPS32) {\n- if (env->hflags & MIPS_HFLAG_64) {\n- env->hflags |= MIPS_HFLAG_COP1X;\n- }\n- } else if (env->insn_flags & ISA_MIPS4) {\n- /* All supported MIPS IV CPUs use the XX (CU3) to enable\n- and disable the MIPS IV extensions to the MIPS III ISA.\n- Some other MIPS IV CPUs ignore the bit, so the check here\n- would be too restrictive for them. */\n- if (env->CP0_Status & (1U << CP0St_CU3)) {\n- env->hflags |= MIPS_HFLAG_COP1X;\n- }\n- }\n- if (env->insn_flags & ASE_MSA) {\n- if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {\n- env->hflags |= MIPS_HFLAG_MSA;\n- }\n- }\n- if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {\n- if (env->CP0_Config5 & (1 << CP0C5_FRE)) {\n- env->hflags |= MIPS_HFLAG_FRE;\n- }\n- }\n- if (env->CP0_Config3 & (1 << CP0C3_LPA)) {\n- if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {\n- env->hflags |= MIPS_HFLAG_ELPA;\n- }\n- }\n-}\n-\n-void cpu_mips_tlb_flush(CPUMIPSState *env);\n-void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);\n-void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);\n-void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);\n-\n-void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,\n- int error_code, uintptr_t pc);\n-\n-static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,\n- uint32_t exception,\n- uintptr_t pc)\n-{\n- do_raise_exception_err(env, exception, 0, pc);\n-}\n-\n #endif /* MIPS_CPU_H */\ndiff --git a/target/mips/internal.h b/target/mips/internal.h\nnew file mode 100644\nindex 0000000000..91c2df4537\n--- /dev/null\n+++ b/target/mips/internal.h\n@@ -0,0 +1,362 @@\n+/* mips internal definitions and helpers\n+ *\n+ * This work is licensed under the terms of the GNU GPL, version 2 or later.\n+ * See the COPYING file in the top-level directory.\n+ */\n+\n+#ifndef MIPS_INTERNAL_H\n+#define MIPS_INTERNAL_H\n+\n+enum CPUMIPSMSADataFormat {\n+ DF_BYTE = 0,\n+ DF_HALF,\n+ DF_WORD,\n+ DF_DOUBLE\n+};\n+\n+void mips_cpu_do_interrupt(CPUState *cpu);\n+bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);\n+void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,\n+ int flags);\n+hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);\n+int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\n+void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,\n+ MMUAccessType access_type,\n+ int mmu_idx, uintptr_t retaddr);\n+\n+#if !defined(CONFIG_USER_ONLY)\n+\n+typedef struct r4k_tlb_t r4k_tlb_t;\n+struct r4k_tlb_t {\n+ target_ulong VPN;\n+ uint32_t PageMask;\n+ uint16_t ASID;\n+ unsigned int G:1;\n+ unsigned int C0:3;\n+ unsigned int C1:3;\n+ unsigned int V0:1;\n+ unsigned int V1:1;\n+ unsigned int D0:1;\n+ unsigned int D1:1;\n+ unsigned int XI0:1;\n+ unsigned int XI1:1;\n+ unsigned int RI0:1;\n+ unsigned int RI1:1;\n+ unsigned int EHINV:1;\n+ uint64_t PFN[2];\n+};\n+\n+struct CPUMIPSTLBContext {\n+ uint32_t nb_tlb;\n+ uint32_t tlb_in_use;\n+ int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,\n+ target_ulong address, int rw, int access_type);\n+ void (*helper_tlbwi)(struct CPUMIPSState *env);\n+ void (*helper_tlbwr)(struct CPUMIPSState *env);\n+ void (*helper_tlbp)(struct CPUMIPSState *env);\n+ void (*helper_tlbr)(struct CPUMIPSState *env);\n+ void (*helper_tlbinv)(struct CPUMIPSState *env);\n+ void (*helper_tlbinvf)(struct CPUMIPSState *env);\n+ union {\n+ struct {\n+ r4k_tlb_t tlb[MIPS_TLB_MAX];\n+ } r4k;\n+ } mmu;\n+};\n+\n+int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,\n+ target_ulong address, int rw, int access_type);\n+int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,\n+ target_ulong address, int rw, int access_type);\n+int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,\n+ target_ulong address, int rw, int access_type);\n+void r4k_helper_tlbwi(CPUMIPSState *env);\n+void r4k_helper_tlbwr(CPUMIPSState *env);\n+void r4k_helper_tlbp(CPUMIPSState *env);\n+void r4k_helper_tlbr(CPUMIPSState *env);\n+void r4k_helper_tlbinv(CPUMIPSState *env);\n+void r4k_helper_tlbinvf(CPUMIPSState *env);\n+void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);\n+\n+void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,\n+ bool is_write, bool is_exec, int unused,\n+ unsigned size);\n+hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,\n+ int rw);\n+#endif\n+\n+#define cpu_signal_handler cpu_mips_signal_handler\n+\n+#ifndef CONFIG_USER_ONLY\n+extern const struct VMStateDescription vmstate_mips_cpu;\n+#endif\n+\n+static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)\n+{\n+ return (env->CP0_Status & (1 << CP0St_IE)) &&\n+ !(env->CP0_Status & (1 << CP0St_EXL)) &&\n+ !(env->CP0_Status & (1 << CP0St_ERL)) &&\n+ !(env->hflags & MIPS_HFLAG_DM) &&\n+ /* Note that the TCStatus IXMT field is initialized to zero,\n+ and only MT capable cores can set it to one. So we don't\n+ need to check for MT capabilities here. */\n+ !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));\n+}\n+\n+/* Check if there is pending and not masked out interrupt */\n+static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)\n+{\n+ int32_t pending;\n+ int32_t status;\n+ bool r;\n+\n+ pending = env->CP0_Cause & CP0Ca_IP_mask;\n+ status = env->CP0_Status & CP0Ca_IP_mask;\n+\n+ if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {\n+ /* A MIPS configured with a vectorizing external interrupt controller\n+ will feed a vector into the Cause pending lines. The core treats\n+ the status lines as a vector level, not as indiviual masks. */\n+ r = pending > status;\n+ } else {\n+ /* A MIPS configured with compatibility or VInt (Vectored Interrupts)\n+ treats the pending lines as individual interrupt lines, the status\n+ lines are individual masks. */\n+ r = (pending & status) != 0;\n+ }\n+ return r;\n+}\n+\n+void mips_tcg_init(void);\n+\n+/* TODO QOM'ify CPU reset and remove */\n+void cpu_state_reset(CPUMIPSState *s);\n+\n+/* cp0_timer.c */\n+uint32_t cpu_mips_get_random(CPUMIPSState *env);\n+uint32_t cpu_mips_get_count(CPUMIPSState *env);\n+void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);\n+void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);\n+void cpu_mips_start_count(CPUMIPSState *env);\n+void cpu_mips_stop_count(CPUMIPSState *env);\n+\n+/* helper.c */\n+int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,\n+ int mmu_idx);\n+\n+/* op_helper.c */\n+uint32_t float_class_s(uint32_t arg, float_status *fst);\n+uint64_t float_class_d(uint64_t arg, float_status *fst);\n+\n+extern unsigned int ieee_rm[];\n+int ieee_ex_to_mips(int xcpt);\n+\n+static inline void restore_rounding_mode(CPUMIPSState *env)\n+{\n+ set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],\n+ &env->active_fpu.fp_status);\n+}\n+\n+static inline void restore_flush_mode(CPUMIPSState *env)\n+{\n+ set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,\n+ &env->active_fpu.fp_status);\n+}\n+\n+static inline void restore_fp_status(CPUMIPSState *env)\n+{\n+ restore_rounding_mode(env);\n+ restore_flush_mode(env);\n+ restore_snan_bit_mode(env);\n+}\n+\n+static inline void restore_msa_fp_status(CPUMIPSState *env)\n+{\n+ float_status *status = &env->active_tc.msa_fp_status;\n+ int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;\n+ bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;\n+\n+ set_float_rounding_mode(ieee_rm[rounding_mode], status);\n+ set_flush_to_zero(flush_to_zero, status);\n+ set_flush_inputs_to_zero(flush_to_zero, status);\n+}\n+\n+static inline void restore_pamask(CPUMIPSState *env)\n+{\n+ if (env->hflags & MIPS_HFLAG_ELPA) {\n+ env->PAMask = (1ULL << env->PABITS) - 1;\n+ } else {\n+ env->PAMask = PAMASK_BASE;\n+ }\n+}\n+\n+static inline int mips_vpe_active(CPUMIPSState *env)\n+{\n+ int active = 1;\n+\n+ /* Check that the VPE is enabled. */\n+ if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {\n+ active = 0;\n+ }\n+ /* Check that the VPE is activated. */\n+ if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {\n+ active = 0;\n+ }\n+\n+ /* Now verify that there are active thread contexts in the VPE.\n+\n+ This assumes the CPU model will internally reschedule threads\n+ if the active one goes to sleep. If there are no threads available\n+ the active one will be in a sleeping state, and we can turn off\n+ the entire VPE. */\n+ if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {\n+ /* TC is not activated. */\n+ active = 0;\n+ }\n+ if (env->active_tc.CP0_TCHalt & 1) {\n+ /* TC is in halt state. */\n+ active = 0;\n+ }\n+\n+ return active;\n+}\n+\n+static inline int mips_vp_active(CPUMIPSState *env)\n+{\n+ CPUState *other_cs = first_cpu;\n+\n+ /* Check if the VP disabled other VPs (which means the VP is enabled) */\n+ if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {\n+ return 1;\n+ }\n+\n+ /* Check if the virtual processor is disabled due to a DVP */\n+ CPU_FOREACH(other_cs) {\n+ MIPSCPU *other_cpu = MIPS_CPU(other_cs);\n+ if ((&other_cpu->env != env) &&\n+ ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {\n+ return 0;\n+ }\n+ }\n+ return 1;\n+}\n+\n+static inline void compute_hflags(CPUMIPSState *env)\n+{\n+ env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |\n+ MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |\n+ MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |\n+ MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |\n+ MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);\n+ if (env->CP0_Status & (1 << CP0St_ERL)) {\n+ env->hflags |= MIPS_HFLAG_ERL;\n+ }\n+ if (!(env->CP0_Status & (1 << CP0St_EXL)) &&\n+ !(env->CP0_Status & (1 << CP0St_ERL)) &&\n+ !(env->hflags & MIPS_HFLAG_DM)) {\n+ env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;\n+ }\n+#if defined(TARGET_MIPS64)\n+ if ((env->insn_flags & ISA_MIPS3) &&\n+ (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||\n+ (env->CP0_Status & (1 << CP0St_PX)) ||\n+ (env->CP0_Status & (1 << CP0St_UX)))) {\n+ env->hflags |= MIPS_HFLAG_64;\n+ }\n+\n+ if (!(env->insn_flags & ISA_MIPS3)) {\n+ env->hflags |= MIPS_HFLAG_AWRAP;\n+ } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&\n+ !(env->CP0_Status & (1 << CP0St_UX))) {\n+ env->hflags |= MIPS_HFLAG_AWRAP;\n+ } else if (env->insn_flags & ISA_MIPS64R6) {\n+ /* Address wrapping for Supervisor and Kernel is specified in R6 */\n+ if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&\n+ !(env->CP0_Status & (1 << CP0St_SX))) ||\n+ (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&\n+ !(env->CP0_Status & (1 << CP0St_KX)))) {\n+ env->hflags |= MIPS_HFLAG_AWRAP;\n+ }\n+ }\n+#endif\n+ if (((env->CP0_Status & (1 << CP0St_CU0)) &&\n+ !(env->insn_flags & ISA_MIPS32R6)) ||\n+ !(env->hflags & MIPS_HFLAG_KSU)) {\n+ env->hflags |= MIPS_HFLAG_CP0;\n+ }\n+ if (env->CP0_Status & (1 << CP0St_CU1)) {\n+ env->hflags |= MIPS_HFLAG_FPU;\n+ }\n+ if (env->CP0_Status & (1 << CP0St_FR)) {\n+ env->hflags |= MIPS_HFLAG_F64;\n+ }\n+ if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&\n+ (env->CP0_Config5 & (1 << CP0C5_SBRI))) {\n+ env->hflags |= MIPS_HFLAG_SBRI;\n+ }\n+ if (env->insn_flags & ASE_DSPR2) {\n+ /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,\n+ so enable to access DSPR2 resources. */\n+ if (env->CP0_Status & (1 << CP0St_MX)) {\n+ env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;\n+ }\n+\n+ } else if (env->insn_flags & ASE_DSP) {\n+ /* Enables access MIPS DSP resources, now our cpu is DSP ASE,\n+ so enable to access DSP resources. */\n+ if (env->CP0_Status & (1 << CP0St_MX)) {\n+ env->hflags |= MIPS_HFLAG_DSP;\n+ }\n+\n+ }\n+ if (env->insn_flags & ISA_MIPS32R2) {\n+ if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {\n+ env->hflags |= MIPS_HFLAG_COP1X;\n+ }\n+ } else if (env->insn_flags & ISA_MIPS32) {\n+ if (env->hflags & MIPS_HFLAG_64) {\n+ env->hflags |= MIPS_HFLAG_COP1X;\n+ }\n+ } else if (env->insn_flags & ISA_MIPS4) {\n+ /* All supported MIPS IV CPUs use the XX (CU3) to enable\n+ and disable the MIPS IV extensions to the MIPS III ISA.\n+ Some other MIPS IV CPUs ignore the bit, so the check here\n+ would be too restrictive for them. */\n+ if (env->CP0_Status & (1U << CP0St_CU3)) {\n+ env->hflags |= MIPS_HFLAG_COP1X;\n+ }\n+ }\n+ if (env->insn_flags & ASE_MSA) {\n+ if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {\n+ env->hflags |= MIPS_HFLAG_MSA;\n+ }\n+ }\n+ if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {\n+ if (env->CP0_Config5 & (1 << CP0C5_FRE)) {\n+ env->hflags |= MIPS_HFLAG_FRE;\n+ }\n+ }\n+ if (env->CP0_Config3 & (1 << CP0C3_LPA)) {\n+ if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {\n+ env->hflags |= MIPS_HFLAG_ELPA;\n+ }\n+ }\n+}\n+\n+void cpu_mips_tlb_flush(CPUMIPSState *env);\n+void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);\n+void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);\n+void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);\n+\n+void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,\n+ int error_code, uintptr_t pc);\n+\n+static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,\n+ uint32_t exception,\n+ uintptr_t pc)\n+{\n+ do_raise_exception_err(env, exception, 0, pc);\n+}\n+\n+#endif\ndiff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c\nindex a9a58c5604..f4716395df 100644\n--- a/target/mips/cp0_timer.c\n+++ b/target/mips/cp0_timer.c\n@@ -24,6 +24,7 @@\n #include \"hw/mips/cpudevs.h\"\n #include \"qemu/timer.h\"\n #include \"sysemu/kvm.h\"\n+#include \"internal.h\"\n \n #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */\n \ndiff --git a/target/mips/cpu.c b/target/mips/cpu.c\nindex 1bb66b7a5a..68bf423e9d 100644\n--- a/target/mips/cpu.c\n+++ b/target/mips/cpu.c\n@@ -21,6 +21,7 @@\n #include \"qemu/osdep.h\"\n #include \"qapi/error.h\"\n #include \"cpu.h\"\n+#include \"internal.h\"\n #include \"kvm_mips.h\"\n #include \"qemu-common.h\"\n #include \"sysemu/kvm.h\"\ndiff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c\nindex 7c682289c2..6d1fb70f2c 100644\n--- a/target/mips/gdbstub.c\n+++ b/target/mips/gdbstub.c\n@@ -20,6 +20,7 @@\n #include \"qemu/osdep.h\"\n #include \"qemu-common.h\"\n #include \"cpu.h\"\n+#include \"internal.h\"\n #include \"exec/gdbstub.h\"\n \n int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)\ndiff --git a/target/mips/helper.c b/target/mips/helper.c\nindex ca39aca08a..ea076261af 100644\n--- a/target/mips/helper.c\n+++ b/target/mips/helper.c\n@@ -19,6 +19,7 @@\n #include \"qemu/osdep.h\"\n \n #include \"cpu.h\"\n+#include \"internal.h\"\n #include \"exec/exec-all.h\"\n #include \"exec/cpu_ldst.h\"\n #include \"exec/log.h\"\ndiff --git a/target/mips/kvm.c b/target/mips/kvm.c\nindex 3317905e71..e604aa8b12 100644\n--- a/target/mips/kvm.c\n+++ b/target/mips/kvm.c\n@@ -16,6 +16,7 @@\n \n #include \"qemu-common.h\"\n #include \"cpu.h\"\n+#include \"internal.h\"\n #include \"qemu/error-report.h\"\n #include \"qemu/timer.h\"\n #include \"sysemu/sysemu.h\"\ndiff --git a/target/mips/machine.c b/target/mips/machine.c\nindex 898825de3b..20100d5adb 100644\n--- a/target/mips/machine.c\n+++ b/target/mips/machine.c\n@@ -1,6 +1,7 @@\n #include \"qemu/osdep.h\"\n #include \"qemu-common.h\"\n #include \"cpu.h\"\n+#include \"internal.h\"\n #include \"hw/hw.h\"\n #include \"migration/cpu.h\"\n \ndiff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c\nindex 1fdb0d9792..f167a42655 100644\n--- a/target/mips/msa_helper.c\n+++ b/target/mips/msa_helper.c\n@@ -19,6 +19,7 @@\n \n #include \"qemu/osdep.h\"\n #include \"cpu.h\"\n+#include \"internal.h\"\n #include \"exec/exec-all.h\"\n #include \"exec/helper-proto.h\"\n \ndiff --git a/target/mips/op_helper.c b/target/mips/op_helper.c\nindex 320f2b0dc4..e537a8bfd8 100644\n--- a/target/mips/op_helper.c\n+++ b/target/mips/op_helper.c\n@@ -19,6 +19,7 @@\n #include \"qemu/osdep.h\"\n #include \"qemu/main-loop.h\"\n #include \"cpu.h\"\n+#include \"internal.h\"\n #include \"qemu/host-utils.h\"\n #include \"exec/helper-proto.h\"\n #include \"exec/exec-all.h\"\ndiff --git a/target/mips/translate.c b/target/mips/translate.c\nindex c78d27294c..f0febaf1b2 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -23,6 +23,7 @@\n \n #include \"qemu/osdep.h\"\n #include \"cpu.h\"\n+#include \"internal.h\"\n #include \"disas/disas.h\"\n #include \"exec/exec-all.h\"\n #include \"tcg-op.h\"\n", "prefixes": [ "v3", "2/6" ] }