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GET /api/patches/814484/?format=api
{ "id": 814484, "url": "http://patchwork.ozlabs.org/api/patches/814484/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/CAEUhbmV-_dyW885A3yJvyEokLBgT+KcCasZh8j1NLvTpy7rRmQ@mail.gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<CAEUhbmV-_dyW885A3yJvyEokLBgT+KcCasZh8j1NLvTpy7rRmQ@mail.gmail.com>", "list_archive_url": null, "date": "2017-09-16T09:54:47", "name": "[U-Boot] Please pull u-boot-x86", "commit_ref": null, "pull_url": "git://git.denx.de/u-boot-x86.git", "state": "accepted", "archived": false, "hash": null, "submitter": { "id": 64981, "url": "http://patchwork.ozlabs.org/api/people/64981/?format=api", "name": "Bin Meng", "email": "bmeng.cn@gmail.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/CAEUhbmV-_dyW885A3yJvyEokLBgT+KcCasZh8j1NLvTpy7rRmQ@mail.gmail.com/mbox/", "series": [ { "id": 3427, "url": "http://patchwork.ozlabs.org/api/series/3427/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3427", "date": "2017-09-16T09:54:47", "name": "[U-Boot] Please pull u-boot-x86", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3427/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/814484/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/814484/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", 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(mail-wm0-f66.google.com\n\t[74.125.82.66])\n\tby lists.denx.de (Postfix) with ESMTPS id E8B13C21C2F\n\tfor <u-boot@lists.denx.de>; Sat, 16 Sep 2017 09:54:48 +0000 (UTC)", "by mail-wm0-f66.google.com with SMTP id e64so4669893wmi.2\n\tfor <u-boot@lists.denx.de>; Sat, 16 Sep 2017 02:54:48 -0700 (PDT)", "by 10.223.145.3 with HTTP; Sat, 16 Sep 2017 02:54:47 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:from:date:message-id:subject:to:cc;\n\tbh=QMjOWehICSRTUq52H1rxVeWg9L0+EYW6LDcwNpyRlfo=;\n\tb=nnBHrtPEyxkhuQn2ZrlYKn+YeCn0507Ob6ua4H6bDMWRaRuzTAZa0cxrKw0qNVenXV\n\t6F1rt6/ISwYrYpoFHjZ+ynLivCS5KiBgYGnNXVLBpnSQ80vPFiyNEsYmNl1W935mYjor\n\t1i5DWiKt2IcWKYTpqq5N6cYEUOSKWkWXw1DE5PDJTimvqJhd55CY77yx7I/uqtGl2LTh\n\tj59GC5h3QbITmtJsmICsM+SRdzyPTnO0wha5RGJQwEBOe4rhmI6fKHcmRHLcngdkrvM+\n\tI6sBHD0ksnhehOzm8dd+re/FF36Z9R1xm5eZhm6tfjKlH9tcqJ7AU6aTvgQfTttf71Y4\n\t9JFQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; \n\tbh=QMjOWehICSRTUq52H1rxVeWg9L0+EYW6LDcwNpyRlfo=;\n\tb=YzeyUadbNzncnZTovn/eAJRZcWeh9d9EsIRAN1SH1kpbK+m/172uVtvSpPqi216afW\n\t3Phq+sbvFAc//FcTteXefl9dDRBHBePR5QmaEcUKo6sEXC6Cf5yb5Y3QEDe953il19KG\n\t9FsjYGP7zv7PM4AD2We/xPKX1Pz5peKpVJACZCLOVuFKg5cYL4OOyTWo5ihmHQUFofz/\n\t0t6/7akH6GYdYbT+OgZMDk6cJqxxkBAKK76rkFcojM0vVd9/1BD1FBeCy8XVnSkAEyCR\n\tV3UdznqCtMNLvj0x7ZXWd9BnZplq+EUJ+qddXRWB7eXN+7NQ7ahAWE2zIdL3PvHveBb7\n\tTqHw==", "X-Gm-Message-State": "AHPjjUjjaFN/SfWe1LD97iEogaLpf58ljR12oJAtvlFEKCwYUPVfp9dr\n\tqYc3l1ZipxRFnGuKS5dSQXF66rcJjticJk9hPkk=", "X-Google-Smtp-Source": "AOwi7QBaLgLlaxZ8bB2jGChOkYTRg8iokI8F1W11+QErAXxpWZLNs5uVjpPROouNzMkSfrkW3LYlPSPnzaPJmaSNNyU=", "X-Received": "by 10.28.218.141 with SMTP id r135mr5260177wmg.63.1505555688395; \n\tSat, 16 Sep 2017 02:54:48 -0700 (PDT)", "MIME-Version": "1.0", "From": "Bin Meng <bmeng.cn@gmail.com>", "Date": "Sat, 16 Sep 2017 17:54:47 +0800", "Message-ID": "<CAEUhbmV-_dyW885A3yJvyEokLBgT+KcCasZh8j1NLvTpy7rRmQ@mail.gmail.com>", "To": "Tom Rini <trini@konsulko.com>, U-Boot Mailing List <u-boot@lists.denx.de>", "Subject": "[U-Boot] Please pull u-boot-x86", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Hi Tom,\n\nThe following changes since commit 079c92b0a77b9a9bf237a9430ed16cf81d43ce5d:\n\n ARM: davinci: Remove CONFIG_SOC_DA830 (2017-09-15 12:35:48 -0400)\n\nare available in the git repository at:\n\n git://git.denx.de/u-boot-x86.git\n\nfor you to fetch changes up to 8a1c44271c55961fb70fb6177f9c02fdb05287c5:\n\n x86: ivybridge: remove unused variables (2017-09-16 14:57:44 +0800)\n\n----------------------------------------------------------------\nBin Meng (13):\n x86: tsc: Add Airmont reference clock values\n x86: fsp: Update struct common_buf for FSP spec 1.1\n x86: fsp: Add FSP_GRAPHICS_INFO_HOB\n x86: Add Video BIOS Table (VBT) related Kconfig options\n tools: binman: Add a new entry type for Intel VBT\n x86: dts: Include Intel Video BIOS Table in the ROM image\n x86: dm: video: Add a framebuffer driver that utilizes VBT\n x86: fsp: Update fsp command to show spec 1.1 header\n x86: Add Intel Braswell SoC support\n x86: braswell: Add microcode for B0/C0/D0 stepping SoC\n x86: braswell: Add FSP configuration\n x86: braswell: Disable PUNIT power configuration for B0 stepping\n x86: Support Intel Cherry Hill board\n\nHeinrich Schuchardt (1):\n x86: ivybridge: remove unused variables\n\nSimon Glass (5):\n board_f: Drop the timer after relocation\n dm: x86: Allow TSC timer to be used before DM is ready\n bootstage: Drop unused options\n bootstage: Provide a separate record count setting for SPL\n x86: Enable early timer for chromebook_link\n\n arch/x86/Kconfig | 43 ++\n arch/x86/cpu/Makefile | 1 +\n arch/x86/cpu/braswell/Kconfig | 39 +\n arch/x86/cpu/braswell/Makefile | 7 +\n arch/x86/cpu/braswell/braswell.c | 36 +\n arch/x86/cpu/braswell/cpu.c | 170 +++++\n arch/x86/cpu/braswell/early_uart.c | 82 +++\n arch/x86/cpu/braswell/fsp_configs.c | 164 +++++\n arch/x86/cpu/ivybridge/northbridge.c | 10 -\n arch/x86/dts/Makefile | 1 +\n arch/x86/dts/cherryhill.dts | 215 ++++++\n arch/x86/dts/microcode/m01406c2220.dtsi | 4308\n+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n arch/x86/dts/microcode/m01406c3363.dtsi | 4308\n+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n arch/x86/dts/microcode/m01406c440a.dtsi | 4308\n+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n arch/x86/dts/u-boot.dtsi | 6 +\n arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h | 89 +++\n arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h | 172 +++++\n arch/x86/include/asm/arch-braswell/gpio.h | 217 ++++++\n arch/x86/include/asm/arch-braswell/iomap.h | 50 ++\n arch/x86/include/asm/fsp/fsp_api.h | 3 +-\n arch/x86/include/asm/fsp/fsp_hob.h | 34 +\n arch/x86/include/asm/fsp/fsp_infoheader.h | 9 +-\n arch/x86/include/asm/fsp/fsp_support.h | 12 +\n arch/x86/include/asm/global_data.h | 1 +\n arch/x86/lib/fsp/Makefile | 1 +\n arch/x86/lib/fsp/cmd_fsp.c | 24 +-\n arch/x86/lib/fsp/fsp_graphics.c | 124 ++++\n arch/x86/lib/fsp/fsp_support.c | 7 +\n board/intel/Kconfig | 10 +\n board/intel/cherryhill/Kconfig | 25 +\n board/intel/cherryhill/MAINTAINERS | 6 +\n board/intel/cherryhill/Makefile | 7 +\n board/intel/cherryhill/cherryhill.c | 596 +++++++++++++++\n board/intel/cherryhill/start.S | 9 +\n common/Kconfig | 16 +-\n common/board_f.c | 3 +\n common/bootstage.c | 6 +-\n configs/cherryhill_defconfig | 36 +\n configs/chromebook_link64_defconfig | 1 +\n configs/chromebook_link_defconfig | 1 +\n configs/sandbox_defconfig | 1 -\n configs/sandbox_flattree_defconfig | 1 -\n configs/sandbox_noblk_defconfig | 1 -\n configs/sandbox_spl_defconfig | 1 -\n doc/README.x86 | 30 +\n drivers/timer/tsc_timer.c | 47 +-\n include/bootstage.h | 6 -\n include/configs/cherryhill.h | 22 +\n tools/binman/etype/intel_vbt.py | 14 +\n tools/binman/func_test.py | 9 +-\n tools/binman/test/46_intel-vbt.dts | 14 +\n 51 files changed, 15254 insertions(+), 49 deletions(-)\n create mode 100644 arch/x86/cpu/braswell/Kconfig\n create mode 100644 arch/x86/cpu/braswell/Makefile\n create mode 100644 arch/x86/cpu/braswell/braswell.c\n create mode 100644 arch/x86/cpu/braswell/cpu.c\n create mode 100644 arch/x86/cpu/braswell/early_uart.c\n create mode 100644 arch/x86/cpu/braswell/fsp_configs.c\n create mode 100644 arch/x86/dts/cherryhill.dts\n create mode 100644 arch/x86/dts/microcode/m01406c2220.dtsi\n create mode 100644 arch/x86/dts/microcode/m01406c3363.dtsi\n create mode 100644 arch/x86/dts/microcode/m01406c440a.dtsi\n create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h\n create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h\n create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h\n create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h\n create mode 100644 arch/x86/lib/fsp/fsp_graphics.c\n create mode 100644 board/intel/cherryhill/Kconfig\n create mode 100644 board/intel/cherryhill/MAINTAINERS\n create mode 100644 board/intel/cherryhill/Makefile\n create mode 100644 board/intel/cherryhill/cherryhill.c\n create mode 100644 board/intel/cherryhill/start.S\n create mode 100644 configs/cherryhill_defconfig\n create mode 100644 include/configs/cherryhill.h\n create mode 100644 tools/binman/etype/intel_vbt.py\n create mode 100644 tools/binman/test/46_intel-vbt.dts\n\nRegards,\nBin", "diff": null, "prefixes": [ "U-Boot" ] }