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GET /api/patches/814451/?format=api
{ "id": 814451, "url": "http://patchwork.ozlabs.org/api/patches/814451/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1505524870-4783-7-git-send-email-linuxram@us.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1505524870-4783-7-git-send-email-linuxram@us.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1505524870-4783-7-git-send-email-linuxram@us.ibm.com/", "date": "2017-09-16T01:21:10", "name": "[6/6] Documentation/vm: PowerPC specific updates to memory protection keys", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "47070c49dcb546972679225f8128252a82a150f6", "submitter": { "id": 2667, "url": "http://patchwork.ozlabs.org/api/people/2667/?format=api", "name": "Ram Pai", "email": "linuxram@us.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1505524870-4783-7-git-send-email-linuxram@us.ibm.com/mbox/", "series": [ { "id": 3406, "url": "http://patchwork.ozlabs.org/api/series/3406/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=3406", "date": "2017-09-16T01:21:04", "name": "mm, x86, powerpc: Memory Protection Keys enhancement", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3406/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/814451/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/814451/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xvFFG2rCMz9t2c\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 16 Sep 2017 11:34:58 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xvFFG1XCGzDqZC\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 16 Sep 2017 11:34:58 +1000 (AEST)", "from mail-qk0-x244.google.com (mail-qk0-x244.google.com\n\t[IPv6:2607:f8b0:400d:c09::244])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xvDy42FVLzDrht\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 16 Sep 2017 11:21:48 +1000 (AEST)", "by mail-qk0-x244.google.com with SMTP id c69so2422985qke.5\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 15 Sep 2017 18:21:48 -0700 (PDT)", "from localhost.localdomain (50-39-103-96.bvtn.or.frontiernet.net.\n\t[50.39.103.96]) by smtp.gmail.com with ESMTPSA id\n\tv11sm1493189qkl.45.2017.09.15.18.21.43\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 15 Sep 2017 18:21:45 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"iOiArWLo\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"iOiArWLo\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400d:c09::244; helo=mail-qk0-x244.google.com;\n\tenvelope-from=ram.n.pai@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"iOiArWLo\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=BVQjOGrczUre6jOSsVtTFW00iGnrZjICnBM75YCS1RI=;\n\tb=iOiArWLo/Qdmd3zRNXhlCtSNRAGBHjMPz1M9WxKfZjvAxxvVew0fW1Es0KYeKXJ5nS\n\twdwj/l+ftI9xk9IM0nXAhYyTbzVQedBzv5w9AOk4/kgfKrLY9UPeFWPcuPbILvzmyMTS\n\t84NXSpiYhmuoymufCsbEbzzbmJrTMvyQDj5hYa4GSEeaS0LZ/YxOH/zGHfJE0lnY9Ygh\n\tliXndOSv6IkO48hIhXG5lJrzfUksO7lZK5Saf7t6kY4hYmf0vflneE12fzxD4ZLU2DW8\n\tvqCqaQmUAGe03QaRjM7dS5Wn2/gTgaD8IFMPJ8K4i/pZCfAqVcriq8TyI3No8DbVF25n\n\tjpfA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references;\n\tbh=BVQjOGrczUre6jOSsVtTFW00iGnrZjICnBM75YCS1RI=;\n\tb=o6Hofh1pSmuL8h82c62zFLrHH41IIlVPZDUsdCZEv+ZYY26HEXDKq6e1VAvaLJnloU\n\t8e/e4sHsZdo09esbeJUbn6rA/csPpGqileS0ox0xc2DbZbE41Xao6DY0e482SsmEmRjb\n\t2SXPnABtk+rliCvZvkfvOaCNUqhJU/dwVtEG64LVk1KDHz4mZyoOrtjSPNsDmJjY9AFo\n\tBj6crX+CFnOjrvkW9hWV855JH5ob1ZwMT4WyvkF8bELtKeVI36CkzoBMIAn1/bzMY/SZ\n\t1n+se2ZwyQPQLWup27SiqBBkjZfs8ltCdquKWhb9+4uQk+d431QAntzdc371zLigb/XN\n\t18pw==", "X-Gm-Message-State": "AHPjjUgfRmDr3Wk120Itz1tdj8tEXcvt+OAoOmHS6M/vypIB6Js2gtgG\n\tjPizy15r5wgcBQ==", "X-Google-Smtp-Source": "AOwi7QAcQh8s2G8fq2XnPHHLVG91OhrQDzFvWEUakSqm+h31VPeTeYXm6XSj0xRvXmky/7m8lWa16w==", "X-Received": "by 10.55.135.197 with SMTP id\n\tj188mr10331280qkd.277.1505524906272; \n\tFri, 15 Sep 2017 18:21:46 -0700 (PDT)", "From": "Ram Pai <linuxram@us.ibm.com>", "To": "mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org,\n\tlinux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,\n\tlinux-mm@kvack.org, x86@kernel.org, linux-doc@vger.kernel.org", "Subject": "[PATCH 6/6] Documentation/vm: PowerPC specific updates to memory\n\tprotection keys", "Date": "Fri, 15 Sep 2017 18:21:10 -0700", "Message-Id": "<1505524870-4783-7-git-send-email-linuxram@us.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1505524870-4783-1-git-send-email-linuxram@us.ibm.com>", "References": "<1505524870-4783-1-git-send-email-linuxram@us.ibm.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "ebiederm@xmission.com, arnd@arndb.de, corbet@lwn.net, linuxram@us.ibm.com,\n\tmhocko@kernel.org, mingo@redhat.com, paulus@samba.org,\n\taneesh.kumar@linux.vnet.ibm.com, bauerman@linux.vnet.ibm.com,\n\takpm@linux-foundation.org, khandual@linux.vnet.ibm.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Add documentation updates that capture PowerPC specific changes.\n\nSigned-off-by: Thiago Jung Bauermann <bauerman@linux.vnet.ibm.com>\nSigned-off-by: Ram Pai <linuxram@us.ibm.com>\n---\n Documentation/vm/protection-keys.txt | 125 +++++++++++++++++++++++++++-------\n 1 files changed, 100 insertions(+), 25 deletions(-)", "diff": "diff --git a/Documentation/vm/protection-keys.txt b/Documentation/vm/protection-keys.txt\nindex b643045..ef5f73b 100644\n--- a/Documentation/vm/protection-keys.txt\n+++ b/Documentation/vm/protection-keys.txt\n@@ -1,22 +1,45 @@\n-Memory Protection Keys for Userspace (PKU aka PKEYs) is a CPU feature\n-which will be found on future Intel CPUs.\n-\n-Memory Protection Keys provides a mechanism for enforcing page-based\n-protections, but without requiring modification of the page tables\n-when an application changes protection domains. It works by\n-dedicating 4 previously ignored bits in each page table entry to a\n-\"protection key\", giving 16 possible keys.\n-\n-There is also a new user-accessible register (PKRU) with two separate\n-bits (Access Disable and Write Disable) for each key. Being a CPU\n-register, PKRU is inherently thread-local, potentially giving each\n-thread a different set of protections from every other thread.\n-\n-There are two new instructions (RDPKRU/WRPKRU) for reading and writing\n-to the new register. The feature is only available in 64-bit mode,\n-even though there is theoretically space in the PAE PTEs. These\n-permissions are enforced on data access only and have no effect on\n-instruction fetches.\n+Memory Protection Keys for Userspace (PKU aka PKEYs) is a CPU feature found on\n+future Intel CPUs and on PowerPC 5 and higher CPUs.\n+\n+Memory Protection Keys provide a mechanism for enforcing page-based\n+protections, but without requiring modification of the page tables when an\n+application changes protection domains.\n+\n+It works by dedicating bits in each page table entry to a \"protection key\".\n+There is also a user-accessible register with two separate bits for each\n+key. Being a CPU register, the user-accessible register is inherently\n+thread-local, potentially giving each thread a different set of protections\n+from every other thread.\n+\n+On Intel:\n+\n+\tFour previously bits are used the page table entry giving 16 possible keys.\n+\n+\tThe user accessible register(PKRU) has a bit each per key to disable\n+\taccess and to disable write.\n+\n+\tThe feature is only available in 64-bit mode, even though there is\n+\ttheoretically space in the PAE PTEs. These permissions are enforced on\n+\tdata access only and have no effect on instruction fetches.\n+\n+On PowerPC:\n+\n+\tFive bits in the page table entry are used giving 32 possible keys.\n+\tThis support is currently for Hash Page Table mode only.\n+\n+\tThe user accessible register(AMR) has a bit each per key to disable\n+\tread and write. Access disable can be achieved by disabling\n+\tread and write.\n+\n+\t'mtspr 0xd, mem' reads the AMR register\n+\t'mfspr mem, 0xd' writes into the AMR register.\n+\n+\tExecution can be disabled by allocating a key with execute-disabled\n+\tpermission. The execute-permissions on the key; however, cannot be\n+\tchanged through a user accessible register. The CPU will not allow\n+\texecution of instruction in pages that are associated with\n+\texecute-disabled key.\n+\n \n =========================== Syscalls ===========================\n \n@@ -28,9 +51,9 @@ There are 3 system calls which directly interact with pkeys:\n \t\t\t unsigned long prot, int pkey);\n \n Before a pkey can be used, it must first be allocated with\n-pkey_alloc(). An application calls the WRPKRU instruction\n+pkey_alloc(). An application calls the WRPKRU/AMR instruction\n directly in order to change access permissions to memory covered\n-with a key. In this example WRPKRU is wrapped by a C function\n+with a key. In this example WRPKRU/AMR is wrapped by a C function\n called pkey_set().\n \n \tint real_prot = PROT_READ|PROT_WRITE;\n@@ -52,11 +75,11 @@ is no longer in use:\n \tmunmap(ptr, PAGE_SIZE);\n \tpkey_free(pkey);\n \n-(Note: pkey_set() is a wrapper for the RDPKRU and WRPKRU instructions.\n+(Note: pkey_set() is a wrapper for the RDPKRU,WRPKRU or AMR instructions.\n An example implementation can be found in\n- tools/testing/selftests/x86/protection_keys.c)\n+ tools/testing/selftests/vm/protection_keys.c)\n \n-=========================== Behavior ===========================\n+=========================== Behavior =================================\n \n The kernel attempts to make protection keys consistent with the\n behavior of a plain mprotect(). For instance if you do this:\n@@ -66,7 +89,7 @@ behavior of a plain mprotect(). For instance if you do this:\n \n you can expect the same effects with protection keys when doing this:\n \n-\tpkey = pkey_alloc(0, PKEY_DISABLE_WRITE | PKEY_DISABLE_READ);\n+\tpkey = pkey_alloc(0, PKEY_DISABLE_ACCESS);\n \tpkey_mprotect(ptr, size, PROT_READ|PROT_WRITE, pkey);\n \tsomething(ptr);\n \n@@ -83,3 +106,55 @@ with a read():\n The kernel will send a SIGSEGV in both cases, but si_code will be set\n to SEGV_PKERR when violating protection keys versus SEGV_ACCERR when\n the plain mprotect() permissions are violated.\n+\n+========================== sysfs Interface ==========================\n+\n+Information about support of protection keys on the system can be\n+found in the /sys/kernel/mm/protection_keys directory, which\n+contains the following files:\n+\n+- total_keys: Shows the number of keys supported by the hardware.\n+ Not all of those keys may be available for use by a process\n+ because the platform or operating system may reserve some keys\n+ for their own use.\n+\n+- usable_keys: Shows the minimum number of keys guaranteed to be\n+ available for use by a process. In other words: total_keys minus\n+ the keys reserved by the platform or operating system. This\n+ number doesn't change to reflect keys that are already being\n+ used by the process reading the file.\n+\n+ There may be one more key available than what is advertised in\n+ this file because the kernel may use one key for mprotect()\n+ calls setting up memory with execute-only permissions. This file\n+ assumes that this key is being used, but if it is not the\n+ process will have one more key it can use for other purposes.\n+\n+- disable_access_supported: Tells whether the system supports keys\n+ which disallow reading from a given page (i.e., the\n+ PKEY_DISABLE_ACCESS flag is supported).\n+\n+- disable_write_supported: Tells whether the system supports keys\n+ which disallow writing to a given page (i.e., the\n+ PKEY_DISABLE_WRITE flag is supported).\n+\n+- disable_execute_supported: Tells whether the system supports keys\n+ which disallow code execution from a given page (i.e., the\n+ PKEY_DISABLE_EXECUTE flag is supported).\n+\n+====================================================================\n+\t\tSemantic differences\n+\n+The following semantic differences exist between x86 and power.\n+\n+a) powerpc (PowerPC8 onwards) *also* allows creation of a key with\n+ execute-disabled.\n+\tThe following is allowed\n+\tpkey = pkey_alloc(0, PKEY_DISABLE_EXECUTE);\n+\n+b) changes to the key permission bits from a signal handler do not\n+ persist on x86. The PKRU specific fpregs entry need to be\n+ modified for it to persist. On powerpc the key permission can\n+ be modified by programming the AMR register from the signal\n+ handler. The changes persist across signal boundaries.\n+=====================================================================\n", "prefixes": [ "6/6" ] }