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GET /api/patches/814337/?format=api
{ "id": 814337, "url": "http://patchwork.ozlabs.org/api/patches/814337/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505494753-10837-4-git-send-email-sundeep.lkml@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505494753-10837-4-git-send-email-sundeep.lkml@gmail.com>", "list_archive_url": null, "date": "2017-09-15T16:59:11", "name": "[Qemu,devel,v9,3/5] msf2: Add Smartfusion2 SPI controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f10badcc578fe9b06f7e876e35eb2249b94faeb7", "submitter": { "id": 64324, "url": "http://patchwork.ozlabs.org/api/people/64324/?format=api", "name": "sundeep subbaraya", "email": "sundeep.lkml@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505494753-10837-4-git-send-email-sundeep.lkml@gmail.com/mbox/", "series": [ { "id": 3336, "url": "http://patchwork.ozlabs.org/api/series/3336/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3336", "date": "2017-09-15T16:59:10", "name": "Add support for Smartfusion2 SoC", "version": 9, "mbox": "http://patchwork.ozlabs.org/series/3336/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/814337/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/814337/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"ra16pPeW\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xv1xf5w8wz9s7m\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 16 Sep 2017 03:05:42 +1000 (AEST)", "from localhost ([::1]:54313 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dsu3g-0002M7-Vs\n\tfor incoming@patchwork.ozlabs.org; Fri, 15 Sep 2017 13:05:41 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:49932)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <sundeep.lkml@gmail.com>) id 1dstxr-0005O3-1K\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 12:59:42 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <sundeep.lkml@gmail.com>) id 1dstxp-00042h-5L\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 12:59:39 -0400", "from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:36829)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <sundeep.lkml@gmail.com>)\n\tid 1dstxo-00042K-S7; Fri, 15 Sep 2017 12:59:37 -0400", "by mail-pg0-x244.google.com with SMTP id d8so1602584pgt.3;\n\tFri, 15 Sep 2017 09:59:36 -0700 (PDT)", "from localhost.localdomain ([124.123.70.3])\n\tby smtp.gmail.com with ESMTPSA id\n\ts17sm3111350pgq.25.2017.09.15.09.59.33\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tFri, 15 Sep 2017 09:59:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=tm10aCIkGW+uG5Vj16uLl/SCD27VG/4Bq7qyBEcyY9Q=;\n\tb=ra16pPeWNAHjDoQpzTrbyfZdEqAAo7BqhtfUSYXimAwG3xxOFSHXsH7+AddsSa8dnm\n\t7ceMiCNstfkSgcLVwKHS9pc0F0Ejw8vobgebRtNQFMVCqdt7cCayUuzsxK/TJVK06InU\n\tHijE3aAc+Bo41x+A88jtzLYya6hqwkPLeOcQ0I5dcXvSqgw6vwK3SGE7JUByNT9dn2cf\n\tdBj1zRaBC07GP2Q9CY+6ifJPbqh2BW+xnaAyFWN+Fw572VpnQRhTBKi64bttrQs7Vi4u\n\tnnW2bvSTf8UtHXai0UiIl7yQlGA5PNtW/+r7FKNRhXSEq7BRIynCkrbVTqgNQhqfNq81\n\tzImQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=tm10aCIkGW+uG5Vj16uLl/SCD27VG/4Bq7qyBEcyY9Q=;\n\tb=pt02E9ikIq2JcWqLhg0xY8llEkCT7tUMPYvBgxXJYqLQl6BcBLJBKZZPEm4kkiKlOt\n\tA3qEXNjWemtaJkUF1Duep8J+Ic44jdi1uVJagsVyuedSfCLKYv1CkHBLybxp6pjHiDAg\n\t1OaZbNQdN4xBouMImNmHzwdgnpAPqKs4jEf/SmzGE+lY6KjCop3Ryy8HGonZuKAZ9HmR\n\tQXGuuZF7rzr4ZHYiqp0GQJnkZpRvuoj2W2pXt9fzytTM+1NAfCUWBAgBKray3oNMv0oN\n\tZuoDzSrPg6yvK4actyYhwILiefBkYkD1s4BWacb/Kkh3FBpHnTUaaiel9VRjAaeq7ixM\n\t6k2w==", "X-Gm-Message-State": "AHPjjUhsWdcskk8eNHkKQHuRgYpTq7Qr9oZ0SlNAfd3HTQXGjHbN368p\n\tHzaqNKnXPTiA6aNM", "X-Google-Smtp-Source": "ADKCNb7tBf4EierF8Hrx9kG/rV15dqaxWr0QPYYFnMNYIl1U6Jj+g5dH2gyODjh54NzI+3NHi7nz4Q==", "X-Received": "by 10.101.64.139 with SMTP id t11mr15430004pgp.299.1505494775538;\n\tFri, 15 Sep 2017 09:59:35 -0700 (PDT)", "From": "Subbaraya Sundeep <sundeep.lkml@gmail.com>", "To": "qemu-devel@nongnu.org,\n\tqemu-arm@nongnu.org", "Date": "Fri, 15 Sep 2017 22:29:11 +0530", "Message-Id": "<1505494753-10837-4-git-send-email-sundeep.lkml@gmail.com>", "X-Mailer": "git-send-email 2.5.0", "In-Reply-To": "<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>", "References": "<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::244", "Subject": "[Qemu-devel] [Qemu devel v9 PATCH 3/5] msf2: Add Smartfusion2 SPI\n\tcontroller", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Subbaraya Sundeep <sundeep.lkml@gmail.com>,\n\tf4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Modelled Microsemi's Smartfusion2 SPI controller.\n\nSigned-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>\nReviewed-by: Alistair Francis <alistair.francis@xilinx.com>\n---\n hw/ssi/Makefile.objs | 1 +\n hw/ssi/mss-spi.c | 404 +++++++++++++++++++++++++++++++++++++++++++++++\n include/hw/ssi/mss-spi.h | 58 +++++++\n 3 files changed, 463 insertions(+)\n create mode 100644 hw/ssi/mss-spi.c\n create mode 100644 include/hw/ssi/mss-spi.h", "diff": "diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs\nindex 487add2..f5bcc65 100644\n--- a/hw/ssi/Makefile.objs\n+++ b/hw/ssi/Makefile.objs\n@@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o\n common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o\n common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o\n common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o\n+common-obj-$(CONFIG_MSF2) += mss-spi.o\n \n obj-$(CONFIG_OMAP) += omap_spi.o\n obj-$(CONFIG_IMX) += imx_spi.o\ndiff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c\nnew file mode 100644\nindex 0000000..5a8e308\n--- /dev/null\n+++ b/hw/ssi/mss-spi.c\n@@ -0,0 +1,404 @@\n+/*\n+ * Block model of SPI controller present in\n+ * Microsemi's SmartFusion2 and SmartFusion SoCs.\n+ *\n+ * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/ssi/mss-spi.h\"\n+#include \"qemu/log.h\"\n+\n+#ifndef MSS_SPI_ERR_DEBUG\n+#define MSS_SPI_ERR_DEBUG 0\n+#endif\n+\n+#define DB_PRINT_L(lvl, fmt, args...) do { \\\n+ if (MSS_SPI_ERR_DEBUG >= lvl) { \\\n+ qemu_log(\"%s: \" fmt \"\\n\", __func__, ## args); \\\n+ } \\\n+} while (0);\n+\n+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)\n+\n+#define FIFO_CAPACITY 32\n+\n+#define R_SPI_CONTROL 0\n+#define R_SPI_DFSIZE 1\n+#define R_SPI_STATUS 2\n+#define R_SPI_INTCLR 3\n+#define R_SPI_RX 4\n+#define R_SPI_TX 5\n+#define R_SPI_CLKGEN 6\n+#define R_SPI_SS 7\n+#define R_SPI_MIS 8\n+#define R_SPI_RIS 9\n+\n+#define S_TXDONE (1 << 0)\n+#define S_RXRDY (1 << 1)\n+#define S_RXCHOVRF (1 << 2)\n+#define S_RXFIFOFUL (1 << 4)\n+#define S_RXFIFOFULNXT (1 << 5)\n+#define S_RXFIFOEMP (1 << 6)\n+#define S_RXFIFOEMPNXT (1 << 7)\n+#define S_TXFIFOFUL (1 << 8)\n+#define S_TXFIFOFULNXT (1 << 9)\n+#define S_TXFIFOEMP (1 << 10)\n+#define S_TXFIFOEMPNXT (1 << 11)\n+#define S_FRAMESTART (1 << 12)\n+#define S_SSEL (1 << 13)\n+#define S_ACTIVE (1 << 14)\n+\n+#define C_ENABLE (1 << 0)\n+#define C_MODE (1 << 1)\n+#define C_INTRXDATA (1 << 4)\n+#define C_INTTXDATA (1 << 5)\n+#define C_INTRXOVRFLO (1 << 6)\n+#define C_SPS (1 << 26)\n+#define C_BIGFIFO (1 << 29)\n+#define C_RESET (1 << 31)\n+\n+#define FRAMESZ_MASK 0x1F\n+#define FMCOUNT_MASK 0x00FFFF00\n+#define FMCOUNT_SHIFT 8\n+\n+static void txfifo_reset(MSSSpiState *s)\n+{\n+ fifo32_reset(&s->tx_fifo);\n+\n+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;\n+ s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;\n+}\n+\n+static void rxfifo_reset(MSSSpiState *s)\n+{\n+ fifo32_reset(&s->rx_fifo);\n+\n+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;\n+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;\n+}\n+\n+static void set_fifodepth(MSSSpiState *s)\n+{\n+ unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;\n+\n+ if (size <= 8) {\n+ s->fifo_depth = 32;\n+ } else if (size <= 16) {\n+ s->fifo_depth = 16;\n+ } else if (size <= 32) {\n+ s->fifo_depth = 8;\n+ } else {\n+ s->fifo_depth = 4;\n+ }\n+}\n+\n+static void update_mis(MSSSpiState *s)\n+{\n+ uint32_t reg = s->regs[R_SPI_CONTROL];\n+ uint32_t tmp;\n+\n+ /*\n+ * form the Control register interrupt enable bits\n+ * same as RIS, MIS and Interrupt clear registers for simplicity\n+ */\n+ tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |\n+ ((reg & C_INTTXDATA) >> 5);\n+ s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];\n+}\n+\n+static void spi_update_irq(MSSSpiState *s)\n+{\n+ int irq;\n+\n+ update_mis(s);\n+ irq = !!(s->regs[R_SPI_MIS]);\n+\n+ qemu_set_irq(s->irq, irq);\n+}\n+\n+static void mss_spi_reset(DeviceState *d)\n+{\n+ MSSSpiState *s = MSS_SPI(d);\n+\n+ memset(s->regs, 0, sizeof s->regs);\n+ s->regs[R_SPI_CONTROL] = 0x80000102;\n+ s->regs[R_SPI_DFSIZE] = 0x4;\n+ s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;\n+ s->regs[R_SPI_CLKGEN] = 0x7;\n+ s->regs[R_SPI_RIS] = 0x0;\n+\n+ s->fifo_depth = 4;\n+ s->frame_count = 1;\n+ s->enabled = false;\n+\n+ rxfifo_reset(s);\n+ txfifo_reset(s);\n+}\n+\n+static uint64_t\n+spi_read(void *opaque, hwaddr addr, unsigned int size)\n+{\n+ MSSSpiState *s = opaque;\n+ uint32_t ret = 0;\n+\n+ addr >>= 2;\n+ switch (addr) {\n+ case R_SPI_RX:\n+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;\n+ s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;\n+ ret = fifo32_pop(&s->rx_fifo);\n+ if (fifo32_is_empty(&s->rx_fifo)) {\n+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;\n+ }\n+ break;\n+\n+ case R_SPI_MIS:\n+ update_mis(s);\n+ ret = s->regs[R_SPI_MIS];\n+ break;\n+\n+ default:\n+ if (addr < ARRAY_SIZE(s->regs)) {\n+ ret = s->regs[addr];\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: Bad offset 0x%\" HWADDR_PRIx \"\\n\", __func__,\n+ addr * 4);\n+ return ret;\n+ }\n+ break;\n+ }\n+\n+ DB_PRINT(\"addr=0x%\" HWADDR_PRIx \" = 0x%\" PRIx32, addr * 4, ret);\n+ spi_update_irq(s);\n+ return ret;\n+}\n+\n+static void assert_cs(MSSSpiState *s)\n+{\n+ qemu_set_irq(s->cs_line, 0);\n+}\n+\n+static void deassert_cs(MSSSpiState *s)\n+{\n+ qemu_set_irq(s->cs_line, 1);\n+}\n+\n+static void spi_flush_txfifo(MSSSpiState *s)\n+{\n+ uint32_t tx;\n+ uint32_t rx;\n+ bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);\n+\n+ /*\n+ * Chip Select(CS) is automatically controlled by this controller.\n+ * If SPS bit is set in Control register then CS is asserted\n+ * until all the frames set in frame count of Control register are\n+ * transferred. If SPS is not set then CS pulses between frames.\n+ * Note that Slave Select register specifies which of the CS line\n+ * has to be controlled automatically by controller. Bits SS[7:1] are for\n+ * masters in FPGA fabric since we model only Microcontroller subsystem\n+ * of Smartfusion2 we control only one CS(SS[0]) line.\n+ */\n+ while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {\n+ assert_cs(s);\n+\n+ s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);\n+\n+ tx = fifo32_pop(&s->tx_fifo);\n+ DB_PRINT(\"data tx:0x%\" PRIx32, tx);\n+ rx = ssi_transfer(s->spi, tx);\n+ DB_PRINT(\"data rx:0x%\" PRIx32, rx);\n+\n+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {\n+ s->regs[R_SPI_STATUS] |= S_RXCHOVRF;\n+ s->regs[R_SPI_RIS] |= S_RXCHOVRF;\n+ } else {\n+ fifo32_push(&s->rx_fifo, rx);\n+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;\n+ if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {\n+ s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;\n+ } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {\n+ s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;\n+ }\n+ }\n+ s->frame_count--;\n+ if (!sps) {\n+ deassert_cs(s);\n+ }\n+ }\n+\n+ if (!s->frame_count) {\n+ s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>\n+ FMCOUNT_SHIFT;\n+ deassert_cs(s);\n+ s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;\n+ s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;\n+ }\n+}\n+\n+static void spi_write(void *opaque, hwaddr addr,\n+ uint64_t val64, unsigned int size)\n+{\n+ MSSSpiState *s = opaque;\n+ uint32_t value = val64;\n+\n+ DB_PRINT(\"addr=0x%\" HWADDR_PRIx \" =0x%\" PRIx32, addr, value);\n+ addr >>= 2;\n+\n+ switch (addr) {\n+ case R_SPI_TX:\n+ /* adding to already full FIFO */\n+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {\n+ break;\n+ }\n+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;\n+ fifo32_push(&s->tx_fifo, value);\n+ if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {\n+ s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;\n+ } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {\n+ s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;\n+ }\n+ if (s->enabled) {\n+ spi_flush_txfifo(s);\n+ }\n+ break;\n+\n+ case R_SPI_CONTROL:\n+ s->regs[R_SPI_CONTROL] = value;\n+ if (value & C_BIGFIFO) {\n+ set_fifodepth(s);\n+ } else {\n+ s->fifo_depth = 4;\n+ }\n+ s->enabled = value & C_ENABLE;\n+ s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;\n+ if (value & C_RESET) {\n+ mss_spi_reset(DEVICE(s));\n+ }\n+ break;\n+\n+ case R_SPI_DFSIZE:\n+ if (s->enabled) {\n+ break;\n+ }\n+ s->regs[R_SPI_DFSIZE] = value;\n+ break;\n+\n+ case R_SPI_INTCLR:\n+ s->regs[R_SPI_INTCLR] = value;\n+ if (value & S_TXDONE) {\n+ s->regs[R_SPI_RIS] &= ~S_TXDONE;\n+ }\n+ if (value & S_RXRDY) {\n+ s->regs[R_SPI_RIS] &= ~S_RXRDY;\n+ }\n+ if (value & S_RXCHOVRF) {\n+ s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;\n+ }\n+ break;\n+\n+ case R_SPI_MIS:\n+ case R_SPI_STATUS:\n+ case R_SPI_RIS:\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: Write to read only register 0x%\" HWADDR_PRIx \"\\n\",\n+ __func__, addr * 4);\n+ break;\n+\n+ default:\n+ if (addr < ARRAY_SIZE(s->regs)) {\n+ s->regs[addr] = value;\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: Bad offset 0x%\" HWADDR_PRIx \"\\n\", __func__,\n+ addr * 4);\n+ }\n+ break;\n+ }\n+\n+ spi_update_irq(s);\n+}\n+\n+static const MemoryRegionOps spi_ops = {\n+ .read = spi_read,\n+ .write = spi_write,\n+ .endianness = DEVICE_NATIVE_ENDIAN,\n+ .valid = {\n+ .min_access_size = 1,\n+ .max_access_size = 4\n+ }\n+};\n+\n+static void mss_spi_realize(DeviceState *dev, Error **errp)\n+{\n+ MSSSpiState *s = MSS_SPI(dev);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);\n+\n+ s->spi = ssi_create_bus(dev, \"spi\");\n+\n+ sysbus_init_irq(sbd, &s->irq);\n+ ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);\n+ sysbus_init_irq(sbd, &s->cs_line);\n+\n+ memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,\n+ TYPE_MSS_SPI, R_SPI_MAX * 4);\n+ sysbus_init_mmio(sbd, &s->mmio);\n+\n+ fifo32_create(&s->tx_fifo, FIFO_CAPACITY);\n+ fifo32_create(&s->rx_fifo, FIFO_CAPACITY);\n+}\n+\n+static const VMStateDescription vmstate_mss_spi = {\n+ .name = TYPE_MSS_SPI,\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_FIFO32(tx_fifo, MSSSpiState),\n+ VMSTATE_FIFO32(rx_fifo, MSSSpiState),\n+ VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static void mss_spi_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->realize = mss_spi_realize;\n+ dc->reset = mss_spi_reset;\n+ dc->vmsd = &vmstate_mss_spi;\n+}\n+\n+static const TypeInfo mss_spi_info = {\n+ .name = TYPE_MSS_SPI,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(MSSSpiState),\n+ .class_init = mss_spi_class_init,\n+};\n+\n+static void mss_spi_register_types(void)\n+{\n+ type_register_static(&mss_spi_info);\n+}\n+\n+type_init(mss_spi_register_types)\ndiff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h\nnew file mode 100644\nindex 0000000..f0cf324\n--- /dev/null\n+++ b/include/hw/ssi/mss-spi.h\n@@ -0,0 +1,58 @@\n+/*\n+ * Microsemi SmartFusion2 SPI\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#ifndef HW_MSS_SPI_H\n+#define HW_MSS_SPI_H\n+\n+#include \"hw/sysbus.h\"\n+#include \"hw/ssi/ssi.h\"\n+#include \"qemu/fifo32.h\"\n+\n+#define TYPE_MSS_SPI \"mss-spi\"\n+#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)\n+\n+#define R_SPI_MAX 16\n+\n+typedef struct MSSSpiState {\n+ SysBusDevice parent_obj;\n+\n+ MemoryRegion mmio;\n+\n+ qemu_irq irq;\n+\n+ qemu_irq cs_line;\n+\n+ SSIBus *spi;\n+\n+ Fifo32 rx_fifo;\n+ Fifo32 tx_fifo;\n+\n+ int fifo_depth;\n+ uint32_t frame_count;\n+ bool enabled;\n+\n+ uint32_t regs[R_SPI_MAX];\n+} MSSSpiState;\n+\n+#endif /* HW_MSS_SPI_H */\n", "prefixes": [ "Qemu", "devel", "v9", "3/5" ] }