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GET /api/patches/814333/?format=api
{ "id": 814333, "url": "http://patchwork.ozlabs.org/api/patches/814333/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505494753-10837-2-git-send-email-sundeep.lkml@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505494753-10837-2-git-send-email-sundeep.lkml@gmail.com>", "list_archive_url": null, "date": "2017-09-15T16:59:09", "name": "[Qemu,devel,v9,1/5] msf2: Add Smartfusion2 System timer", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c177f65004036c1d9ff8a634662a1cc0170c7804", "submitter": { "id": 64324, "url": "http://patchwork.ozlabs.org/api/people/64324/?format=api", "name": "sundeep subbaraya", "email": "sundeep.lkml@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505494753-10837-2-git-send-email-sundeep.lkml@gmail.com/mbox/", "series": [ { "id": 3336, "url": "http://patchwork.ozlabs.org/api/series/3336/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3336", "date": "2017-09-15T16:59:10", "name": "Add support for Smartfusion2 SoC", "version": 9, "mbox": "http://patchwork.ozlabs.org/series/3336/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/814333/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/814333/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"iECxh/xP\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xv1v92mWPz9sNc\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 16 Sep 2017 03:03:33 +1000 (AEST)", "from localhost ([::1]:54298 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dsu1b-0000kq-Gj\n\tfor incoming@patchwork.ozlabs.org; Fri, 15 Sep 2017 13:03:31 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:49856)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <sundeep.lkml@gmail.com>) id 1dstxl-0005KL-OJ\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 12:59:35 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <sundeep.lkml@gmail.com>) id 1dstxj-0003zq-RV\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 12:59:33 -0400", "from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:34730)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <sundeep.lkml@gmail.com>)\n\tid 1dstxj-0003zY-JB; Fri, 15 Sep 2017 12:59:31 -0400", "by mail-pg0-x243.google.com with SMTP id v82so1610152pgb.1;\n\tFri, 15 Sep 2017 09:59:31 -0700 (PDT)", "from localhost.localdomain ([124.123.70.3])\n\tby smtp.gmail.com with ESMTPSA id\n\ts17sm3111350pgq.25.2017.09.15.09.59.27\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tFri, 15 Sep 2017 09:59:29 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=rYDUhEAMbeLgPAtDNnRzVQNjcZJ/BvND+g5qLvUVVhg=;\n\tb=iECxh/xPF6KNvyMrIMYJzOSftnPDtL99LvBQbqTG3UKDT3fLHx+b149AWoUN6j9bEW\n\thl3Xdwmt9q6U5DzOc+aK9sGzPv4RPmE0MjVv9Pp7YSTP/CQh/1P3iEVoXCddIs+3rcgC\n\tUENvsYtxSjuRmS25xzuT/EMJFeCiiCFi75z2LxxEARzl8jMB8zxx+sGnQWwk88Dru7y+\n\tgECuRHWbmliCMfzS+ehBar20yVigE1JvWedazoH5nc+YLCghWlrH5Lm31iX0wKU6/MGA\n\tn2RbHTxvJaDxUN1wSFuuq0JTBRkP+sT3btfbSY20+i3q3ftcfjjiq+M+6N/b2y2+VmGM\n\txRrA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=rYDUhEAMbeLgPAtDNnRzVQNjcZJ/BvND+g5qLvUVVhg=;\n\tb=gRCxPaP2mn254nkaazRcOGgJl5jIUQrBQ6IvzF5TIwb+JhqPcsl2eWbCUQkO1gBqDp\n\tlVszbQXHYRLvrQkGQnTpbAno57VgI0fW3V8+jdmBB1mvujuwKevr4ydEh/86Klw4zaQw\n\tXIsra1JaEe8V+78URvFHjsjHk2FJOHW23UekN/VNUsKeMf7ZrmUFCqRWd3CDN6mmrVUZ\n\tRWf3AGlmrw8FqQaGqXew0RBsSBdDZEKMMEmpyhr9/VRHgLorje801/xj5ET169FXaRSt\n\tD8Sx7J3SwpwX/kIK6oeVjy1PlJfEsyUG5bbHjxXxA+CUuI+eqEiWESQpIG3ItHBMHBHD\n\tynKw==", "X-Gm-Message-State": "AHPjjUjMjgiELE+q1QX+OVb5xZzMO4DYJDB7JvLfqv6f+9MSMihtsQVO\n\tP8t4Oefo4NGnZY44", "X-Google-Smtp-Source": "ADKCNb67N4e7mygHfiMEgR7EODPfBvsgzXiJdgMSNZoYswo/7OE6K4QFFwJnbRkoUUsHFWlJt3lCqw==", "X-Received": "by 10.98.194.130 with SMTP id w2mr24556644pfk.50.1505494770219; \n\tFri, 15 Sep 2017 09:59:30 -0700 (PDT)", "From": "Subbaraya Sundeep <sundeep.lkml@gmail.com>", "To": "qemu-devel@nongnu.org,\n\tqemu-arm@nongnu.org", "Date": "Fri, 15 Sep 2017 22:29:09 +0530", "Message-Id": "<1505494753-10837-2-git-send-email-sundeep.lkml@gmail.com>", "X-Mailer": "git-send-email 2.5.0", "In-Reply-To": "<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>", "References": "<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::243", "Subject": "[Qemu-devel] [Qemu devel v9 PATCH 1/5] msf2: Add Smartfusion2\n\tSystem timer", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Subbaraya Sundeep <sundeep.lkml@gmail.com>,\n\tf4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Modelled System Timer in Microsemi's Smartfusion2 Soc.\nTimer has two 32bit down counters and two interrupts.\n\nSigned-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>\nReviewed-by: Alistair Francis <alistair.francis@xilinx.com>\n---\n hw/timer/Makefile.objs | 1 +\n hw/timer/mss-timer.c | 289 +++++++++++++++++++++++++++++++++++++++++++\n include/hw/timer/mss-timer.h | 64 ++++++++++\n 3 files changed, 354 insertions(+)\n create mode 100644 hw/timer/mss-timer.c\n create mode 100644 include/hw/timer/mss-timer.h", "diff": "diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs\nindex 15cce1c..8c19eac 100644\n--- a/hw/timer/Makefile.objs\n+++ b/hw/timer/Makefile.objs\n@@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o\n \n common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o\n common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o\n+common-obj-$(CONFIG_MSF2) += mss-timer.o\ndiff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c\nnew file mode 100644\nindex 0000000..60f1213\n--- /dev/null\n+++ b/hw/timer/mss-timer.c\n@@ -0,0 +1,289 @@\n+/*\n+ * Block model of System timer present in\n+ * Microsemi's SmartFusion2 and SmartFusion SoCs.\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/main-loop.h\"\n+#include \"qemu/log.h\"\n+#include \"hw/timer/mss-timer.h\"\n+\n+#ifndef MSS_TIMER_ERR_DEBUG\n+#define MSS_TIMER_ERR_DEBUG 0\n+#endif\n+\n+#define DB_PRINT_L(lvl, fmt, args...) do { \\\n+ if (MSS_TIMER_ERR_DEBUG >= lvl) { \\\n+ qemu_log(\"%s: \" fmt \"\\n\", __func__, ## args); \\\n+ } \\\n+} while (0);\n+\n+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)\n+\n+#define R_TIM_VAL 0\n+#define R_TIM_LOADVAL 1\n+#define R_TIM_BGLOADVAL 2\n+#define R_TIM_CTRL 3\n+#define R_TIM_RIS 4\n+#define R_TIM_MIS 5\n+\n+#define TIMER_CTRL_ENBL (1 << 0)\n+#define TIMER_CTRL_ONESHOT (1 << 1)\n+#define TIMER_CTRL_INTR (1 << 2)\n+#define TIMER_RIS_ACK (1 << 0)\n+#define TIMER_RST_CLR (1 << 6)\n+#define TIMER_MODE (1 << 0)\n+\n+static void timer_update_irq(struct Msf2Timer *st)\n+{\n+ bool isr, ier;\n+\n+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);\n+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);\n+ qemu_set_irq(st->irq, (ier && isr));\n+}\n+\n+static void timer_update(struct Msf2Timer *st)\n+{\n+ uint64_t count;\n+\n+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {\n+ ptimer_stop(st->ptimer);\n+ return;\n+ }\n+\n+ count = st->regs[R_TIM_LOADVAL];\n+ ptimer_set_limit(st->ptimer, count, 1);\n+ ptimer_run(st->ptimer, 1);\n+}\n+\n+static uint64_t\n+timer_read(void *opaque, hwaddr offset, unsigned int size)\n+{\n+ MSSTimerState *t = opaque;\n+ hwaddr addr;\n+ struct Msf2Timer *st;\n+ uint32_t ret = 0;\n+ int timer = 0;\n+ int isr;\n+ int ier;\n+\n+ addr = offset >> 2;\n+ /*\n+ * Two independent timers has same base address.\n+ * Based on address passed figure out which timer is being used.\n+ */\n+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {\n+ timer = 1;\n+ addr -= R_TIM1_MAX;\n+ }\n+\n+ st = &t->timers[timer];\n+\n+ switch (addr) {\n+ case R_TIM_VAL:\n+ ret = ptimer_get_count(st->ptimer);\n+ break;\n+\n+ case R_TIM_MIS:\n+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);\n+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);\n+ ret = ier & isr;\n+ break;\n+\n+ default:\n+ if (addr < R_TIM1_MAX) {\n+ ret = st->regs[addr];\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ TYPE_MSS_TIMER\": 64-bit mode not supported\\n\");\n+ return ret;\n+ }\n+ break;\n+ }\n+\n+ DB_PRINT(\"timer=%d 0x%\" HWADDR_PRIx \"=0x%\" PRIx32, timer, offset,\n+ ret);\n+ return ret;\n+}\n+\n+static void\n+timer_write(void *opaque, hwaddr offset,\n+ uint64_t val64, unsigned int size)\n+{\n+ MSSTimerState *t = opaque;\n+ hwaddr addr;\n+ struct Msf2Timer *st;\n+ int timer = 0;\n+ uint32_t value = val64;\n+\n+ addr = offset >> 2;\n+ /*\n+ * Two independent timers has same base address.\n+ * Based on addr passed figure out which timer is being used.\n+ */\n+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {\n+ timer = 1;\n+ addr -= R_TIM1_MAX;\n+ }\n+\n+ st = &t->timers[timer];\n+\n+ DB_PRINT(\"addr=0x%\" HWADDR_PRIx \" val=0x%\" PRIx32 \" (timer=%d)\", offset,\n+ value, timer);\n+\n+ switch (addr) {\n+ case R_TIM_CTRL:\n+ st->regs[R_TIM_CTRL] = value;\n+ timer_update(st);\n+ break;\n+\n+ case R_TIM_RIS:\n+ if (value & TIMER_RIS_ACK) {\n+ st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;\n+ }\n+ break;\n+\n+ case R_TIM_LOADVAL:\n+ st->regs[R_TIM_LOADVAL] = value;\n+ if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {\n+ timer_update(st);\n+ }\n+ break;\n+\n+ case R_TIM_BGLOADVAL:\n+ st->regs[R_TIM_BGLOADVAL] = value;\n+ st->regs[R_TIM_LOADVAL] = value;\n+ break;\n+\n+ case R_TIM_VAL:\n+ case R_TIM_MIS:\n+ break;\n+\n+ default:\n+ if (addr < R_TIM1_MAX) {\n+ st->regs[addr] = value;\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ TYPE_MSS_TIMER\": 64-bit mode not supported\\n\");\n+ return;\n+ }\n+ break;\n+ }\n+ timer_update_irq(st);\n+}\n+\n+static const MemoryRegionOps timer_ops = {\n+ .read = timer_read,\n+ .write = timer_write,\n+ .endianness = DEVICE_NATIVE_ENDIAN,\n+ .valid = {\n+ .min_access_size = 1,\n+ .max_access_size = 4\n+ }\n+};\n+\n+static void timer_hit(void *opaque)\n+{\n+ struct Msf2Timer *st = opaque;\n+\n+ st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;\n+\n+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {\n+ timer_update(st);\n+ }\n+ timer_update_irq(st);\n+}\n+\n+static void mss_timer_init(Object *obj)\n+{\n+ MSSTimerState *t = MSS_TIMER(obj);\n+ int i;\n+\n+ /* Init all the ptimers. */\n+ for (i = 0; i < NUM_TIMERS; i++) {\n+ struct Msf2Timer *st = &t->timers[i];\n+\n+ st->bh = qemu_bh_new(timer_hit, st);\n+ st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);\n+ ptimer_set_freq(st->ptimer, t->freq_hz);\n+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);\n+ }\n+\n+ memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,\n+ NUM_TIMERS * R_TIM1_MAX * 4);\n+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);\n+}\n+\n+static const VMStateDescription vmstate_timers = {\n+ .name = \"mss-timer-block\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_PTIMER(ptimer, struct Msf2Timer),\n+ VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static const VMStateDescription vmstate_mss_timer = {\n+ .name = TYPE_MSS_TIMER,\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_UINT32(freq_hz, MSSTimerState),\n+ VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,\n+ vmstate_timers, struct Msf2Timer),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static Property mss_timer_properties[] = {\n+ /* Libero GUI shows 100Mhz as default for clocks */\n+ DEFINE_PROP_UINT32(\"clock-frequency\", MSSTimerState, freq_hz,\n+ 100 * 1000000),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n+static void mss_timer_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->props = mss_timer_properties;\n+ dc->vmsd = &vmstate_mss_timer;\n+}\n+\n+static const TypeInfo mss_timer_info = {\n+ .name = TYPE_MSS_TIMER,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(MSSTimerState),\n+ .instance_init = mss_timer_init,\n+ .class_init = mss_timer_class_init,\n+};\n+\n+static void mss_timer_register_types(void)\n+{\n+ type_register_static(&mss_timer_info);\n+}\n+\n+type_init(mss_timer_register_types)\ndiff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h\nnew file mode 100644\nindex 0000000..d15d173\n--- /dev/null\n+++ b/include/hw/timer/mss-timer.h\n@@ -0,0 +1,64 @@\n+/*\n+ * Microsemi SmartFusion2 Timer.\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#ifndef HW_MSS_TIMER_H\n+#define HW_MSS_TIMER_H\n+\n+#include \"hw/sysbus.h\"\n+#include \"hw/ptimer.h\"\n+\n+#define TYPE_MSS_TIMER \"mss-timer\"\n+#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \\\n+ (obj), TYPE_MSS_TIMER)\n+\n+/*\n+ * There are two 32-bit down counting timers.\n+ * Timers 1 and 2 can be concatenated into a single 64-bit Timer\n+ * that operates either in Periodic mode or in One-shot mode.\n+ * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.\n+ * In 64-bit mode, writing to the 32-bit registers has no effect.\n+ * Similarly, in 32-bit mode, writing to the 64-bit mode registers\n+ * has no effect. Only two 32-bit timers are supported currently.\n+ */\n+#define NUM_TIMERS 2\n+\n+#define R_TIM1_MAX 6\n+\n+struct Msf2Timer {\n+ QEMUBH *bh;\n+ ptimer_state *ptimer;\n+\n+ uint32_t regs[R_TIM1_MAX];\n+ qemu_irq irq;\n+};\n+\n+typedef struct MSSTimerState {\n+ SysBusDevice parent_obj;\n+\n+ MemoryRegion mmio;\n+ uint32_t freq_hz;\n+ struct Msf2Timer timers[NUM_TIMERS];\n+} MSSTimerState;\n+\n+#endif /* HW_MSS_TIMER_H */\n", "prefixes": [ "Qemu", "devel", "v9", "1/5" ] }