Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/813824/?format=api
{ "id": 813824, "url": "http://patchwork.ozlabs.org/api/patches/813824/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/150539848430.21523.2732328570419779115.stgit@bahia/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<150539848430.21523.2732328570419779115.stgit@bahia>", "list_archive_url": null, "date": "2017-09-14T14:14:44", "name": "[v2,2/2] spapr_pci: make index property mandatory", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "71f1b948b93c43673eb471648170f95144628539", "submitter": { "id": 69178, "url": "http://patchwork.ozlabs.org/api/people/69178/?format=api", "name": "Greg Kurz", "email": "groug@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/150539848430.21523.2732328570419779115.stgit@bahia/mbox/", "series": [ { "id": 3102, "url": "http://patchwork.ozlabs.org/api/series/3102/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3102", "date": "2017-09-14T14:14:21", "name": "spapr_pci: make index property mandatory", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/3102/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813824/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813824/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtLDp1RqXz9s4s\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 15 Sep 2017 00:16:26 +1000 (AEST)", "from localhost ([::1]:48053 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dsUwK-0005Qd-6C\n\tfor incoming@patchwork.ozlabs.org; Thu, 14 Sep 2017 10:16:24 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:59680)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <groug@kaod.org>) id 1dsUus-0004cM-Rm\n\tfor qemu-devel@nongnu.org; Thu, 14 Sep 2017 10:14:56 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <groug@kaod.org>) id 1dsUup-00009z-IW\n\tfor qemu-devel@nongnu.org; Thu, 14 Sep 2017 10:14:54 -0400", "from 5.mo2.mail-out.ovh.net ([87.98.181.248]:54263)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <groug@kaod.org>) id 1dsUup-00009N-91\n\tfor qemu-devel@nongnu.org; Thu, 14 Sep 2017 10:14:51 -0400", "from player770.ha.ovh.net (b6.ovh.net [213.186.33.56])\n\tby mo2.mail-out.ovh.net (Postfix) with ESMTP id 4031BAC1DC\n\tfor <qemu-devel@nongnu.org>; Thu, 14 Sep 2017 16:14:50 +0200 (CEST)", "from [192.168.0.243] (gar31-1-82-66-74-139.fbx.proxad.net\n\t[82.66.74.139]) (Authenticated sender: groug@kaod.org)\n\tby player770.ha.ovh.net (Postfix) with ESMTPA id D5B0E3C00CE;\n\tThu, 14 Sep 2017 16:14:44 +0200 (CEST)" ], "From": "Greg Kurz <groug@kaod.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 14 Sep 2017 16:14:44 +0200", "Message-ID": "<150539848430.21523.2732328570419779115.stgit@bahia>", "In-Reply-To": "<150539846159.21523.16161730500010192093.stgit@bahia>", "References": "<150539846159.21523.16161730500010192093.stgit@bahia>", "User-Agent": "StGit/0.17.1-46-g6855-dirty", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "X-Ovh-Tracer-Id": "10293539902228961781", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "gggruggvucftvghtrhhoucdtuddrfeelledrgeeigdejiecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "87.98.181.248", "Subject": "[Qemu-devel] [PATCH v2 2/2] spapr_pci: make index property mandatory", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Alexey Kardashevskiy <aik@ozlabs.ru>, Paolo Bonzini <pbonzini@redhat.com>,\n\tqemu-ppc@nongnu.org, Michael Roth <mdroth@linux.vnet.ibm.com>,\n\tDavid Gibson <david@gibson.dropbear.id.au>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Creating several PHBs without index property confuses the DRC code\nand causes issues:\n- only the first index-less PHB is functional, the other ones will\n silently ignore hotplugging of PCI devices\n- QEMU will even terminate if these PHBs have cold-plugged devices\n\nqemu-system-ppc64: -device virtio-net,bus=pci2.0: an attached device\n is still awaiting release\n\nThis happens because DR connectors for child PCI devices are created\nwith a DRC index that is derived from the PHB's index property. If the\nPHBs are created without index, then the same value of -1 is used to\ncompute the DRC indexes for both PHBs, hence causing the collision.\n\nAlso, the index property is used to compute the placement of the PHB's\nmemory regions. It is limited to 31 or 255, depending on the machine\ntype version. This fits well with the requirements of DRC indexes, which\nneed the PHB index to be a 16-bit value.\n\nThis patch hence makes the index property mandatory. As a consequence,\nthe PHB's memory regions and BUID are now always configured according\nto the index, and it is no longer possible to set them from the command\nline. We have to introduce a PHB instance init function to initialize\nthe 64-bit window address to -1 because pseries-2.7 and older machines\ndon't set it.\n\nThis DOES BREAK backwards compat, but we don't think the non-index\nPHB feature was used in practice (at least libvirt doesn't) and the\nsimplification is worth it.\n\nSigned-off-by: Greg Kurz <groug@kaod.org>\n---\nv1->v2: - error out if mem64_win_pciaddr is set but mem64_win_size\n isn't\n - set mem64_win_addr to -1 for old configuration with 32-bit\n window below 2G in spapr_phb_realize()\n - drop instance init function\n\nRFC->v1: - as suggested dy David, updated the changelog to explicitely\n mention that we intentionally break backwards compat.\n---\n hw/ppc/spapr_pci.c | 53 +++++++++++-----------------------------------------\n 1 file changed, 11 insertions(+), 42 deletions(-)", "diff": "diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c\nindex cf54160526fa..024638e18b53 100644\n--- a/hw/ppc/spapr_pci.c\n+++ b/hw/ppc/spapr_pci.c\n@@ -1523,16 +1523,6 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)\n sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);\n Error *local_err = NULL;\n \n- if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn[0] != (uint32_t)-1)\n- || (sphb->dma_liobn[1] != (uint32_t)-1 && windows_supported == 2)\n- || (sphb->mem_win_addr != (hwaddr)-1)\n- || (sphb->mem64_win_addr != (hwaddr)-1)\n- || (sphb->io_win_addr != (hwaddr)-1)) {\n- error_setg(errp, \"Either \\\"index\\\" or other parameters must\"\n- \" be specified for PAPR PHB, not both\");\n- return;\n- }\n-\n smc->phb_placement(spapr, sphb->index,\n &sphb->buid, &sphb->io_win_addr,\n &sphb->mem_win_addr, &sphb->mem64_win_addr,\n@@ -1541,36 +1531,12 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)\n error_propagate(errp, local_err);\n return;\n }\n- }\n-\n- if (sphb->buid == (uint64_t)-1) {\n- error_setg(errp, \"BUID not specified for PHB\");\n- return;\n- }\n-\n- if ((sphb->dma_liobn[0] == (uint32_t)-1) ||\n- ((sphb->dma_liobn[1] == (uint32_t)-1) && (windows_supported > 1))) {\n- error_setg(errp, \"LIOBN(s) not specified for PHB\");\n- return;\n- }\n-\n- if (sphb->mem_win_addr == (hwaddr)-1) {\n- error_setg(errp, \"Memory window address not specified for PHB\");\n- return;\n- }\n-\n- if (sphb->io_win_addr == (hwaddr)-1) {\n- error_setg(errp, \"IO window address not specified for PHB\");\n+ } else {\n+ error_setg(errp, \"\\\"index\\\" for PAPR PHB is mandatory\");\n return;\n }\n \n if (sphb->mem64_win_size != 0) {\n- if (sphb->mem64_win_addr == (hwaddr)-1) {\n- error_setg(errp,\n- \"64-bit memory window address not specified for PHB\");\n- return;\n- }\n-\n if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {\n error_setg(errp, \"32-bit memory window of size 0x%\"HWADDR_PRIx\n \" (max 2 GiB)\", sphb->mem_win_size);\n@@ -1581,6 +1547,9 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)\n /* 64-bit window defaults to identity mapping */\n sphb->mem64_win_pciaddr = sphb->mem64_win_addr;\n }\n+ } else if (sphb->mem64_win_pciaddr != (hwaddr) -1) {\n+ error_setg(errp, \"64-bit memory window requires \\\"mem64_win_size\\\"\");\n+ return;\n } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {\n /*\n * For compatibility with old configuration, if no 64-bit MMIO\n@@ -1594,6 +1563,12 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)\n sphb->mem64_win_pciaddr =\n SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE;\n sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE;\n+ } else {\n+ /* Old configuration with the 32-bit MMIO window <= 2GiB don't need a\n+ * 64-bit MMIO window.\n+ */\n+ sphb->mem64_win_addr = (hwaddr) -1;\n+ sphb->mem64_win_pciaddr = (hwaddr) -1;\n }\n \n if (spapr_pci_find_phb(spapr, sphb->buid)) {\n@@ -1789,18 +1764,12 @@ static void spapr_phb_reset(DeviceState *qdev)\n \n static Property spapr_phb_properties[] = {\n DEFINE_PROP_UINT32(\"index\", sPAPRPHBState, index, -1),\n- DEFINE_PROP_UINT64(\"buid\", sPAPRPHBState, buid, -1),\n- DEFINE_PROP_UINT32(\"liobn\", sPAPRPHBState, dma_liobn[0], -1),\n- DEFINE_PROP_UINT32(\"liobn64\", sPAPRPHBState, dma_liobn[1], -1),\n- DEFINE_PROP_UINT64(\"mem_win_addr\", sPAPRPHBState, mem_win_addr, -1),\n DEFINE_PROP_UINT64(\"mem_win_size\", sPAPRPHBState, mem_win_size,\n SPAPR_PCI_MEM32_WIN_SIZE),\n- DEFINE_PROP_UINT64(\"mem64_win_addr\", sPAPRPHBState, mem64_win_addr, -1),\n DEFINE_PROP_UINT64(\"mem64_win_size\", sPAPRPHBState, mem64_win_size,\n SPAPR_PCI_MEM64_WIN_SIZE),\n DEFINE_PROP_UINT64(\"mem64_win_pciaddr\", sPAPRPHBState, mem64_win_pciaddr,\n -1),\n- DEFINE_PROP_UINT64(\"io_win_addr\", sPAPRPHBState, io_win_addr, -1),\n DEFINE_PROP_UINT64(\"io_win_size\", sPAPRPHBState, io_win_size,\n SPAPR_PCI_IO_WIN_SIZE),\n DEFINE_PROP_BOOL(\"dynamic-reconfiguration\", sPAPRPHBState, dr_enabled,\n", "prefixes": [ "v2", "2/2" ] }