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GET /api/patches/813507/?format=api
{ "id": 813507, "url": "http://patchwork.ozlabs.org/api/patches/813507/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505318412-27121-9-git-send-email-patrice.chotard@st.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505318412-27121-9-git-send-email-patrice.chotard@st.com>", "list_archive_url": null, "date": "2017-09-13T16:00:11", "name": "[U-Boot,v2,8/9] ARM: DTS: stm32: adapt stm32h7 dts files for U-boot", "commit_ref": "a1e384b4d9df74735f02e3b9a2f8f70ff02543a5", "pull_url": null, "state": "accepted", "archived": false, "hash": "6e50148bf026e1aef259fbf415c5e229ddcfb487", "submitter": { "id": 63958, "url": "http://patchwork.ozlabs.org/api/people/63958/?format=api", "name": "Patrice CHOTARD", "email": "patrice.chotard@st.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505318412-27121-9-git-send-email-patrice.chotard@st.com/mbox/", "series": [ { "id": 2943, "url": "http://patchwork.ozlabs.org/api/series/2943/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=2943", "date": "2017-09-13T16:00:03", "name": "Add STM32H7 SoC, Discovery and Evaluation board support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2943/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813507/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813507/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsml72JnRz9sPk\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 14 Sep 2017 02:07:15 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 8D140C220AA; Wed, 13 Sep 2017 16:06:15 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id ABB54C225B9;\n\tWed, 13 Sep 2017 16:00:49 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 96013C226A7; Wed, 13 Sep 2017 16:00:29 +0000 (UTC)", "from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com\n\t[91.207.212.93])\n\tby lists.denx.de (Postfix) with ESMTPS id D9005C222C4\n\tfor <u-boot@lists.denx.de>; Wed, 13 Sep 2017 16:00:24 +0000 (UTC)", "from pps.filterd (m0046660.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8DFxD1A000876; Wed, 13 Sep 2017 18:00:23 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2cv5e519u3-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tWed, 13 Sep 2017 18:00:23 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0EB1938;\n\tWed, 13 Sep 2017 16:00:23 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DAA3A2B31;\n\tWed, 13 Sep 2017 16:00:22 +0000 (GMT)", "from localhost (10.75.127.46) by SFHDAG6NODE3.st.com (10.75.127.18)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tWed, 13 Sep 2017 18:00:22 +0200" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "From": "<patrice.chotard@st.com>", "To": "<u-boot@lists.denx.de>, <albert.u.boot@aribaud.net>, <sjg@chromium.org>, \n\t<vikas.manocha@st.com>", "Date": "Wed, 13 Sep 2017 18:00:11 +0200", "Message-ID": "<1505318412-27121-9-git-send-email-patrice.chotard@st.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1505318412-27121-1-git-send-email-patrice.chotard@st.com>", "References": "<1505318412-27121-1-git-send-email-patrice.chotard@st.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.75.127.46]", "X-ClientProxiedBy": "SFHDAG6NODE2.st.com (10.75.127.17) To SFHDAG6NODE3.st.com\n\t(10.75.127.18)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-13_04:, , signatures=0", "Subject": "[U-Boot] [PATCH v2 8/9] ARM: DTS: stm32: adapt stm32h7 dts files\n\tfor U-boot", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Patrice Chotard <patrice.chotard@st.com>\n\nThis patch adapts stm32h743 disco and eval dts files to match\nwith U-boot requirements or add features wich are not yet\nupstreamed on kernel side :\n\n_ Add RCC clock driver node and update all clocks phandle\n accordingly.\n\n By default, on kernel side, all clocks was temporarly\n configured as a phandle to timer_clk waiting for a RCC\n clock driver to be available.\n On U-boot side, we now have a dedicated RCC clock driver, we\n can configured all clocks as phandle to this driver.\n\n All this binding update will be available soon in a kernel tag,\n as all the bindings have been acked by Rob Herring [1].\n\n [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html\n\n_ Align STM32H7 serial compatible string with the one which will be\n available in next kernel tag. The bindings has been acked by\n Rob Herring [2].\n This compatible string will be usefull to add stm32h7 specific\n feature for this serial driver.\n\n [2] https://lkml.org/lkml/2017/7/17/739\n\n_ Add gpio compatible and aliases for stm32h743\n\n_ Add FMC sdram node with associated new bindings value to\n manage second bank (ie bank 1).\n\n_ Add missing HSI and CSI oscillators nodes needed\n by STM32H7 RCC clock driver.\n\n Clock sources could be:\n\t_ HSE (High Speed External)\n\t_ HSI (High Speed Internal)\n\t_ CSI (Low Power Internal)\n\n These clocks can be used as clocksource in some configuration.\n By default, HSE is selected as clock source.\n\n_ Set HSE to 25Mhz for stm32h743i-disco and eval board\n\n By default, the external oscillator frequency is defined at\n 25 Mhz in SoC stm32h743.dtsi file.\n It has been set at 125 Mhz in kernel DT temporarly waiting for\n RCC clock driver becomes available.\n\n As in U-boot we got a RCC clock driver, the real value of HSE\n clock can be used.\n\n_ Add \"u-boot,dm-pre-reloc\" for rcc, fmc, fixed-clock, pinctrl,\n pwrcfg and gpio nodes.\n\nSigned-off-by: Patrice Chotard <patrice.chotard@st.com>\n---\n arch/arm/dts/stm32h7-u-boot.dtsi | 88 ++++++++++++++++++++++++++\n arch/arm/dts/stm32h743-pinctrl.dtsi | 102 +++++++++++++++++++++++++++----\n arch/arm/dts/stm32h743.dtsi | 56 ++++++++++++++---\n arch/arm/dts/stm32h743i-disco.dts | 35 +++++++++--\n arch/arm/dts/stm32h743i-eval.dts | 34 +++++++++--\n include/dt-bindings/memory/stm32-sdram.h | 7 +++\n 6 files changed, 294 insertions(+), 28 deletions(-)\n create mode 100644 arch/arm/dts/stm32h7-u-boot.dtsi", "diff": "diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi\nnew file mode 100644\nindex 0000000..2525035\n--- /dev/null\n+++ b/arch/arm/dts/stm32h7-u-boot.dtsi\n@@ -0,0 +1,88 @@\n+/{\n+\tclocks {\n+\t\tu-boot,dm-pre-reloc;\n+\t};\n+\n+\tsoc {\n+\t\tu-boot,dm-pre-reloc;\n+\t\tpin-controller {\n+\t\t\tu-boot,dm-pre-reloc;\n+\t\t};\n+\t};\n+};\n+\n+&clk_hse {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&clk_lse {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&clk_i2s {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&pwrcfg {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&rcc {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&fmc {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&clk_hsi {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&clk_csi {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpioa {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpiob {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpioc {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpiod {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpioe {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpiof {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpiog {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpioh {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpioi {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpioj {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&gpiok {\n+\tu-boot,dm-pre-reloc;\n+};\ndiff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi\nindex 76bbd65..d3e11d5 100644\n--- a/arch/arm/dts/stm32h743-pinctrl.dtsi\n+++ b/arch/arm/dts/stm32h743-pinctrl.dtsi\n@@ -54,88 +54,99 @@\n \t\t\tgpioa: gpio@58020000 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0x0 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOA_CK>;\n \t\t\t\tst,bank-name = \"GPIOA\";\n \t\t\t};\n \n \t\t\tgpiob: gpio@58020400 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0x400 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOB_CK>;\n \t\t\t\tst,bank-name = \"GPIOB\";\n \t\t\t};\n \n \t\t\tgpioc: gpio@58020800 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0x800 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOC_CK>;\n \t\t\t\tst,bank-name = \"GPIOC\";\n \t\t\t};\n \n \t\t\tgpiod: gpio@58020c00 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0xc00 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOD_CK>;\n \t\t\t\tst,bank-name = \"GPIOD\";\n \t\t\t};\n \n \t\t\tgpioe: gpio@58021000 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0x1000 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOE_CK>;\n \t\t\t\tst,bank-name = \"GPIOE\";\n \t\t\t};\n \n \t\t\tgpiof: gpio@58021400 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0x1400 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOF_CK>;\n \t\t\t\tst,bank-name = \"GPIOF\";\n \t\t\t};\n \n \t\t\tgpiog: gpio@58021800 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0x1800 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOG_CK>;\n \t\t\t\tst,bank-name = \"GPIOG\";\n \t\t\t};\n \n \t\t\tgpioh: gpio@58021c00 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0x1c00 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOH_CK>;\n \t\t\t\tst,bank-name = \"GPIOH\";\n \t\t\t};\n \n \t\t\tgpioi: gpio@58022000 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0x2000 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOI_CK>;\n \t\t\t\tst,bank-name = \"GPIOI\";\n \t\t\t};\n \n \t\t\tgpioj: gpio@58022400 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0x2400 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOJ_CK>;\n \t\t\t\tst,bank-name = \"GPIOJ\";\n \t\t\t};\n \n \t\t\tgpiok: gpio@58022800 {\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tcompatible = \"st,stm32-gpio\";\n \t\t\t\treg = <0x2800 0x400>;\n-\t\t\t\tclocks = <&timer_clk>;\n+\t\t\t\tclocks = <&rcc GPIOK_CK>;\n \t\t\t\tst,bank-name = \"GPIOK\";\n \t\t\t};\n \n@@ -164,6 +175,75 @@\n \t\t\t\t\tbias-disable;\n \t\t\t\t};\n \t\t\t};\n+\n+\t\t\tfmc_pins: fmc@0 {\n+\t\t\t\t pins {\n+\t\t\t\t\t pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,\n+\t\t\t\t\t\t <STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,\n+\t\t\t\t\t\t <STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,\n+\t\t\t\t\t\t <STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,\n+\t\t\t\t\t\t <STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,\n+\t\t\t\t\t\t <STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,\n+\t\t\t\t\t\t <STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,\n+\n+\t\t\t\t\t\t <STM32H7_PE0_FUNC_FMC_NBL0>,\n+\t\t\t\t\t\t <STM32H7_PE1_FUNC_FMC_NBL1>,\n+\t\t\t\t\t\t <STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,\n+\t\t\t\t\t\t <STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,\n+\t\t\t\t\t\t <STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,\n+\t\t\t\t\t\t <STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,\n+\t\t\t\t\t\t <STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,\n+\t\t\t\t\t\t <STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,\n+\t\t\t\t\t\t <STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,\n+\t\t\t\t\t\t <STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,\n+\t\t\t\t\t\t <STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,\n+\n+\t\t\t\t\t\t <STM32H7_PF0_FUNC_FMC_A0>,\n+\t\t\t\t\t\t <STM32H7_PF1_FUNC_FMC_A1>,\n+\t\t\t\t\t\t <STM32H7_PF2_FUNC_FMC_A2>,\n+\t\t\t\t\t\t <STM32H7_PF3_FUNC_FMC_A3>,\n+\t\t\t\t\t\t <STM32H7_PF4_FUNC_FMC_A4>,\n+\t\t\t\t\t\t <STM32H7_PF5_FUNC_FMC_A5>,\n+\t\t\t\t\t\t <STM32H7_PF11_FUNC_FMC_SDNRAS>,\n+\t\t\t\t\t\t <STM32H7_PF12_FUNC_FMC_A6>,\n+\t\t\t\t\t\t <STM32H7_PF13_FUNC_FMC_A7>,\n+\t\t\t\t\t\t <STM32H7_PF14_FUNC_FMC_A8>,\n+\t\t\t\t\t\t <STM32H7_PF15_FUNC_FMC_A9>,\n+\n+\t\t\t\t\t\t <STM32H7_PG0_FUNC_FMC_A10>,\n+\t\t\t\t\t\t <STM32H7_PG1_FUNC_FMC_A11>,\n+\t\t\t\t\t\t <STM32H7_PG2_FUNC_FMC_A12>,\n+\t\t\t\t\t\t <STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,\n+\t\t\t\t\t\t <STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,\n+\t\t\t\t\t\t <STM32H7_PG8_FUNC_FMC_SDCLK>,\n+\t\t\t\t\t\t <STM32H7_PG15_FUNC_FMC_SDNCAS>,\n+\n+\t\t\t\t\t\t <STM32H7_PH5_FUNC_FMC_SDNWE>,\n+\t\t\t\t\t\t <STM32H7_PH6_FUNC_FMC_SDNE1>,\n+\t\t\t\t\t\t <STM32H7_PH7_FUNC_FMC_SDCKE1>,\n+\t\t\t\t\t\t <STM32H7_PH8_FUNC_FMC_D16>,\n+\t\t\t\t\t\t <STM32H7_PH9_FUNC_FMC_D17>,\n+\t\t\t\t\t\t <STM32H7_PH10_FUNC_FMC_D18>,\n+\t\t\t\t\t\t <STM32H7_PH11_FUNC_FMC_D19>,\n+\t\t\t\t\t\t <STM32H7_PH12_FUNC_FMC_D20>,\n+\t\t\t\t\t\t <STM32H7_PH13_FUNC_FMC_D21>,\n+\t\t\t\t\t\t <STM32H7_PH14_FUNC_FMC_D22>,\n+\t\t\t\t\t\t <STM32H7_PH15_FUNC_FMC_D23>,\n+\n+\t\t\t\t\t\t <STM32H7_PI0_FUNC_FMC_D24>,\n+\t\t\t\t\t\t <STM32H7_PI1_FUNC_FMC_D25>,\n+\t\t\t\t\t\t <STM32H7_PI2_FUNC_FMC_D26>,\n+\t\t\t\t\t\t <STM32H7_PI3_FUNC_FMC_D27>,\n+\t\t\t\t\t\t <STM32H7_PI4_FUNC_FMC_NBL2>,\n+\t\t\t\t\t\t <STM32H7_PI5_FUNC_FMC_NBL3>,\n+\t\t\t\t\t\t <STM32H7_PI6_FUNC_FMC_D28>,\n+\t\t\t\t\t\t <STM32H7_PI7_FUNC_FMC_D29>,\n+\t\t\t\t\t\t <STM32H7_PI9_FUNC_FMC_D30>,\n+\t\t\t\t\t\t <STM32H7_PI10_FUNC_FMC_D31>;\n+\n+\t\t\t\t\t slew-rate = <3>;\n+\t\t\t\t};\n+\t\t\t};\n \t\t};\n \t};\n };\ndiff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi\nindex 36a99db..16e9308 100644\n--- a/arch/arm/dts/stm32h743.dtsi\n+++ b/arch/arm/dts/stm32h743.dtsi\n@@ -42,45 +42,83 @@\n \n #include \"skeleton.dtsi\"\n #include \"armv7-m.dtsi\"\n+#include <dt-bindings/clock/stm32h7-clks.h>\n \n / {\n \tclocks {\n \t\tclk_hse: clk-hse {\n \t\t\t#clock-cells = <0>;\n \t\t\tcompatible = \"fixed-clock\";\n-\t\t\tclock-frequency = <0>;\n+\t\t\tclock-frequency = <25000000>;\n+\t\t};\n+\n+\t\tclk_lse: clk-lse {\n+\t\t\t#clock-cells = <0>;\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\tclock-frequency = <32768>;\n \t\t};\n \n-\t\ttimer_clk: timer-clk {\n+\t\tclk_i2s: i2s_ckin {\n \t\t\t#clock-cells = <0>;\n \t\t\tcompatible = \"fixed-clock\";\n-\t\t\tclock-frequency = <125000000>;\n+\t\t\tclock-frequency = <0>;\n \t\t};\n \t};\n \n \tsoc {\n+\t\trcc: rcc@58024400 {\n+\t\t\t#clock-cells = <1>;\n+\t\t\t#reset-cells = <1>;\n+\t\t\tcompatible = \"st,stm32h743-rcc\", \"st,stm32-rcc\";\n+\t\t\treg = <0x58024400 0x400>;\n+\t\t\tclocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>, <&clk_hsi>, <&clk_csi>;\n+\t\t\tst,syscfg = <&pwrcfg>;\n+\t\t};\n+\n \t\tusart1: serial@40011000 {\n-\t\t\tcompatible = \"st,stm32f7-usart\", \"st,stm32f7-uart\";\n+\t\t\tcompatible = \"st,stm32h7-usart\", \"st,stm32h7-uart\";\n \t\t\treg = <0x40011000 0x400>;\n \t\t\tinterrupts = <37>;\n \t\t\tstatus = \"disabled\";\n-\t\t\tclocks = <&timer_clk>;\n-\n+\t\t\tclocks = <&rcc USART1_CK>;\n \t\t};\n \n \t\tusart2: serial@40004400 {\n-\t\t\tcompatible = \"st,stm32f7-usart\", \"st,stm32f7-uart\";\n+\t\t\tcompatible = \"st,stm32h7-usart\", \"st,stm32h7-uart\";\n \t\t\treg = <0x40004400 0x400>;\n \t\t\tinterrupts = <38>;\n \t\t\tstatus = \"disabled\";\n-\t\t\tclocks = <&timer_clk>;\n+\t\t\tclocks = <&rcc USART2_CK>;\n \t\t};\n \n \t\ttimer5: timer@40000c00 {\n \t\t\tcompatible = \"st,stm32-timer\";\n \t\t\treg = <0x40000c00 0x400>;\n \t\t\tinterrupts = <50>;\n-\t\t\tclocks = <&timer_clk>;\n+\t\t\tclocks = <&rcc TIM5_CK>;\n+\t\t};\n+\n+\t\tpwrcfg: power-config@58024800 {\n+\t\t\tcompatible = \"syscon\";\n+\t\t\treg = <0x58024800 0x400>;\n+\t\t};\n+\n+\t\tfmc: fmc@52004000 {\n+\t\t\tcompatible = \"st,stm32h7-fmc\";\n+\t\t\treg = <0x52004000 0x1000>;\n+\t\t\tclocks = <&rcc FMC_CK>;\n+\t\t};\n+\n+\t\tclk_hsi: clk-hsi {\n+\t\t\t#clock-cells = <0>;\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\tclock-frequency = <64000000>;\n+\t\t};\n+\n+\t\tclk_csi: clk-csi {\n+\t\t\t#clock-cells = <0>;\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\tclock-frequency = <4000000>;\n \t\t};\n \t};\n };\ndiff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts\nindex 79e841d..bef7e90 100644\n--- a/arch/arm/dts/stm32h743i-disco.dts\n+++ b/arch/arm/dts/stm32h743i-disco.dts\n@@ -43,6 +43,7 @@\n /dts-v1/;\n #include \"stm32h743.dtsi\"\n #include \"stm32h743-pinctrl.dtsi\"\n+#include <dt-bindings/memory/stm32-sdram.h>\n \n / {\n \tmodel = \"STMicroelectronics STM32H743i-Discovery board\";\n@@ -59,15 +60,41 @@\n \n \taliases {\n \t\tserial0 = &usart2;\n+\t\tgpio0 = &gpioa;\n+\t\tgpio1 = &gpiob;\n+\t\tgpio2 = &gpioc;\n+\t\tgpio3 = &gpiod;\n+\t\tgpio4 = &gpioe;\n+\t\tgpio5 = &gpiof;\n+\t\tgpio6 = &gpiog;\n+\t\tgpio7 = &gpioh;\n+\t\tgpio8 = &gpioi;\n+\t\tgpio9 = &gpioj;\n+\t\tgpio10 = &gpiok;\n \t};\n };\n \n-&clk_hse {\n-\tclock-frequency = <125000000>;\n-};\n-\n &usart2 {\n \tpinctrl-0 = <&usart2_pins>;\n \tpinctrl-names = \"default\";\n \tstatus = \"okay\";\n };\n+\n+&fmc {\n+\tpinctrl-0 = <&fmc_pins>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+\n+\t/*\n+\t * Memory configuration from sdram datasheet IS42S32800G-6BLI\n+\t * firsct bank is bank@0\n+\t * second bank is bank@1\n+\t */\n+\tbank1: bank@1 {\n+\t\tst,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4\n+\t\t\t\t CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;\n+\t\tst,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2\n+\t\t\t\t TWR_1 TRCD_1>;\n+\t\tst,sdram-refcount = <1539>;\n+\t};\n+};\ndiff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts\nindex c6effbb..0e01ce5 100644\n--- a/arch/arm/dts/stm32h743i-eval.dts\n+++ b/arch/arm/dts/stm32h743i-eval.dts\n@@ -43,6 +43,7 @@\n /dts-v1/;\n #include \"stm32h743.dtsi\"\n #include \"stm32h743-pinctrl.dtsi\"\n+#include <dt-bindings/memory/stm32-sdram.h>\n \n / {\n \tmodel = \"STMicroelectronics STM32H743i-EVAL board\";\n@@ -59,16 +60,41 @@\n \n \taliases {\n \t\tserial0 = &usart1;\n+\t\tgpio0 = &gpioa;\n+\t\tgpio1 = &gpiob;\n+\t\tgpio2 = &gpioc;\n+\t\tgpio3 = &gpiod;\n+\t\tgpio4 = &gpioe;\n+\t\tgpio5 = &gpiof;\n+\t\tgpio6 = &gpiog;\n+\t\tgpio7 = &gpioh;\n+\t\tgpio8 = &gpioi;\n+\t\tgpio9 = &gpioj;\n+\t\tgpio10 = &gpiok;\n \t};\n };\n \n-&clk_hse {\n-\tclock-frequency = <125000000>;\n-};\n-\n &usart1 {\n \tpinctrl-0 = <&usart1_pins>;\n \tpinctrl-names = \"default\";\n \tstatus = \"okay\";\n };\n \n+&fmc {\n+\tpinctrl-0 = <&fmc_pins>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+\n+\t/*\n+\t * Memory configuration from sdram datasheet IS42S32800G-6BLI\n+\t * firsct bank is bank@0\n+\t * second bank is bank@1\n+\t */\n+\tbank2: bank@1 {\n+\t\tst,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4\n+\t\t\t\t CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;\n+\t\tst,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2\n+\t\t\t\t TWR_1 TRCD_1>;\n+\t\tst,sdram-refcount = <1539>;\n+\t};\n+};\ndiff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h\nindex 89b719a..c2b911f 100644\n--- a/include/dt-bindings/memory/stm32-sdram.h\n+++ b/include/dt-bindings/memory/stm32-sdram.h\n@@ -18,7 +18,9 @@\n #define CAS_1\t\t0x1\n #define CAS_2\t\t0x2\n #define CAS_3\t\t0x3\n+#define SDCLK_DIS\t0x0\n #define SDCLK_2\t\t0x2\n+#define SDCLK_3\t\t0x3\n #define RD_BURST_EN\t0x1\n #define RD_BURST_DIS\t0x0\n #define RD_PIPE_DL_0\t0x0\n@@ -26,12 +28,17 @@\n #define RD_PIPE_DL_2\t0x2\n \n /* Timing = value +1 cycles */\n+#define TMRD_1\t\t(1 - 1)\n #define TMRD_2\t\t(2 - 1)\n+#define TXSR_1\t\t(1 - 1)\n #define TXSR_6\t\t(6 - 1)\n+#define TRAS_1\t\t(1 - 1)\n #define TRAS_4\t\t(4 - 1)\n #define TRC_6\t\t(6 - 1)\n+#define TWR_1\t\t(1 - 1)\n #define TWR_2\t\t(2 - 1)\n #define TRP_2\t\t(2 - 1)\n+#define TRCD_1\t\t(1 - 1)\n #define TRCD_2\t\t(2 - 1)\n \n #endif\n", "prefixes": [ "U-Boot", "v2", "8/9" ] }