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GET /api/patches/813504/?format=api
{ "id": 813504, "url": "http://patchwork.ozlabs.org/api/patches/813504/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505318412-27121-6-git-send-email-patrice.chotard@st.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505318412-27121-6-git-send-email-patrice.chotard@st.com>", "list_archive_url": null, "date": "2017-09-13T16:00:08", "name": "[U-Boot,v2,5/9] dm: misc: add stm32 rcc driver", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "7a8a0c833095c282dd1322c8c63f364fd39bffad", "submitter": { "id": 63958, "url": "http://patchwork.ozlabs.org/api/people/63958/?format=api", "name": "Patrice CHOTARD", "email": "patrice.chotard@st.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505318412-27121-6-git-send-email-patrice.chotard@st.com/mbox/", "series": [ { "id": 2943, "url": "http://patchwork.ozlabs.org/api/series/2943/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=2943", "date": "2017-09-13T16:00:03", "name": "Add STM32H7 SoC, Discovery and Evaluation board support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2943/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813504/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813504/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsmjN5Hpkz9sNw\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 14 Sep 2017 02:05:44 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 6D628C22255; Wed, 13 Sep 2017 16:03:18 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id CE210C2261B;\n\tWed, 13 Sep 2017 16:00:38 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 7AC26C22466; Wed, 13 Sep 2017 16:00:27 +0000 (UTC)", "from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com\n\t[91.207.212.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 82A4DC223E4\n\tfor <u-boot@lists.denx.de>; Wed, 13 Sep 2017 16:00:22 +0000 (UTC)", "from pps.filterd (m0046661.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8DFwjAh018007; Wed, 13 Sep 2017 18:00:21 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2cy58vgvv1-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tWed, 13 Sep 2017 18:00:21 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E2F6D31;\n\tWed, 13 Sep 2017 16:00:20 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 721602B31;\n\tWed, 13 Sep 2017 16:00:20 +0000 (GMT)", "from localhost (10.75.127.44) by SFHDAG6NODE3.st.com (10.75.127.18)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tWed, 13 Sep 2017 18:00:20 +0200" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "From": "<patrice.chotard@st.com>", "To": "<u-boot@lists.denx.de>, <albert.u.boot@aribaud.net>, <sjg@chromium.org>, \n\t<vikas.manocha@st.com>", "Date": "Wed, 13 Sep 2017 18:00:08 +0200", "Message-ID": "<1505318412-27121-6-git-send-email-patrice.chotard@st.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1505318412-27121-1-git-send-email-patrice.chotard@st.com>", "References": "<1505318412-27121-1-git-send-email-patrice.chotard@st.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.75.127.44]", "X-ClientProxiedBy": "SFHDAG8NODE2.st.com (10.75.127.23) To SFHDAG6NODE3.st.com\n\t(10.75.127.18)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-13_04:, , signatures=0", "Subject": "[U-Boot] [PATCH v2 5/9] dm: misc: add stm32 rcc driver", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Christophe Kerello <christophe.kerello@st.com>\n\nThis patch adds the support of reset and clock control\nblock (rcc) found on STM32 SoCs.\nThis driver is similar to a MFD linux driver.\n\nThis driver supports currently STM32H7 only.\nSTM32F4 and STM32F7 will be migrated to this rcc MFD driver\nin the future to uniformize all STM32 SoCs already upstreamed.\n\nSigned-off-by: Christophe Kerello <christophe.kerello@st.com>\nSigned-off-by: Patrice Chotard <patrice.chotard@st.com>\nReviewed-by: Vikas Manocha <vikas.manocha@st.com>\n---\n\nv2: _ merge peripheral and kernel clocks arrays\n\t_ add voltage scaling support needed for Evaluation board\n\n drivers/misc/Kconfig | 9 +++++++++\n drivers/misc/Makefile | 1 +\n drivers/misc/stm32_rcc.c | 45 +++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 55 insertions(+)\n create mode 100644 drivers/misc/stm32_rcc.c", "diff": "diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig\nindex 4133017..f1c15cb 100644\n--- a/drivers/misc/Kconfig\n+++ b/drivers/misc/Kconfig\n@@ -158,6 +158,15 @@ config PCA9551_I2C_ADDR\n \thelp\n \t The I2C address of the PCA9551 LED controller.\n \n+config STM32_RCC\n+\tbool \"Enable RCC driver for the STM32 SoC's family\"\n+\tdepends on STM32 && MISC\n+\thelp\n+\t Enable the STM32 RCC driver. The RCC block (Reset and Clock Control\n+\t block) is responsible of the management of the clock and reset\n+\t generation.\n+\t This driver is similar to an MFD driver in the Linux kernel.\n+\n config TEGRA_CAR\n \tbool \"Enable support for the Tegra CAR driver\"\n \tdepends on TEGRA_NO_BPMP\ndiff --git a/drivers/misc/Makefile b/drivers/misc/Makefile\nindex 21f7e6c..ada7624 100644\n--- a/drivers/misc/Makefile\n+++ b/drivers/misc/Makefile\n@@ -52,3 +52,4 @@ obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o\n obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o\n obj-$(CONFIG_QFW) += qfw.o\n obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o\n+obj-$(CONFIG_STM32_RCC) += stm32_rcc.o\ndiff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c\nnew file mode 100644\nindex 0000000..a6c2a75\n--- /dev/null\n+++ b/drivers/misc/stm32_rcc.c\n@@ -0,0 +1,45 @@\n+/*\n+ * Copyright (C) STMicroelectronics SA 2017\n+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <misc.h>\n+#include <dm/lists.h>\n+\n+static int stm32_rcc_bind(struct udevice *dev)\n+{\n+\tint ret;\n+\tstruct udevice *child;\n+\n+\tdebug(\"%s(dev=%p)\\n\", __func__, dev);\n+\n+\tret = device_bind_driver_to_node(dev, \"stm32h7_rcc_clock\",\n+\t\t\t\t\t \"stm32h7_rcc_clock\",\n+\t\t\t\t\t dev_ofnode(dev), &child);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn device_bind_driver_to_node(dev, \"stm32_rcc_reset\",\n+\t\t\t\t\t \"stm32_rcc_reset\",\n+\t\t\t\t\t dev_ofnode(dev), &child);\n+}\n+\n+static const struct misc_ops stm32_rcc_ops = {\n+};\n+\n+static const struct udevice_id stm32_rcc_ids[] = {\n+\t{.compatible = \"st,stm32h743-rcc\"},\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(stm32_rcc) = {\n+\t.name\t\t= \"stm32-rcc\",\n+\t.id\t\t= UCLASS_MISC,\n+\t.of_match\t= stm32_rcc_ids,\n+\t.bind\t\t= stm32_rcc_bind,\n+\t.ops\t\t= &stm32_rcc_ops,\n+};\n", "prefixes": [ "U-Boot", "v2", "5/9" ] }