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GET /api/patches/813499/?format=api
{ "id": 813499, "url": "http://patchwork.ozlabs.org/api/patches/813499/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505318412-27121-5-git-send-email-patrice.chotard@st.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505318412-27121-5-git-send-email-patrice.chotard@st.com>", "list_archive_url": null, "date": "2017-09-13T16:00:07", "name": "[U-Boot,v2,4/9] dm: reset: add stm32 reset driver", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "7afbf5444ab662257309e3b350c2767d3dedaaf7", "submitter": { "id": 63958, "url": "http://patchwork.ozlabs.org/api/people/63958/?format=api", "name": "Patrice CHOTARD", "email": "patrice.chotard@st.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505318412-27121-5-git-send-email-patrice.chotard@st.com/mbox/", "series": [ { "id": 2943, "url": "http://patchwork.ozlabs.org/api/series/2943/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=2943", "date": "2017-09-13T16:00:03", "name": "Add STM32H7 SoC, Discovery and Evaluation board support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2943/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813499/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813499/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsmg31n8Xz9sBW\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 14 Sep 2017 02:03:43 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 0565BC225AF; Wed, 13 Sep 2017 16:02:27 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id B521EC2256F;\n\tWed, 13 Sep 2017 16:00:29 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 59689C2259F; Wed, 13 Sep 2017 16:00:23 +0000 (UTC)", "from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com\n\t[91.207.212.93])\n\tby lists.denx.de (Postfix) with ESMTPS id A1057C220AA\n\tfor <u-boot@lists.denx.de>; Wed, 13 Sep 2017 16:00:21 +0000 (UTC)", "from pps.filterd (m0046661.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8DFwjAg018007; Wed, 13 Sep 2017 18:00:20 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2cy58vgvuw-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tWed, 13 Sep 2017 18:00:20 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 018AF34;\n\tWed, 13 Sep 2017 16:00:19 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CBE522B31;\n\tWed, 13 Sep 2017 16:00:19 +0000 (GMT)", "from localhost (10.75.127.49) by SFHDAG6NODE3.st.com (10.75.127.18)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tWed, 13 Sep 2017 18:00:19 +0200" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "From": "<patrice.chotard@st.com>", "To": "<u-boot@lists.denx.de>, <albert.u.boot@aribaud.net>, <sjg@chromium.org>, \n\t<vikas.manocha@st.com>", "Date": "Wed, 13 Sep 2017 18:00:07 +0200", "Message-ID": "<1505318412-27121-5-git-send-email-patrice.chotard@st.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1505318412-27121-1-git-send-email-patrice.chotard@st.com>", "References": "<1505318412-27121-1-git-send-email-patrice.chotard@st.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.75.127.49]", "X-ClientProxiedBy": "SFHDAG1NODE2.st.com (10.75.127.2) To SFHDAG6NODE3.st.com\n\t(10.75.127.18)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-13_04:, , signatures=0", "Subject": "[U-Boot] [PATCH v2 4/9] dm: reset: add stm32 reset driver", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Patrice Chotard <patrice.chotard@st.com>\n\nThis driver is adapted from linux drivers/reset/reset-stm32.c\nIt's compatible with STM32 F4/F7/H7 SoCs.\n\nThis driver doesn't implement .of_match as it's binded\nby MFD RCC driver.\n\nTo add support for each SoC family, a SoC's specific\ninclude/dt-binfings/mfd/stm32xx-rcc.h file must be added.\n\nThis patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs.\nOther SoCs support will be added in the future.\n\nSigned-off-by: Patrice Chotard <patrice.chotard@st.com>\n---\n doc/device-tree-bindings/reset/st,stm32-rcc.txt | 6 ++\n drivers/reset/Kconfig | 7 ++\n drivers/reset/Makefile | 1 +\n drivers/reset/stm32-reset.c | 80 ++++++++++++++\n include/dt-bindings/mfd/stm32h7-rcc.h | 138 ++++++++++++++++++++++++\n 5 files changed, 232 insertions(+)\n create mode 100644 doc/device-tree-bindings/reset/st,stm32-rcc.txt\n create mode 100644 drivers/reset/stm32-reset.c\n create mode 100644 include/dt-bindings/mfd/stm32h7-rcc.h", "diff": "diff --git a/doc/device-tree-bindings/reset/st,stm32-rcc.txt b/doc/device-tree-bindings/reset/st,stm32-rcc.txt\nnew file mode 100644\nindex 0000000..01db343\n--- /dev/null\n+++ b/doc/device-tree-bindings/reset/st,stm32-rcc.txt\n@@ -0,0 +1,6 @@\n+STMicroelectronics STM32 Peripheral Reset Controller\n+====================================================\n+\n+The RCC IP is both a reset and a clock controller.\n+\n+Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt\ndiff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig\nindex e6af7da..ce46e27 100644\n--- a/drivers/reset/Kconfig\n+++ b/drivers/reset/Kconfig\n@@ -28,6 +28,13 @@ config STI_RESET\n \t Say Y if you want to control reset signals provided by system config\n \t block.\n \n+config STM32_RESET\n+\tbool \"Enable the STM32 reset\"\n+\tdepends on STM32\n+\thelp\n+\t Support for reset controllers on STMicroelectronics STM32 family SoCs.\n+\t This resset driver is compatible with STM32 F4/F7 and H7 SoCs.\n+\n config TEGRA_CAR_RESET\n \tbool \"Enable Tegra CAR-based reset driver\"\n \tdepends on TEGRA_CAR\ndiff --git a/drivers/reset/Makefile b/drivers/reset/Makefile\nindex d5e06c2..252cefe 100644\n--- a/drivers/reset/Makefile\n+++ b/drivers/reset/Makefile\n@@ -6,6 +6,7 @@ obj-$(CONFIG_DM_RESET) += reset-uclass.o\n obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o\n obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o\n obj-$(CONFIG_STI_RESET) += sti-reset.o\n+obj-$(CONFIG_STM32_RESET) += stm32-reset.o\n obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o\n obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o\n obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o\ndiff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c\nnew file mode 100644\nindex 0000000..9c627d8\n--- /dev/null\n+++ b/drivers/reset/stm32-reset.c\n@@ -0,0 +1,80 @@\n+/*\n+ * Copyright (C) STMicroelectronics SA 2017\n+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <errno.h>\n+#include <reset-uclass.h>\n+#include <asm/io.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+struct stm32_reset_priv {\n+\tfdt_addr_t base;\n+};\n+\n+static int stm32_reset_request(struct reset_ctl *reset_ctl)\n+{\n+\treturn 0;\n+}\n+\n+static int stm32_reset_free(struct reset_ctl *reset_ctl)\n+{\n+\treturn 0;\n+}\n+\n+static int stm32_reset_assert(struct reset_ctl *reset_ctl)\n+{\n+\tstruct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);\n+\tint bank = (reset_ctl->id / BITS_PER_LONG) * 4;\n+\tint offset = reset_ctl->id % BITS_PER_LONG;\n+\tdebug(\"%s: reset id = %ld bank = %d offset = %d)\\n\", __func__,\n+\t reset_ctl->id, bank, offset);\n+\n+\tsetbits_le32(priv->base + bank, BIT(offset));\n+\n+\treturn 0;\n+}\n+\n+static int stm32_reset_deassert(struct reset_ctl *reset_ctl)\n+{\n+\tstruct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);\n+\tint bank = (reset_ctl->id / BITS_PER_LONG) * 4;\n+\tint offset = reset_ctl->id % BITS_PER_LONG;\n+\tdebug(\"%s: reset id = %ld bank = %d offset = %d)\\n\", __func__,\n+\t reset_ctl->id, bank, offset);\n+\n+\tclrbits_le32(priv->base + bank, BIT(offset));\n+\n+\treturn 0;\n+}\n+\n+static const struct reset_ops stm32_reset_ops = {\n+\t.request\t= stm32_reset_request,\n+\t.free\t\t= stm32_reset_free,\n+\t.rst_assert\t= stm32_reset_assert,\n+\t.rst_deassert\t= stm32_reset_deassert,\n+};\n+\n+static int stm32_reset_probe(struct udevice *dev)\n+{\n+\tstruct stm32_reset_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->base = devfdt_get_addr(dev);\n+\tif (priv->base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_DRIVER(stm32_rcc_reset) = {\n+\t.name\t\t\t= \"stm32_rcc_reset\",\n+\t.id\t\t\t= UCLASS_RESET,\n+\t.probe\t\t\t= stm32_reset_probe,\n+\t.priv_auto_alloc_size\t= sizeof(struct stm32_reset_priv),\n+\t.ops\t\t\t= &stm32_reset_ops,\n+};\ndiff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h\nnew file mode 100644\nindex 0000000..b96b3c3\n--- /dev/null\n+++ b/include/dt-bindings/mfd/stm32h7-rcc.h\n@@ -0,0 +1,138 @@\n+/*\n+ * This header provides constants for the STM32H7 RCC IP\n+ */\n+\n+#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H\n+#define _DT_BINDINGS_MFD_STM32H7_RCC_H\n+\n+/* AHB3 */\n+#define STM32H7_RCC_AHB3_MDMA\t\t0\n+#define STM32H7_RCC_AHB3_DMA2D\t\t4\n+#define STM32H7_RCC_AHB3_JPGDEC\t\t5\n+#define STM32H7_RCC_AHB3_FMC\t\t12\n+#define STM32H7_RCC_AHB3_QUADSPI\t14\n+#define STM32H7_RCC_AHB3_SDMMC1\t\t16\n+#define STM32H7_RCC_AHB3_CPU1\t\t31\n+\n+#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))\n+\n+/* AHB1 */\n+#define STM32H7_RCC_AHB1_DMA1\t\t0\n+#define STM32H7_RCC_AHB1_DMA2\t\t1\n+#define STM32H7_RCC_AHB1_ADC12\t\t5\n+#define STM32H7_RCC_AHB1_ART\t\t14\n+#define STM32H7_RCC_AHB1_ETH1MAC\t15\n+#define STM32H7_RCC_AHB1_USB1OTG\t25\n+#define STM32H7_RCC_AHB1_USB2OTG\t27\n+#define STM32H7_RCC_AHB1_CPU2\t\t31\n+\n+#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))\n+\n+/* AHB2 */\n+#define STM32H7_RCC_AHB2_CAMITF\t\t0\n+#define STM32H7_RCC_AHB2_CRYPT\t\t4\n+#define STM32H7_RCC_AHB2_HASH\t\t5\n+#define STM32H7_RCC_AHB2_RNG\t\t6\n+#define STM32H7_RCC_AHB2_SDMMC2\t\t9\n+\n+#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))\n+\n+/* AHB4 */\n+#define STM32H7_RCC_AHB4_GPIOA\t\t0\n+#define STM32H7_RCC_AHB4_GPIOB\t\t1\n+#define STM32H7_RCC_AHB4_GPIOC\t\t2\n+#define STM32H7_RCC_AHB4_GPIOD\t\t3\n+#define STM32H7_RCC_AHB4_GPIOE\t\t4\n+#define STM32H7_RCC_AHB4_GPIOF\t\t5\n+#define STM32H7_RCC_AHB4_GPIOG\t\t6\n+#define STM32H7_RCC_AHB4_GPIOH\t\t7\n+#define STM32H7_RCC_AHB4_GPIOI\t\t8\n+#define STM32H7_RCC_AHB4_GPIOJ\t\t9\n+#define STM32H7_RCC_AHB4_GPIOK\t\t10\n+#define STM32H7_RCC_AHB4_CRC\t\t19\n+#define STM32H7_RCC_AHB4_BDMA\t\t21\n+#define STM32H7_RCC_AHB4_ADC3\t\t24\n+#define STM32H7_RCC_AHB4_HSEM\t\t25\n+\n+#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))\n+\n+\n+/* APB3 */\n+#define STM32H7_RCC_APB3_LTDC\t\t3\n+#define STM32H7_RCC_APB3_DSI\t\t4\n+\n+#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))\n+\n+/* APB1L */\n+#define STM32H7_RCC_APB1L_TIM2\t\t0\n+#define STM32H7_RCC_APB1L_TIM3\t\t1\n+#define STM32H7_RCC_APB1L_TIM4\t\t2\n+#define STM32H7_RCC_APB1L_TIM5\t\t3\n+#define STM32H7_RCC_APB1L_TIM6\t\t4\n+#define STM32H7_RCC_APB1L_TIM7\t\t5\n+#define STM32H7_RCC_APB1L_TIM12\t\t6\n+#define STM32H7_RCC_APB1L_TIM13\t\t7\n+#define STM32H7_RCC_APB1L_TIM14\t\t8\n+#define STM32H7_RCC_APB1L_LPTIM1\t9\n+#define STM32H7_RCC_APB1L_SPI2\t\t14\n+#define STM32H7_RCC_APB1L_SPI3\t\t15\n+#define STM32H7_RCC_APB1L_SPDIF_RX\t16\n+#define STM32H7_RCC_APB1L_USART2\t17\n+#define STM32H7_RCC_APB1L_USART3\t18\n+#define STM32H7_RCC_APB1L_UART4\t\t19\n+#define STM32H7_RCC_APB1L_UART5\t\t20\n+#define STM32H7_RCC_APB1L_I2C1\t\t21\n+#define STM32H7_RCC_APB1L_I2C2\t\t22\n+#define STM32H7_RCC_APB1L_I2C3\t\t23\n+#define STM32H7_RCC_APB1L_HDMICEC\t27\n+#define STM32H7_RCC_APB1L_DAC12\t\t29\n+#define STM32H7_RCC_APB1L_USART7\t30\n+#define STM32H7_RCC_APB1L_USART8\t31\n+\n+#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))\n+\n+/* APB1H */\n+#define STM32H7_RCC_APB1H_CRS\t\t1\n+#define STM32H7_RCC_APB1H_SWP\t\t2\n+#define STM32H7_RCC_APB1H_OPAMP\t\t4\n+#define STM32H7_RCC_APB1H_MDIOS\t\t5\n+#define STM32H7_RCC_APB1H_FDCAN\t\t8\n+\n+#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))\n+\n+/* APB2 */\n+#define STM32H7_RCC_APB2_TIM1\t\t0\n+#define STM32H7_RCC_APB2_TIM8\t\t1\n+#define STM32H7_RCC_APB2_USART1\t\t4\n+#define STM32H7_RCC_APB2_USART6\t\t5\n+#define STM32H7_RCC_APB2_SPI1\t\t12\n+#define STM32H7_RCC_APB2_SPI4\t\t13\n+#define STM32H7_RCC_APB2_TIM15\t\t16\n+#define STM32H7_RCC_APB2_TIM16\t\t17\n+#define STM32H7_RCC_APB2_TIM17\t\t18\n+#define STM32H7_RCC_APB2_SPI5\t\t20\n+#define STM32H7_RCC_APB2_SAI1\t\t22\n+#define STM32H7_RCC_APB2_SAI2\t\t23\n+#define STM32H7_RCC_APB2_SAI3\t\t24\n+#define STM32H7_RCC_APB2_DFSDM1\t\t28\n+#define STM32H7_RCC_APB2_HRTIM\t\t29\n+\n+#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))\n+\n+/* APB4 */\n+#define STM32H7_RCC_APB4_SYSCFG\t\t1\n+#define STM32H7_RCC_APB4_LPUART1\t3\n+#define STM32H7_RCC_APB4_SPI6\t\t5\n+#define STM32H7_RCC_APB4_I2C4\t\t7\n+#define STM32H7_RCC_APB4_LPTIM2\t\t9\n+#define STM32H7_RCC_APB4_LPTIM3\t\t10\n+#define STM32H7_RCC_APB4_LPTIM4\t\t11\n+#define STM32H7_RCC_APB4_LPTIM5\t\t12\n+#define STM32H7_RCC_APB4_COMP12\t\t14\n+#define STM32H7_RCC_APB4_VREF\t\t15\n+#define STM32H7_RCC_APB4_SAI4\t\t21\n+#define STM32H7_RCC_APB4_TMPSENS\t26\n+\n+#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))\n+\n+#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */\n", "prefixes": [ "U-Boot", "v2", "4/9" ] }