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GET /api/patches/813249/?format=api
{ "id": 813249, "url": "http://patchwork.ozlabs.org/api/patches/813249/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170913090522.4022-11-Sergio.G.DelReal@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170913090522.4022-11-Sergio.G.DelReal@gmail.com>", "list_archive_url": null, "date": "2017-09-13T09:05:18", "name": "[v4,10/14] hvf: implement hvf_get_supported_cpuid", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2ded40ea4c564b4f81b954bf9cf9d064c3b32b27", "submitter": { "id": 70675, "url": "http://patchwork.ozlabs.org/api/people/70675/?format=api", "name": "Sergio Andres Gomez Del Real", "email": "sergio.g.delreal@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170913090522.4022-11-Sergio.G.DelReal@gmail.com/mbox/", "series": [ { "id": 2843, "url": "http://patchwork.ozlabs.org/api/series/2843/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2843", "date": "2017-09-13T09:05:08", "name": "add support for Hypervisor.framework in QEMU", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/2843/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813249/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813249/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"sNfI63Yk\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsbfW1YGpz9sPs\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 19:17:39 +1000 (AEST)", "from localhost ([::1]:41115 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1ds3nd-0004wW-7L\n\tfor incoming@patchwork.ozlabs.org; Wed, 13 Sep 2017 05:17:37 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:34088)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <sergio.g.delreal@gmail.com>) id 1ds3cP-0001Xi-NM\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 05:06:03 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <sergio.g.delreal@gmail.com>) id 1ds3cO-0007Y1-83\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 05:06:01 -0400", "from mail-vk0-x241.google.com ([2607:f8b0:400c:c05::241]:36912)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <sergio.g.delreal@gmail.com>)\n\tid 1ds3cO-0007XY-29\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 05:06:00 -0400", "by mail-vk0-x241.google.com with SMTP id 184so3319681vkn.4\n\tfor <qemu-devel@nongnu.org>; Wed, 13 Sep 2017 02:05:59 -0700 (PDT)", "from localhost.localdomain ([190.66.154.128])\n\tby smtp.gmail.com with ESMTPSA id\n\tr74sm2677601vkf.19.2017.09.13.02.05.58\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 13 Sep 2017 02:05:58 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=qgJBrhC4zESVMibV0b+BdWWddxQ3EtxOF+dZXwz6rbU=;\n\tb=sNfI63YkdSzUrbfppTyg0VNqSF/SobgLkLiX4Oow9z6BxVmngOMFL7s9QOH9Fqpssy\n\tYXM94rpJ5/nv/VS/8wmAqcoWrv2PjMvydNzoa2Y41N5di0ik0W8jgTfAEbc1543XmN/W\n\tTtUByn5HbdBSYPTLjKVBoh032NV6i5SIFcvf3a1H2g6elOU2bx2E4c32Qps1KcGOdjEJ\n\tM2mS6xCF59GGVutl/lzsK38iCsximdcnT8KyOYEUmKjXbU2+TZpadXh3HjLARVLldXgI\n\t3H0azjNYU1zEeztRG3QOqI1/IzXVmOE582lbuihKEXSS6RnUkRhrXt7md6HKWGKiMHYp\n\t65BQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=qgJBrhC4zESVMibV0b+BdWWddxQ3EtxOF+dZXwz6rbU=;\n\tb=Rj6VMRVwznARgU3PaPBJN/ZGCRktYPlWo9/i7Pt3pNQrr8AvhS7lh6uAGsR5ffeWG8\n\tD0XyeJpWsNliZ/ixEEkKsGpiXL5SQHXsIVzDobK2GAjP0DmU2LM3bY/f1meRQ26ESX9L\n\tksJntlGKBRLGlZwul1JwYQ63+LrSnHuT5/ds3pk8Y9I77FlognidH4j6HFiad+Tr0Mk2\n\tr+oyNgNaoqDWN4BGk0Ol1qwaQx+e9jWC2RKEhhBpStissw4QaQcWLWwCoX5b26XOC9Qh\n\tk9JBY+YuBiMHNidYujj2H0vUyj6pKqv1+4e/tdj+T6zLGRvGsYPPWkkz2D2PxUq74ACa\n\t/ikg==", "X-Gm-Message-State": "AHPjjUg3pYnQHZZ614eLXmZ4hN3dWW1YjyAJ2DcSBtdXE0ucSMs2GngT\n\tPhj0cyt1pPox5Zv9", "X-Google-Smtp-Source": "AOwi7QB+7OWxbS8eA8cUfNWUque8dRJEVOqt6nvxWptANJ8aeLIl0GjyeJ2CNHQxrXs73mYoK1hckQ==", "X-Received": "by 10.31.109.195 with SMTP id\n\ti186mr13083607vkc.118.1505293559274; \n\tWed, 13 Sep 2017 02:05:59 -0700 (PDT)", "From": "Sergio Andres Gomez Del Real <sergio.g.delreal@gmail.com>", "X-Google-Original-From": "Sergio Andres Gomez Del Real\n\t<Sergio.G.DelReal@gmail.com>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 13 Sep 2017 04:05:18 -0500", "Message-Id": "<20170913090522.4022-11-Sergio.G.DelReal@gmail.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170913090522.4022-1-Sergio.G.DelReal@gmail.com>", "References": "<20170913090522.4022-1-Sergio.G.DelReal@gmail.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400c:c05::241", "Subject": "[Qemu-devel] [PATCH v4 10/14] hvf: implement hvf_get_supported_cpuid", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>,\n\tpbonzini@redhat.com, stefanha@gmail.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "This patch implements hvf_get_supported_cpuid, which returns the set of\nfeatures supported by both the host processor and the hypervisor.\n\nSigned-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>\n---\n target/i386/hvf-utils/x86_cpuid.c | 138 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 138 insertions(+)", "diff": "diff --git a/target/i386/hvf-utils/x86_cpuid.c b/target/i386/hvf-utils/x86_cpuid.c\nindex fe968cb638..0646588ae3 100644\n--- a/target/i386/hvf-utils/x86_cpuid.c\n+++ b/target/i386/hvf-utils/x86_cpuid.c\n@@ -24,6 +24,7 @@\n #include \"x86_cpuid.h\"\n #include \"x86.h\"\n #include \"vmx.h\"\n+#include \"sysemu/hvf.h\"\n \n #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \\\n CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \\\n@@ -94,6 +95,27 @@ struct x86_cpuid builtin_cpus[] = {\n \n static struct x86_cpuid *_cpuid;\n \n+static uint64_t xgetbv(uint32_t xcr)\n+{\n+ uint32_t eax, edx;\n+\n+ __asm__ volatile (\"xgetbv\"\n+ : \"=a\" (eax), \"=d\" (edx)\n+ : \"c\" (xcr));\n+\n+ return (((uint64_t)edx) << 32) | eax;\n+}\n+\n+static bool vmx_mpx_supported()\n+{\n+ uint64_t cap_exit, cap_entry;\n+\n+ hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cap_entry);\n+ hv_vmx_read_capability(HV_VMX_CAP_EXIT, &cap_exit);\n+\n+ return ((cap_exit & (1 << 23)) && (cap_entry & (1 << 16)));\n+}\n+\n void init_cpuid(struct CPUState *cpu)\n {\n _cpuid = &builtin_cpus[2]; /* core2duo */\n@@ -277,3 +299,119 @@ void get_cpuid_func(struct CPUState *cpu, int func, int cnt, uint32_t *eax,\n break;\n }\n }\n+\n+uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,\n+ int reg)\n+{\n+ uint64_t cap;\n+ uint32_t eax, ebx, ecx, edx;\n+\n+ host_cpuid(func, idx, &eax, &ebx, &ecx, &edx);\n+\n+ switch (func) {\n+ case 0:\n+ eax = eax < (uint32_t)0xd ? eax : (uint32_t)0xd;\n+ break;\n+ case 1:\n+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |\n+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |\n+ CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |\n+ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX |\n+ CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS;\n+ ecx &= CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |\n+ CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID |\n+ CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE |\n+ CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_XSAVE |\n+ CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND;\n+ break;\n+ case 6:\n+ eax = 4;\n+ ebx = 0;\n+ ecx = 0;\n+ edx = 0;\n+ break;\n+ case 7:\n+ if (idx == 0) {\n+ ebx &= CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |\n+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 |\n+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |\n+ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_RTM |\n+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |\n+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |\n+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF |\n+ CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |\n+ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |\n+ CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_SHA_NI |\n+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL |\n+ CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_MPX;\n+\n+ if (!vmx_mpx_supported()) {\n+ ebx &= ~CPUID_7_0_EBX_MPX;\n+ }\n+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);\n+ if (!(cap & CPU_BASED2_INVPCID)) {\n+ ebx &= ~CPUID_7_0_EBX_INVPCID;\n+ }\n+\n+ ecx &= CPUID_7_0_ECX_AVX512BMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ;\n+ edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS;\n+ } else {\n+ ebx = 0;\n+ ecx = 0;\n+ edx = 0;\n+ }\n+ eax = 0;\n+ break;\n+ case 0xD:\n+ if (idx == 0) {\n+ uint64_t host_xcr0 = xgetbv(0);\n+ uint64_t supp_xcr0 = host_xcr0 & (XSTATE_FP_MASK | XSTATE_SSE_MASK |\n+ XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK |\n+ XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |\n+ XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK);\n+ eax &= supp_xcr0;\n+ if (!vmx_mpx_supported()) {\n+ eax &= ~(XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK);\n+ }\n+ } else if (idx == 1) {\n+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);\n+ eax &= CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1;\n+ if (!(cap & CPU_BASED2_XSAVES_XRSTORS)) {\n+ eax &= ~CPUID_XSAVE_XSAVES;\n+ }\n+ }\n+ break;\n+ case 0x80000001:\n+ /* LM only if HVF in 64-bit mode */\n+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |\n+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |\n+ CPUID_EXT2_SYSCALL | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |\n+ CPUID_PAT | CPUID_PSE36 | CPUID_EXT2_MMXEXT | CPUID_MMX |\n+ CPUID_FXSR | CPUID_EXT2_FXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_3DNOWEXT |\n+ CPUID_EXT2_3DNOW | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX;\n+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cap);\n+ if (!(cap & CPU_BASED_TSC_OFFSET)) {\n+ edx &= ~CPUID_EXT2_RDTSCP;\n+ }\n+ ecx &= CPUID_EXT3_LAHF_LM | CPUID_EXT3_CMP_LEG | CPUID_EXT3_CR8LEG |\n+ CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | CPUID_EXT3_MISALIGNSSE |\n+ CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_OSVW | CPUID_EXT3_XOP |\n+ CPUID_EXT3_FMA4 | CPUID_EXT3_TBM;\n+ break;\n+ default:\n+ return 0;\n+ }\n+\n+ switch (reg) {\n+ case R_EAX:\n+ return eax;\n+ case R_EBX:\n+ return ebx;\n+ case R_ECX:\n+ return ecx;\n+ case R_EDX:\n+ return edx;\n+ default:\n+ return 0;\n+ }\n+}\n", "prefixes": [ "v4", "10/14" ] }