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GET /api/patches/813228/?format=api
{ "id": 813228, "url": "http://patchwork.ozlabs.org/api/patches/813228/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1505292990-22957-4-git-send-email-yamada.masahiro@socionext.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505292990-22957-4-git-send-email-yamada.masahiro@socionext.com>", "list_archive_url": null, "date": "2017-09-13T08:56:30", "name": "[v5,3/3] gpio: uniphier: add UniPhier GPIO controller driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9caf338d036241f346e4b8a3af9041a3c234b72a", "submitter": { "id": 65882, "url": "http://patchwork.ozlabs.org/api/people/65882/?format=api", "name": "Masahiro Yamada", "email": "yamada.masahiro@socionext.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1505292990-22957-4-git-send-email-yamada.masahiro@socionext.com/mbox/", "series": [ { "id": 2840, "url": "http://patchwork.ozlabs.org/api/series/2840/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=2840", "date": "2017-09-13T08:56:28", "name": "gpio: uniphier: UniPhier GPIO driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/2840/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813228/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813228/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=nifty.com header.i=@nifty.com\n\theader.b=\"xR8mK0R1\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsbDY6pfsz9sRV\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 18:58:37 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752110AbdIMI6g (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 13 Sep 2017 04:58:36 -0400", "from conuserg-09.nifty.com ([210.131.2.76]:64543 \"EHLO\n\tconuserg-09.nifty.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752090AbdIMI6a (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Wed, 13 Sep 2017 04:58:30 -0400", "from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp\n\t[153.142.97.92]) (authenticated)\n\tby conuserg-09.nifty.com with ESMTP id v8D8ugql027391;\n\tWed, 13 Sep 2017 17:56:46 +0900" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8D8ugql027391", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com;\n\ts=dec2015msa; t=1505293007;\n\tbh=MeHoC8YLCKkxVH+G0Wb3+ycFPU1lo5L6OhpxJmIaJ7g=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=xR8mK0R1olfATFhArdbnBdUa/Bw2m7UbRlp8p4V0xuGhLkZvQ/KKi1L4kDTfI4ZSZ\n\tD0lqVMJIqLuomDaKQGjPq0j0M3GJ4g3LGjujDm+BnqjG6iLqwAModwG1k+rFSvWnJx\n\tMeRcMpBw58AKhDgosxaamIkxqrslxZF1LOnWEHgJ5I7gWkYWANpBDj9vBJQDhVAG/O\n\tH1gvcBULC0BixYpnX2iZCyhzQuqDI0sWUUTlSm9E27DZWbojqLiOrSU8yifvDSPdHR\n\tvlxtwhDOGTiLLMly0MyEELURGKjZe64KJ5KwC412ip8bKLV0sWx3z3N4EoezTfKLAn\n\tGeDJljKvAtvpg==", "X-Nifty-SrcIP": "[153.142.97.92]", "From": "Masahiro Yamada <yamada.masahiro@socionext.com>", "To": "Marc Zyngier <marc.zyngier@arm.com>, linux-gpio@vger.kernel.org", "Cc": "Thomas Gleixner <tglx@linutronix.de>,\n\tJason Cooper <jason@lakedaemon.net>, Rob Herring <robh@kernel.org>,\n\tLinus Walleij <linus.walleij@linaro.org>,\n\tDavid Daney <david.daney@cavium.com>,\n\tMasami Hiramatsu <mhiramat@kernel.org>,\n\tJassi Brar <jaswinder.singh@linaro.org>,\n\tMasahiro Yamada <yamada.masahiro@socionext.com>,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,\n\tlinux-arm-kernel@lists.infradead.org", "Subject": "[PATCH v5 3/3] gpio: uniphier: add UniPhier GPIO controller driver", "Date": "Wed, 13 Sep 2017 17:56:30 +0900", "Message-Id": "<1505292990-22957-4-git-send-email-yamada.masahiro@socionext.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505292990-22957-1-git-send-email-yamada.masahiro@socionext.com>", "References": "<1505292990-22957-1-git-send-email-yamada.masahiro@socionext.com>", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "This GPIO controller is used on UniPhier SoC family.\n\nIt also serves as an interrupt controller, but interrupt signals are\njust delivered to the parent irqchip without any latching or OR'ing.\nThis is implemented by using hierarchy IRQ domain.\n\nSigned-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>\n---\n\n MAINTAINERS | 1 +\n drivers/gpio/Kconfig | 8 +\n drivers/gpio/Makefile | 1 +\n drivers/gpio/gpio-uniphier.c | 504 +++++++++++++++++++++++++++++++\n include/dt-bindings/gpio/uniphier-gpio.h | 18 ++\n 5 files changed, 532 insertions(+)\n create mode 100644 drivers/gpio/gpio-uniphier.c\n create mode 100644 include/dt-bindings/gpio/uniphier-gpio.h", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex f46a322..f7c9cfa 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -2013,6 +2013,7 @@ F:\tarch/arm/mm/cache-uniphier.c\n F:\tarch/arm64/boot/dts/socionext/\n F:\tdrivers/bus/uniphier-system-bus.c\n F:\tdrivers/clk/uniphier/\n+F:\tdrivers/gpio/gpio-uniphier.c\n F:\tdrivers/i2c/busses/i2c-uniphier*\n F:\tdrivers/irqchip/irq-uniphier-aidet.c\n F:\tdrivers/pinctrl/uniphier/\ndiff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig\nindex 3f80f16..25c0f308 100644\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -475,6 +475,14 @@ config GPIO_TZ1090_PDC\n \thelp\n \t Say yes here to support Toumaz Xenif TZ1090 PDC GPIOs.\n \n+config GPIO_UNIPHIER\n+\ttristate \"UniPhier GPIO support\"\n+\tdepends on ARCH_UNIPHIER || COMPILE_TEST\n+\tdepends on OF_GPIO\n+\tselect IRQ_DOMAIN_HIERARCHY\n+\thelp\n+\t Say yes here to support UniPhier GPIOs.\n+\n config GPIO_VF610\n \tdef_bool y\n \tdepends on ARCH_MXC && SOC_VF610\ndiff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile\nindex aeb70e9d..472f675 100644\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -131,6 +131,7 @@ obj-$(CONFIG_GPIO_TWL6040)\t+= gpio-twl6040.o\n obj-$(CONFIG_GPIO_TZ1090)\t+= gpio-tz1090.o\n obj-$(CONFIG_GPIO_TZ1090_PDC)\t+= gpio-tz1090-pdc.o\n obj-$(CONFIG_GPIO_UCB1400)\t+= gpio-ucb1400.o\n+obj-$(CONFIG_GPIO_UNIPHIER)\t+= gpio-uniphier.o\n obj-$(CONFIG_GPIO_VF610)\t+= gpio-vf610.o\n obj-$(CONFIG_GPIO_VIPERBOARD)\t+= gpio-viperboard.o\n obj-$(CONFIG_GPIO_VR41XX)\t+= gpio-vr41xx.o\ndiff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c\nnew file mode 100644\nindex 0000000..450474d\n--- /dev/null\n+++ b/drivers/gpio/gpio-uniphier.c\n@@ -0,0 +1,504 @@\n+/*\n+ * Copyright (C) 2017 Socionext Inc.\n+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#include <linux/bitops.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/irq.h>\n+#include <linux/irqdomain.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/of_irq.h>\n+#include <linux/platform_device.h>\n+#include <linux/spinlock.h>\n+#include <dt-bindings/gpio/uniphier-gpio.h>\n+\n+#define UNIPHIER_GPIO_BANK_MASK\t\t\\\n+\t\t\t\tGENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0)\n+\n+#define UNIPHIER_GPIO_IRQ_MAX_NUM\t24\n+\n+#define UNIPHIER_GPIO_PORT_DATA\t\t0x0\t/* data */\n+#define UNIPHIER_GPIO_PORT_DIR\t\t0x4\t/* direction (1:in, 0:out) */\n+#define UNIPHIER_GPIO_IRQ_EN\t\t0x90\t/* irq enable */\n+#define UNIPHIER_GPIO_IRQ_MODE\t\t0x94\t/* irq mode (1: both edge) */\n+#define UNIPHIER_GPIO_IRQ_FLT_EN\t0x98\t/* noise filter enable */\n+#define UNIPHIER_GPIO_IRQ_FLT_CYC\t0x9c\t/* noise filter clock cycle */\n+\n+struct uniphier_gpio_priv {\n+\tstruct gpio_chip chip;\n+\tstruct irq_chip irq_chip;\n+\tstruct irq_domain *domain;\n+\tvoid __iomem *regs;\n+\tspinlock_t lock;\n+\tu32 saved_vals[0];\n+};\n+\n+static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)\n+{\n+\tunsigned int reg;\n+\n+\treg = (bank + 1) * 8;\n+\n+\t/*\n+\t * Unfortunately, the GPIO port registers are not contiguous because\n+\t * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.\n+\t */\n+\tif (reg >= UNIPHIER_GPIO_IRQ_EN)\n+\t\treg += 0x10;\n+\n+\treturn reg;\n+}\n+\n+static void uniphier_gpio_get_bank_and_mask(unsigned int offset,\n+\t\t\t\t\t unsigned int *bank, u32 *mask)\n+{\n+\t*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;\n+\t*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);\n+}\n+\n+static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,\n+\t\t\t\t unsigned int reg, u32 mask, u32 val)\n+{\n+\tunsigned long flags;\n+\tu32 tmp;\n+\n+\tspin_lock_irqsave(&priv->lock, flags);\n+\ttmp = readl(priv->regs + reg);\n+\ttmp &= ~mask;\n+\ttmp |= mask & val;\n+\twritel(tmp, priv->regs + reg);\n+\tspin_unlock_irqrestore(&priv->lock, flags);\n+}\n+\n+static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,\n+\t\t\t\t unsigned int reg, u32 mask, u32 val)\n+{\n+\tstruct uniphier_gpio_priv *priv = gpiochip_get_data(chip);\n+\n+\tif (!mask)\n+\t\treturn;\n+\n+\tuniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,\n+\t\t\t\t mask, val);\n+}\n+\n+static void uniphier_gpio_offset_write(struct gpio_chip *chip,\n+\t\t\t\t unsigned int offset, unsigned int reg,\n+\t\t\t\t int val)\n+{\n+\tunsigned int bank;\n+\tu32 mask;\n+\n+\tuniphier_gpio_get_bank_and_mask(offset, &bank, &mask);\n+\n+\tuniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);\n+}\n+\n+static int uniphier_gpio_offset_read(struct gpio_chip *chip,\n+\t\t\t\t unsigned int offset, unsigned int reg)\n+{\n+\tstruct uniphier_gpio_priv *priv = gpiochip_get_data(chip);\n+\tunsigned int bank, reg_offset;\n+\tu32 mask;\n+\n+\tuniphier_gpio_get_bank_and_mask(offset, &bank, &mask);\n+\treg_offset = uniphier_gpio_bank_to_reg(bank) + reg;\n+\n+\treturn !!(readl(priv->regs + reg_offset) & mask);\n+}\n+\n+static int uniphier_gpio_get_direction(struct gpio_chip *chip,\n+\t\t\t\t unsigned int offset)\n+{\n+\treturn uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR);\n+}\n+\n+static int uniphier_gpio_direction_input(struct gpio_chip *chip,\n+\t\t\t\t\t unsigned int offset)\n+{\n+\tuniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);\n+\n+\treturn 0;\n+}\n+\n+static int uniphier_gpio_direction_output(struct gpio_chip *chip,\n+\t\t\t\t\t unsigned int offset, int val)\n+{\n+\tuniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);\n+\tuniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);\n+\n+\treturn 0;\n+}\n+\n+static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)\n+{\n+\treturn uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);\n+}\n+\n+static void uniphier_gpio_set(struct gpio_chip *chip,\n+\t\t\t unsigned int offset, int val)\n+{\n+\tuniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);\n+}\n+\n+static void uniphier_gpio_set_multiple(struct gpio_chip *chip,\n+\t\t\t\t unsigned long *mask, unsigned long *bits)\n+{\n+\tunsigned int bank, shift, bank_mask, bank_bits;\n+\tint i;\n+\n+\tfor (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) {\n+\t\tbank = i / UNIPHIER_GPIO_LINES_PER_BANK;\n+\t\tshift = i % BITS_PER_LONG;\n+\t\tbank_mask = (mask[BIT_WORD(i)] >> shift) &\n+\t\t\t\t\t\tUNIPHIER_GPIO_BANK_MASK;\n+\t\tbank_bits = bits[BIT_WORD(i)] >> shift;\n+\n+\t\tuniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,\n+\t\t\t\t\t bank_mask, bank_bits);\n+\t}\n+}\n+\n+static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)\n+{\n+\tstruct irq_fwspec fwspec;\n+\n+\tif (offset < UNIPHIER_GPIO_IRQ_OFFSET)\n+\t\treturn -ENXIO;\n+\n+\tfwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);\n+\tfwspec.param_count = 2;\n+\tfwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;\n+\tfwspec.param[1] = IRQ_TYPE_NONE;\n+\n+\treturn irq_create_fwspec_mapping(&fwspec);\n+}\n+\n+static void uniphier_gpio_irq_mask(struct irq_data *data)\n+{\n+\tstruct uniphier_gpio_priv *priv = data->chip_data;\n+\tu32 mask = BIT(data->hwirq);\n+\n+\tuniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);\n+\n+\treturn irq_chip_mask_parent(data);\n+}\n+\n+static void uniphier_gpio_irq_unmask(struct irq_data *data)\n+{\n+\tstruct uniphier_gpio_priv *priv = data->chip_data;\n+\tu32 mask = BIT(data->hwirq);\n+\n+\tuniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);\n+\n+\treturn irq_chip_unmask_parent(data);\n+}\n+\n+static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)\n+{\n+\tstruct uniphier_gpio_priv *priv = data->chip_data;\n+\tu32 mask = BIT(data->hwirq);\n+\tu32 val = 0;\n+\n+\tif (type == IRQ_TYPE_EDGE_BOTH) {\n+\t\tval = mask;\n+\t\ttype = IRQ_TYPE_EDGE_FALLING;\n+\t}\n+\n+\tuniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);\n+\t/* To enable both edge detection, the noise filter must be enabled. */\n+\tuniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);\n+\n+\treturn irq_chip_set_type_parent(data, type);\n+}\n+\n+static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,\n+\t\t\t\t\t struct irq_fwspec *fwspec,\n+\t\t\t\t\t unsigned long *out_hwirq,\n+\t\t\t\t\t unsigned int *out_type)\n+{\n+\tif (WARN_ON(fwspec->param_count < 2))\n+\t\treturn -EINVAL;\n+\n+\t*out_hwirq = fwspec->param[0];\n+\t*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;\n+\n+\treturn 0;\n+}\n+\n+static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,\n+\t\t\t\t\t unsigned int virq,\n+\t\t\t\t\t unsigned int nr_irqs, void *arg)\n+{\n+\tstruct uniphier_gpio_priv *priv = domain->host_data;\n+\tstruct irq_domain *parent_domain = domain->parent;\n+\tstruct of_phandle_args parent_irq;\n+\tstruct irq_fwspec parent_fwspec;\n+\tirq_hw_number_t hwirq, parent_hwirq;\n+\tunsigned int type, parent_virq;\n+\tint ret;\n+\n+\tif (WARN_ON(nr_irqs != 1))\n+\t\treturn -EINVAL;\n+\n+\tret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = of_irq_parse_one(priv->chip.parent->of_node, hwirq, &parent_irq);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tof_phandle_args_to_fwspec(&parent_irq, &parent_fwspec);\n+\n+\tif (WARN_ON(!parent_domain))\n+\t\treturn -EINVAL;\n+\n+\tif (WARN_ON(parent_domain->fwnode != parent_fwspec.fwnode))\n+\t\treturn -EINVAL;\n+\n+\tparent_hwirq = parent_fwspec.param[0];\n+\n+\t/*\n+\t * of_platform_populate() may allocate IRQ resources statically.\n+\t * If the parent hwirq has been already mapped, we need to unmap it\n+\t * because hierarchy irqdomain shares one virq among stacked irqchips.\n+\t */\n+\tparent_virq = irq_find_mapping(parent_domain, parent_hwirq);\n+\tif (parent_virq) {\n+\t\t/* If someone has requested this irq, do not bother it */\n+\t\tif (irq_has_action(parent_virq))\n+\t\t\treturn -EBUSY;\n+\t\tirq_dispose_mapping(parent_virq);\n+\t}\n+\n+\tret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,\n+\t\t\t\t\t &priv->irq_chip, priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (type == IRQ_TYPE_EDGE_BOTH)\n+\t\tparent_fwspec.param[1] = IRQ_TYPE_EDGE_FALLING;\n+\telse\n+\t\tparent_fwspec.param[1] = type;\n+\n+\treturn irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);\n+}\n+\n+static void uniphier_gpio_irq_domain_activate(struct irq_domain *domain,\n+\t\t\t\t\t struct irq_data *data)\n+{\n+\tstruct uniphier_gpio_priv *priv = domain->host_data;\n+\tstruct gpio_chip *chip = &priv->chip;\n+\n+\tgpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);\n+}\n+\n+static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,\n+\t\t\t\t\t\tstruct irq_data *data)\n+{\n+\tstruct uniphier_gpio_priv *priv = domain->host_data;\n+\tstruct gpio_chip *chip = &priv->chip;\n+\n+\tgpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);\n+}\n+\n+static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {\n+\t.alloc = uniphier_gpio_irq_domain_alloc,\n+\t.free = irq_domain_free_irqs_common,\n+\t.activate = uniphier_gpio_irq_domain_activate,\n+\t.deactivate = uniphier_gpio_irq_domain_deactivate,\n+\t.translate = uniphier_gpio_irq_domain_translate,\n+};\n+\n+static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)\n+{\n+\t/*\n+\t * Due to the hardware design, the noise filter must be enabled to\n+\t * detect both edge interrupts. This filter is intended to remove the\n+\t * noise from the irq lines. It does not work for GPIO input, so GPIO\n+\t * debounce is not supported. Unfortunately, the filter period is\n+\t * shared among all irq lines. Just choose a sensible period here.\n+\t */\n+\twritel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);\n+}\n+\n+static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)\n+{\n+\treturn DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);\n+}\n+\n+static int uniphier_gpio_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *parent_np;\n+\tstruct irq_domain *parent_domain;\n+\tstruct uniphier_gpio_priv *priv;\n+\tstruct gpio_chip *chip;\n+\tstruct irq_chip *irq_chip;\n+\tstruct resource *regs;\n+\tunsigned int nregs;\n+\tu32 ngpios;\n+\tint ret;\n+\n+\tparent_np = of_irq_find_parent(dev->of_node);\n+\tif (!parent_np)\n+\t\treturn -ENXIO;\n+\n+\tparent_domain = irq_find_host(parent_np);\n+\tof_node_put(parent_np);\n+\tif (!parent_domain)\n+\t\treturn -EPROBE_DEFER;\n+\n+\tret = of_property_read_u32(dev->of_node, \"ngpios\", &ngpios);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tnregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;\n+\tpriv = devm_kzalloc(dev,\n+\t\t\t sizeof(*priv) + sizeof(priv->saved_vals[0]) * nregs,\n+\t\t\t GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tregs = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tpriv->regs = devm_ioremap_resource(dev, regs);\n+\tif (IS_ERR(priv->regs))\n+\t\treturn PTR_ERR(priv->regs);\n+\n+\tspin_lock_init(&priv->lock);\n+\n+\tchip = &priv->chip;\n+\tchip->label = dev_name(dev);\n+\tchip->parent = dev;\n+\tchip->request = gpiochip_generic_request;\n+\tchip->free = gpiochip_generic_free;\n+\tchip->get_direction = uniphier_gpio_get_direction;\n+\tchip->direction_input = uniphier_gpio_direction_input;\n+\tchip->direction_output = uniphier_gpio_direction_output;\n+\tchip->get = uniphier_gpio_get;\n+\tchip->set = uniphier_gpio_set;\n+\tchip->set_multiple = uniphier_gpio_set_multiple;\n+\tchip->to_irq = uniphier_gpio_to_irq;\n+\tchip->base = -1;\n+\tchip->ngpio = ngpios;\n+\n+\tirq_chip = &priv->irq_chip;\n+\tirq_chip->name = dev_name(dev);\n+\tirq_chip->irq_mask = uniphier_gpio_irq_mask;\n+\tirq_chip->irq_unmask = uniphier_gpio_irq_unmask;\n+\tirq_chip->irq_eoi = irq_chip_eoi_parent;\n+\tirq_chip->irq_set_affinity = irq_chip_set_affinity_parent;\n+\tirq_chip->irq_set_type = uniphier_gpio_irq_set_type;\n+\n+\tuniphier_gpio_hw_init(priv);\n+\n+\tret = devm_gpiochip_add_data(dev, chip, priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tpriv->domain = irq_domain_create_hierarchy(\n+\t\t\t\t\tparent_domain, 0,\n+\t\t\t\t\tUNIPHIER_GPIO_IRQ_MAX_NUM,\n+\t\t\t\t\tof_node_to_fwnode(dev->of_node),\n+\t\t\t\t\t&uniphier_gpio_irq_domain_ops, priv);\n+\tif (!priv->domain)\n+\t\treturn -ENOMEM;\n+\n+\tplatform_set_drvdata(pdev, priv);\n+\n+\treturn 0;\n+}\n+\n+static int uniphier_gpio_remove(struct platform_device *pdev)\n+{\n+\tstruct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);\n+\n+\tirq_domain_remove(priv->domain);\n+\n+\treturn 0;\n+}\n+\n+static int __maybe_unused uniphier_gpio_suspend(struct device *dev)\n+{\n+\tstruct uniphier_gpio_priv *priv = dev_get_drvdata(dev);\n+\tunsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);\n+\tu32 *val = priv->saved_vals;\n+\tunsigned int reg;\n+\tint i;\n+\n+\tfor (i = 0; i < nbanks; i++) {\n+\t\treg = uniphier_gpio_bank_to_reg(i);\n+\n+\t\t*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);\n+\t\t*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);\n+\t}\n+\n+\t*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);\n+\t*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);\n+\t*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);\n+\n+\treturn 0;\n+}\n+\n+static int __maybe_unused uniphier_gpio_resume(struct device *dev)\n+{\n+\tstruct uniphier_gpio_priv *priv = dev_get_drvdata(dev);\n+\tunsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);\n+\tconst u32 *val = priv->saved_vals;\n+\tunsigned int reg;\n+\tint i;\n+\n+\tfor (i = 0; i < nbanks; i++) {\n+\t\treg = uniphier_gpio_bank_to_reg(i);\n+\n+\t\twritel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);\n+\t\twritel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);\n+\t}\n+\n+\twritel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);\n+\twritel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);\n+\twritel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);\n+\n+\tuniphier_gpio_hw_init(priv);\n+\n+\treturn 0;\n+}\n+\n+static const struct dev_pm_ops uniphier_gpio_pm_ops = {\n+\tSET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend,\n+\t\t\t\t uniphier_gpio_resume)\n+};\n+\n+static const struct of_device_id uniphier_gpio_match[] = {\n+\t{ .compatible = \"socionext,uniphier-gpio\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, uniphier_gpio_match);\n+\n+static struct platform_driver uniphier_gpio_driver = {\n+\t.probe = uniphier_gpio_probe,\n+\t.remove = uniphier_gpio_remove,\n+\t.driver = {\n+\t\t.name = \"uniphier-gpio\",\n+\t\t.of_match_table = uniphier_gpio_match,\n+\t\t.pm = &uniphier_gpio_pm_ops,\n+\t},\n+};\n+module_platform_driver(uniphier_gpio_driver);\n+\n+MODULE_AUTHOR(\"Masahiro Yamada <yamada.masahiro@socionext.com>\");\n+MODULE_DESCRIPTION(\"UniPhier GPIO driver\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/include/dt-bindings/gpio/uniphier-gpio.h b/include/dt-bindings/gpio/uniphier-gpio.h\nnew file mode 100644\nindex 0000000..9f0ad17\n--- /dev/null\n+++ b/include/dt-bindings/gpio/uniphier-gpio.h\n@@ -0,0 +1,18 @@\n+/*\n+ * Copyright (C) 2017 Socionext Inc.\n+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>\n+ */\n+\n+#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H\n+#define _DT_BINDINGS_GPIO_UNIPHIER_H\n+\n+#define UNIPHIER_GPIO_LINES_PER_BANK\t8\n+\n+#define UNIPHIER_GPIO_IRQ_OFFSET\t((UNIPHIER_GPIO_LINES_PER_BANK) * 15)\n+\n+#define UNIPHIER_GPIO_PORT(bank, line)\t\\\n+\t\t\t((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))\n+\n+#define UNIPHIER_GPIO_IRQ(n)\t\t((UNIPHIER_GPIO_IRQ_OFFSET) + (n))\n+\n+#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */\n", "prefixes": [ "v5", "3/3" ] }