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GET /api/patches/813188/?format=api
{ "id": 813188, "url": "http://patchwork.ozlabs.org/api/patches/813188/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170913065854.26134-5-wenyou.yang@microchip.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170913065854.26134-5-wenyou.yang@microchip.com>", "list_archive_url": null, "date": "2017-09-13T06:58:49", "name": "[U-Boot,v6,4/9] ARM: at91: spl: Add mck function to lower rate while switching", "commit_ref": "2b21cf55cc767bc1303f22c3f6f7b9d6f0845c02", "pull_url": null, "state": "accepted", "archived": false, "hash": "cdbfa2a73d65ffaa9991e164c3e68ded1d911104", "submitter": { "id": 69532, "url": "http://patchwork.ozlabs.org/api/people/69532/?format=api", "name": "Wenyou Yang", "email": "Wenyou.Yang@microchip.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170913065854.26134-5-wenyou.yang@microchip.com/mbox/", "series": [ { "id": 2820, "url": "http://patchwork.ozlabs.org/api/series/2820/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=2820", "date": "2017-09-13T06:58:45", "name": "board: atmel: Add new board SAMA5D27-SOM1-EK board.", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/2820/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813188/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813188/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsXjH5nxTz9sNw\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 17:04:51 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 97066C2259B; Wed, 13 Sep 2017 07:02:27 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 52861C223E0;\n\tWed, 13 Sep 2017 07:02:10 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 2134FC224E7; Wed, 13 Sep 2017 07:01:00 +0000 (UTC)", "from DVREDG01.corp.atmel.com (nasmtp01.atmel.com [192.199.1.245])\n\tby lists.denx.de (Postfix) with ESMTPS id 28284C22350\n\tfor <u-boot@lists.denx.de>; Wed, 13 Sep 2017 07:00:55 +0000 (UTC)", "from apsmtp01.atmel.com (10.168.254.31) by DVREDG01.corp.atmel.com\n\t(10.42.103.30) with Microsoft SMTP Server (TLS) id 14.3.235.1;\n\tWed, 13 Sep 2017 01:00:05 -0600", "from shaarm01.corp.atmel.com (10.168.254.13) by apsmtp01.atmel.com\n\t(10.168.254.31) with Microsoft SMTP Server id 14.3.235.1;\n\tWed, 13 Sep 2017 15:04:28 +0800" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "From": "Wenyou Yang <wenyou.yang@microchip.com>", "To": "U-Boot Mailing List <u-boot@lists.denx.de>", "Date": "Wed, 13 Sep 2017 14:58:49 +0800", "Message-ID": "<20170913065854.26134-5-wenyou.yang@microchip.com>", "X-Mailer": "git-send-email 2.13.0", "In-Reply-To": "<20170913065854.26134-1-wenyou.yang@microchip.com>", "References": "<20170913065854.26134-1-wenyou.yang@microchip.com>", "MIME-Version": "1.0", "Cc": "Marek Vasut <marex@denx.de>, Tom Rini <trini@konsulko.com>", "Subject": "[U-Boot] [PATCH v6 4/9] ARM: at91: spl: Add mck function to lower\n\trate while switching", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Refer to the commit 70f8c8316ad(PMC: add new mck function to lower\nrate while switching) from AT91Bootstrap.\n\nWhile switching to a lower clock source, we must switch the clock\nsource first instead of last. Otherwise, we could end up with\ntoo high frequency on internal bus and peripherals.\nThis happens on SAMA5D2 as exitting from the ROM code.\n\nAdd a function pmc_mck_init_down() to allow this sequence.\n\nSigned-off-by: Wenyou Yang <wenyou.yang@microchip.com>\nReviewed-by: Simon Glass <sjg@chromium.org>\n---\n\nChanges in v6:\n - Add function comments for at91_mck_init_down().\n\nChanges in v5: None\nChanges in v4: None\nChanges in v3: None\nChanges in v2: None\n\n arch/arm/mach-at91/armv7/clock.c | 42 +++++++++++++++++++++++++++\n arch/arm/mach-at91/include/mach/at91_common.h | 1 +\n 2 files changed, 43 insertions(+)", "diff": "diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c\nindex 2e55953799..51c5e80be7 100644\n--- a/arch/arm/mach-at91/armv7/clock.c\n+++ b/arch/arm/mach-at91/armv7/clock.c\n@@ -150,6 +150,48 @@ void at91_mck_init(u32 mckr)\n \t\t;\n }\n \n+/*\n+ * For the Master Clock Controller Register(MCKR), while switching\n+ * to a lower clock source, we must switch the clock source first\n+ * instead of last. Otherwise, we could end up with too high frequency\n+ * on the internal bus and peripherals.\n+ */\n+void at91_mck_init_down(u32 mckr)\n+{\n+\tstruct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;\n+\tu32 tmp;\n+\n+\ttmp = readl(&pmc->mckr);\n+\ttmp &= (~AT91_PMC_MCKR_CSS_MASK);\n+\ttmp |= (mckr & AT91_PMC_MCKR_CSS_MASK);\n+\twritel(tmp, &pmc->mckr);\n+\n+\twhile (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))\n+\t\t;\n+\n+#ifdef CPU_HAS_H32MXDIV\n+\ttmp = readl(&pmc->mckr);\n+\ttmp &= (~AT91_PMC_MCKR_H32MXDIV);\n+\ttmp |= (mckr & AT91_PMC_MCKR_H32MXDIV);\n+\twritel(tmp, &pmc->mckr);\n+#endif\n+\n+\ttmp = readl(&pmc->mckr);\n+\ttmp &= (~AT91_PMC_MCKR_PLLADIV_MASK);\n+\ttmp |= (mckr & AT91_PMC_MCKR_PLLADIV_MASK);\n+\twritel(tmp, &pmc->mckr);\n+\n+\ttmp = readl(&pmc->mckr);\n+\ttmp &= (~AT91_PMC_MCKR_MDIV_MASK);\n+\ttmp |= (mckr & AT91_PMC_MCKR_MDIV_MASK);\n+\twritel(tmp, &pmc->mckr);\n+\n+\ttmp = readl(&pmc->mckr);\n+\ttmp &= (~AT91_PMC_MCKR_PRES_MASK);\n+\ttmp |= (mckr & AT91_PMC_MCKR_PRES_MASK);\n+\twritel(tmp, &pmc->mckr);\n+}\n+\n int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)\n {\n \tstruct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;\ndiff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h\nindex 5416eb455d..0b09ce7b2e 100644\n--- a/arch/arm/mach-at91/include/mach/at91_common.h\n+++ b/arch/arm/mach-at91/include/mach/at91_common.h\n@@ -25,6 +25,7 @@ void at91_lcd_hw_init(void);\n void at91_plla_init(u32 pllar);\n void at91_pllb_init(u32 pllar);\n void at91_mck_init(u32 mckr);\n+void at91_mck_init_down(u32 mckr);\n void at91_pmc_init(void);\n void mem_init(void);\n void at91_phy_reset(void);\n", "prefixes": [ "U-Boot", "v6", "4/9" ] }