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GET /api/patches/813172/?format=api
{ "id": 813172, "url": "http://patchwork.ozlabs.org/api/patches/813172/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170913061049.13256-4-bsingharora@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20170913061049.13256-4-bsingharora@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20170913061049.13256-4-bsingharora@gmail.com/", "date": "2017-09-13T06:10:47", "name": "[v2,3/5] powerpc/mce: Hookup derror (load/store) UE errors", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "abcf6cc9adb5c427f8cd49da50ee18751f0a1a3a", "submitter": { "id": 9347, "url": "http://patchwork.ozlabs.org/api/people/9347/?format=api", "name": "Balbir Singh", "email": "bsingharora@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170913061049.13256-4-bsingharora@gmail.com/mbox/", "series": [ { "id": 2813, "url": "http://patchwork.ozlabs.org/api/series/2813/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=2813", "date": "2017-09-13T06:10:44", "name": "Revisit MCE handling for UE Errors", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2813/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813172/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813172/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsWj13z9Qz9sPs\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 13 Sep 2017 16:19:33 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xsWj12rQhzDrJV\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 13 Sep 2017 16:19:33 +1000 (AEST)", "from mail-pf0-x243.google.com (mail-pf0-x243.google.com\n\t[IPv6:2607:f8b0:400e:c00::243])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xsWWM74hhzDrJZ\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 13 Sep 2017 16:11:11 +1000 (AEST)", "by mail-pf0-x243.google.com with SMTP id f84so7146903pfj.3\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 12 Sep 2017 23:11:11 -0700 (PDT)", "from firefly.ozlabs.ibm.com.ozlabs.ibm.com ([122.99.82.10])\n\tby smtp.gmail.com with ESMTPSA id\n\tt65sm22581016pfk.59.2017.09.12.23.11.07\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 12 Sep 2017 23:11:09 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"WlV1ZSkR\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"WlV1ZSkR\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400e:c00::243; helo=mail-pf0-x243.google.com;\n\tenvelope-from=bsingharora@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"WlV1ZSkR\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=crXOrPYW8lc5m0Aj2nuDiruudstRXfIORA9jQ/v/EA0=;\n\tb=WlV1ZSkR8Lwg0ech5R3YZYdRXtNSlfLEy2r2vcdTiKfPQ6P/vebHnMNqohARUF55Mr\n\tReUVjytEjmgp8DK+dL51PXOmAtI6iyWgGngcHBlaeDrmQDFEB1w+4Zf7LY/aHU5KXW3k\n\ti6lQN1yaZ4saCRYtibXzJment0ezXilKGJ4lXH2lmnKk1PMe7ACQy81rfSuxS2CaqNH/\n\tUIOIuyJqEwva8/afbr5QsF9RMDzW2fviQ7ZTjfo/4BUmSrmypdDe8arH89mKqJad8p9D\n\tTuQ3Y/KcM8BmyeiI8xE2LWnkijox4RBCgXcPlZXfF6914ny91K9DbhzwUPgA52zB7Pu+\n\tYFwg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=crXOrPYW8lc5m0Aj2nuDiruudstRXfIORA9jQ/v/EA0=;\n\tb=ivxyBma+3szIa4XBXg35pddK21ASPO2aC8xAy2wfK2IeU+1ukbFNs2OEY1Vwt/KMsA\n\tQPmAeGO3Ec5pNGNTff3QpDK1+tf8sm4fFryotVUsZQYIc0mAv3vNpMuX3RC7fDk0lr2t\n\tj2C5n4gE0dgblZ03BfBIBF3FYdcvqnoYxNm2wuCIksmV+ePATjlIBm5/UxtKFlFLG6Qp\n\tjtyuaYNRyBctao1ttIIKsha0um1Pk5vhAPCnvuxhOege8f5KOEAy0Iwplukc9Ay3Zg4/\n\tomWcz4sQrwhcyntxeGhQqR5xoRsAir6RykcbvNTpzFHzHMno6IM3/wmHQ279I+4r6ECW\n\tk+3g==", "X-Gm-Message-State": "AHPjjUhUP3+nUTzomjJmoZ6A6pSJ0/tBhS8BoTxlG83t4xll6g1v84KR\n\tiOnWk+fEmqKjsA==", "X-Google-Smtp-Source": "ADKCNb44dzeMASeMZyadG6Jv7Yal1EB8Gq7s/fNLBhKEdkxYt2ldehp1dNJiGnGnlk2b/ndfycwIqw==", "X-Received": "by 10.98.80.85 with SMTP id e82mr17549168pfb.265.1505283069983; \n\tTue, 12 Sep 2017 23:11:09 -0700 (PDT)", "From": "Balbir Singh <bsingharora@gmail.com>", "To": "mpe@ellerman.id.au,\n\tnpiggin@gmail.com,\n\tmahesh@linux.vnet.ibm.com", "Subject": "[PATCH v2 3/5] powerpc/mce: Hookup derror (load/store) UE errors", "Date": "Wed, 13 Sep 2017 16:10:47 +1000", "Message-Id": "<20170913061049.13256-4-bsingharora@gmail.com>", "X-Mailer": "git-send-email 2.9.5", "In-Reply-To": "<20170913061049.13256-1-bsingharora@gmail.com>", "References": "<20170913061049.13256-1-bsingharora@gmail.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "linuxppc-dev@lists.ozlabs.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Extract physical_address for UE errors by walking the page\ntables for the mm and address at the NIP, to extract the\ninstruction. Then use the instruction to find the effective\naddress via analyse_instr().\n\nWe might have page table walking races, but we expect them to\nbe rare, the physical address extraction is best effort. The idea\nis to then hook up this infrastructure to memory failure eventually.\n\nSigned-off-by: Balbir Singh <bsingharora@gmail.com>\n---\n arch/powerpc/include/asm/mce.h | 2 +-\n arch/powerpc/kernel/mce.c | 6 +++-\n arch/powerpc/kernel/mce_power.c | 80 ++++++++++++++++++++++++++++++++++++++---\n 3 files changed, 81 insertions(+), 7 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h\nindex 75292c7..3a1226e 100644\n--- a/arch/powerpc/include/asm/mce.h\n+++ b/arch/powerpc/include/asm/mce.h\n@@ -204,7 +204,7 @@ struct mce_error_info {\n \n extern void save_mce_event(struct pt_regs *regs, long handled,\n \t\t\t struct mce_error_info *mce_err, uint64_t nip,\n-\t\t\t uint64_t addr);\n+\t\t\t uint64_t addr, uint64_t phys_addr);\n extern int get_mce_event(struct machine_check_event *mce, bool release);\n extern void release_mce_event(void);\n extern void machine_check_queue_event(void);\ndiff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c\nindex f351adf..c7acc33 100644\n--- a/arch/powerpc/kernel/mce.c\n+++ b/arch/powerpc/kernel/mce.c\n@@ -82,7 +82,7 @@ static void mce_set_error_info(struct machine_check_event *mce,\n */\n void save_mce_event(struct pt_regs *regs, long handled,\n \t\t struct mce_error_info *mce_err,\n-\t\t uint64_t nip, uint64_t addr)\n+\t\t uint64_t nip, uint64_t addr, uint64_t phys_addr)\n {\n \tint index = __this_cpu_inc_return(mce_nest_count) - 1;\n \tstruct machine_check_event *mce = this_cpu_ptr(&mce_event[index]);\n@@ -140,6 +140,10 @@ void save_mce_event(struct pt_regs *regs, long handled,\n \t} else if (mce->error_type == MCE_ERROR_TYPE_UE) {\n \t\tmce->u.ue_error.effective_address_provided = true;\n \t\tmce->u.ue_error.effective_address = addr;\n+\t\tif (phys_addr != ULONG_MAX) {\n+\t\t\tmce->u.ue_error.physical_address_provided = true;\n+\t\t\tmce->u.ue_error.physical_address = phys_addr;\n+\t\t}\n \t}\n \treturn;\n }\ndiff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c\nindex b76ca19..2dfbbe0 100644\n--- a/arch/powerpc/kernel/mce_power.c\n+++ b/arch/powerpc/kernel/mce_power.c\n@@ -27,6 +27,29 @@\n #include <asm/mmu.h>\n #include <asm/mce.h>\n #include <asm/machdep.h>\n+#include <asm/pgtable.h>\n+#include <asm/pte-walk.h>\n+#include <asm/sstep.h>\n+\n+/*\n+ * Convert an address related to an mm to a PFN. NOTE: we are in real\n+ * mode, we could potentially race with page table updates.\n+ */\n+static unsigned long addr_to_pfn(struct mm_struct *mm, unsigned long addr)\n+{\n+\tpte_t *ptep;\n+\tunsigned long flags;\n+\n+\tlocal_irq_save(flags);\n+\tif (mm == current->mm)\n+\t\tptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL);\n+\telse\n+\t\tptep = find_init_mm_pte(addr, NULL);\n+\tlocal_irq_restore(flags);\n+\tif (!ptep || pte_special(*ptep))\n+\t\treturn ULONG_MAX;\n+\treturn pte_pfn(*ptep);\n+}\n \n static void flush_tlb_206(unsigned int num_sets, unsigned int action)\n {\n@@ -421,6 +444,48 @@ static const struct mce_derror_table mce_p9_derror_table[] = {\n MCE_INITIATOR_CPU, MCE_SEV_ERROR_SYNC, },\n { 0, false, 0, 0, 0, 0 } };\n \n+static int mce_find_instr_ea_and_pfn(struct pt_regs *regs, uint64_t *addr,\n+\t\t\t\t\tuint64_t *phys_addr)\n+{\n+\t/*\n+\t * Carefully look at the NIP to determine\n+\t * the instruction to analyse. Reading the NIP\n+\t * in real-mode is tricky and can lead to recursive\n+\t * faults\n+\t */\n+\tint instr;\n+\tstruct mm_struct *mm;\n+\tunsigned long nip = regs->nip;\n+\tunsigned long pfn, instr_addr;\n+\tstruct instruction_op op;\n+\tstruct pt_regs tmp = *regs;\n+\n+\tif (user_mode(regs))\n+\t\tmm = current->mm;\n+\telse\n+\t\tmm = &init_mm;\n+\n+\tpfn = addr_to_pfn(mm, nip);\n+\tif (pfn != ULONG_MAX) {\n+\t\tinstr_addr = (pfn << PAGE_SHIFT) + (nip & ~PAGE_MASK);\n+\t\tinstr = *(unsigned int *)(instr_addr);\n+\t\tif (!analyse_instr(&op, &tmp, instr)) {\n+\t\t\tpfn = addr_to_pfn(mm, op.ea);\n+\t\t\t*addr = op.ea;\n+\t\t\t*phys_addr = pfn;\n+\t\t\treturn 0;\n+\t\t}\n+\t\t/*\n+\t\t * analyse_instr() might fail if the instruction\n+\t\t * is not a load/store, although this is unexpected\n+\t\t * for load/store errors or if we got the NIP\n+\t\t * wrong\n+\t\t */\n+\t}\n+\t*addr = 0;\n+\treturn -1;\n+}\n+\n static int mce_handle_ierror(struct pt_regs *regs,\n \t\tconst struct mce_ierror_table table[],\n \t\tstruct mce_error_info *mce_err, uint64_t *addr)\n@@ -489,7 +554,8 @@ static int mce_handle_ierror(struct pt_regs *regs,\n \n static int mce_handle_derror(struct pt_regs *regs,\n \t\tconst struct mce_derror_table table[],\n-\t\tstruct mce_error_info *mce_err, uint64_t *addr)\n+\t\tstruct mce_error_info *mce_err, uint64_t *addr,\n+\t\tuint64_t *phys_addr)\n {\n \tuint64_t dsisr = regs->dsisr;\n \tint handled = 0;\n@@ -555,7 +621,10 @@ static int mce_handle_derror(struct pt_regs *regs,\n \t\tmce_err->initiator = table[i].initiator;\n \t\tif (table[i].dar_valid)\n \t\t\t*addr = regs->dar;\n-\n+\t\telse if (mce_err->severity == MCE_SEV_ERROR_SYNC &&\n+\t\t\t\ttable[i].error_type == MCE_ERROR_TYPE_UE) {\n+\t\t\tmce_find_instr_ea_and_pfn(regs, addr, phys_addr);\n+\t\t}\n \t\tfound = 1;\n \t}\n \n@@ -592,19 +661,20 @@ static long mce_handle_error(struct pt_regs *regs,\n \t\tconst struct mce_ierror_table itable[])\n {\n \tstruct mce_error_info mce_err = { 0 };\n-\tuint64_t addr;\n+\tuint64_t addr, phys_addr;\n \tuint64_t srr1 = regs->msr;\n \tlong handled;\n \n \tif (SRR1_MC_LOADSTORE(srr1))\n-\t\thandled = mce_handle_derror(regs, dtable, &mce_err, &addr);\n+\t\thandled = mce_handle_derror(regs, dtable, &mce_err, &addr,\n+\t\t\t\t&phys_addr);\n \telse\n \t\thandled = mce_handle_ierror(regs, itable, &mce_err, &addr);\n \n \tif (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE)\n \t\thandled = mce_handle_ue_error(regs);\n \n-\tsave_mce_event(regs, handled, &mce_err, regs->nip, addr);\n+\tsave_mce_event(regs, handled, &mce_err, regs->nip, addr, phys_addr);\n \n \treturn handled;\n }\n", "prefixes": [ "v2", "3/5" ] }