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GET /api/patches/813006/?format=api
{ "id": 813006, "url": "http://patchwork.ozlabs.org/api/patches/813006/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-18-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-18-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:14:04", "name": "[17/19] nvic: Make ICSR banked for v8M", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8bee523bcfe63b7677e9606bf27d82a2886c19d9", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-18-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813006/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813006/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsD2j6xRQz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:33:49 +1000 (AEST)", "from localhost ([::1]:38052 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drq0K-00065F-37\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:33:48 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43622)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph7-0003Yu-Lg\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:58 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph6-0006Vs-Fq\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:57 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37316)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drph3-0006QF-7O; Tue, 12 Sep 2017 14:13:53 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drph1-0001AY-7j; Tue, 12 Sep 2017 19:13:51 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:14:04 +0100", "Message-Id": "<1505240046-11454-18-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 17/19] nvic: Make ICSR banked for v8M", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "The ICSR NVIC register is banked for v8M. This doesn't\nrequire any new state, but it does mean that some bits\nare controlled by BFHNFNMINS and some bits must work\nwith the correct banked exception. There is also a new\nin v8M PENDNMICLR bit.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/intc/armv7m_nvic.c | 45 ++++++++++++++++++++++++++++++++-------------\n 1 file changed, 32 insertions(+), 13 deletions(-)", "diff": "diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 5e5aecd..21fd199 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -703,7 +703,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)\n }\n case 0xd00: /* CPUID Base. */\n return cpu->midr;\n- case 0xd04: /* Interrupt Control State. */\n+ case 0xd04: /* Interrupt Control State (ICSR) */\n /* VECTACTIVE */\n val = cpu->env.v7m.exception;\n /* VECTPENDING */\n@@ -716,19 +716,32 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)\n if (nvic_rettobase(s)) {\n val |= (1 << 11);\n }\n- /* PENDSTSET */\n- if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {\n- val |= (1 << 26);\n- }\n- /* PENDSVSET */\n- if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {\n- val |= (1 << 28);\n+ if (attrs.secure) {\n+ /* PENDSTSET */\n+ if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) {\n+ val |= (1 << 26);\n+ }\n+ /* PENDSVSET */\n+ if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) {\n+ val |= (1 << 28);\n+ }\n+ } else {\n+ /* PENDSTSET */\n+ if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {\n+ val |= (1 << 26);\n+ }\n+ /* PENDSVSET */\n+ if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {\n+ val |= (1 << 28);\n+ }\n }\n /* NMIPENDSET */\n- if (s->vectors[ARMV7M_EXCP_NMI].pending) {\n+ if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) &&\n+ s->vectors[ARMV7M_EXCP_NMI].pending) {\n val |= (1 << 31);\n }\n- /* ISRPREEMPT not implemented */\n+ /* ISRPREEMPT: RES0 when halting debug not implemented */\n+ /* STTNS: RES0 for the Main Extension */\n return val;\n case 0xd08: /* Vector Table Offset. */\n return cpu->env.v7m.vecbase[attrs.secure];\n@@ -953,9 +966,15 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n nvic_irq_update(s);\n break;\n }\n- case 0xd04: /* Interrupt Control State. */\n- if (value & (1 << 31)) {\n- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);\n+ case 0xd04: /* Interrupt Control State (ICSR) */\n+ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {\n+ if (value & (1 << 31)) {\n+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);\n+ } else if (value & (1 << 30) &&\n+ arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ /* PENDNMICLR didn't exist in v7M */\n+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false);\n+ }\n }\n if (value & (1 << 28)) {\n armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);\n", "prefixes": [ "17/19" ] }