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GET /api/patches/813000/?format=api
{ "id": 813000, "url": "http://patchwork.ozlabs.org/api/patches/813000/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-9-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-9-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:13:55", "name": "[08/19] nvic: Handle banked exceptions in nvic_recompute_state()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d34d421432177a4ccde785fc6b2734718cb4b725", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-9-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813000/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813000/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCqP2R61z9t2S\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:24:01 +1000 (AEST)", "from localhost ([::1]:37998 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drpqp-0004Ak-A7\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:23:59 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43478)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph4-0003Tz-3N\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:56 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph1-0006S0-Uj\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:54 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37298)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgw-0006Mo-0k; Tue, 12 Sep 2017 14:13:46 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgv-000162-0H; Tue, 12 Sep 2017 19:13:45 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:13:55 +0100", "Message-Id": "<1505240046-11454-9-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 08/19] nvic: Handle banked exceptions in\n\tnvic_recompute_state()", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Update the nvic_recompute_state() code to handle the security\nextension and its associated banked registers.\n\nCode that uses the resulting cached state (ie the irq\nacknowledge and complete code) will be updated in a later\ncommit.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/intc/armv7m_nvic.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++--\n hw/intc/trace-events | 1 +\n 2 files changed, 147 insertions(+), 5 deletions(-)", "diff": "diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex b97dbe3..fb824e6 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -54,6 +54,8 @@\n * (higher than the highest possible priority value)\n */\n #define NVIC_NOEXC_PRIO 0x100\n+/* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */\n+#define NVIC_NS_PRIO_LIMIT 0x80\n \n static const uint8_t nvic_id[] = {\n 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1\n@@ -126,13 +128,139 @@ static bool nvic_isrpending(NVICState *s)\n return false;\n }\n \n+static bool exc_is_banked(int exc)\n+{\n+ /* Return true if this is one of the limited set of exceptions which\n+ * are banked (and thus have state in sec_vectors[])\n+ */\n+ return exc == ARMV7M_EXCP_HARD ||\n+ exc == ARMV7M_EXCP_MEM ||\n+ exc == ARMV7M_EXCP_USAGE ||\n+ exc == ARMV7M_EXCP_SVC ||\n+ exc == ARMV7M_EXCP_PENDSV ||\n+ exc == ARMV7M_EXCP_SYSTICK;\n+}\n+\n /* Return a mask word which clears the subpriority bits from\n * a priority value for an M-profile exception, leaving only\n * the group priority.\n */\n-static inline uint32_t nvic_gprio_mask(NVICState *s)\n+static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)\n+{\n+ return ~0U << (s->prigroup[secure] + 1);\n+}\n+\n+static bool exc_targets_secure(NVICState *s, int exc)\n+{\n+ /* Return true if this non-banked exception targets Secure state. */\n+ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {\n+ return false;\n+ }\n+\n+ if (exc >= NVIC_FIRST_IRQ) {\n+ return !s->itns[exc];\n+ }\n+\n+ /* Function shouldn't be called for banked exceptions. */\n+ assert(!exc_is_banked(exc));\n+\n+ switch (exc) {\n+ case ARMV7M_EXCP_NMI:\n+ case ARMV7M_EXCP_BUS:\n+ return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);\n+ case ARMV7M_EXCP_SECURE:\n+ return true;\n+ case ARMV7M_EXCP_DEBUG:\n+ /* TODO: controlled by DEMCR.SDME, which we don't yet implement */\n+ return false;\n+ default:\n+ /* reset, and reserved (unused) low exception numbers.\n+ * We'll get called by code that loops through all the exception\n+ * numbers, but it doesn't matter what we return here as these\n+ * non-existent exceptions will never be pended or active.\n+ */\n+ return true;\n+ }\n+}\n+\n+static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)\n+{\n+ /* Return the group priority for this exception, given its raw\n+ * (group-and-subgroup) priority value and whether it is targeting\n+ * secure state or not.\n+ */\n+ if (rawprio < 0) {\n+ return rawprio;\n+ }\n+ rawprio &= nvic_gprio_mask(s, targets_secure);\n+ /* AIRCR.PRIS causes us to squash all NS priorities into the\n+ * lower half of the total range\n+ */\n+ if (!targets_secure &&\n+ (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {\n+ rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;\n+ }\n+ return rawprio;\n+}\n+\n+/* Recompute vectpending and exception_prio for a CPU which implements\n+ * the Security extension\n+ */\n+static void nvic_recompute_state_secure(NVICState *s)\n {\n- return ~0U << (s->prigroup[M_REG_NS] + 1);\n+ int i, bank;\n+ int pend_prio = NVIC_NOEXC_PRIO;\n+ int active_prio = NVIC_NOEXC_PRIO;\n+ int pend_irq = 0;\n+ bool pending_is_s_banked = false;\n+\n+ /* R_CQRV: precedence is by:\n+ * - lowest group priority; if both the same then\n+ * - lowest subpriority; if both the same then\n+ * - lowest exception number; if both the same (ie banked) then\n+ * - secure exception takes precedence\n+ * Compare pseudocode RawExecutionPriority.\n+ * Annoyingly, now we have two prigroup values (for S and NS)\n+ * we can't do the loop comparison on raw priority values.\n+ */\n+ for (i = 1; i < s->num_irq; i++) {\n+ for (bank = M_REG_S; bank >= M_REG_NS; bank--) {\n+ VecInfo *vec;\n+ int prio;\n+ bool targets_secure;\n+\n+ if (bank == M_REG_S) {\n+ if (!exc_is_banked(i)) {\n+ continue;\n+ }\n+ vec = &s->sec_vectors[i];\n+ targets_secure = true;\n+ } else {\n+ vec = &s->vectors[i];\n+ targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);\n+ }\n+\n+ prio = exc_group_prio(s, vec->prio, targets_secure);\n+ if (vec->enabled && vec->pending && prio < pend_prio) {\n+ pend_prio = prio;\n+ pend_irq = i;\n+ pending_is_s_banked = (bank == M_REG_S);\n+ }\n+ if (vec->active && prio < active_prio) {\n+ active_prio = prio;\n+ }\n+ }\n+ }\n+\n+ s->vectpending_is_s_banked = pending_is_s_banked;\n+ s->vectpending = pend_irq;\n+ s->vectpending_prio = pend_prio;\n+ s->exception_prio = active_prio;\n+\n+ trace_nvic_recompute_state_secure(s->vectpending,\n+ s->vectpending_is_s_banked,\n+ s->vectpending_prio,\n+ s->exception_prio);\n }\n \n /* Recompute vectpending and exception_prio */\n@@ -143,6 +271,18 @@ static void nvic_recompute_state(NVICState *s)\n int active_prio = NVIC_NOEXC_PRIO;\n int pend_irq = 0;\n \n+ /* In theory we could write one function that handled both\n+ * the \"security extension present\" and \"not present\"; however\n+ * the security related changes significantly complicate the\n+ * recomputation just by themselves and mixing both cases together\n+ * would be even worse, so we retain a separate non-secure-only\n+ * version for CPUs which don't implement the security extension.\n+ */\n+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {\n+ nvic_recompute_state_secure(s);\n+ return;\n+ }\n+\n for (i = 1; i < s->num_irq; i++) {\n VecInfo *vec = &s->vectors[i];\n \n@@ -156,11 +296,11 @@ static void nvic_recompute_state(NVICState *s)\n }\n \n if (active_prio > 0) {\n- active_prio &= nvic_gprio_mask(s);\n+ active_prio &= nvic_gprio_mask(s, false);\n }\n \n if (pend_prio > 0) {\n- pend_prio &= nvic_gprio_mask(s);\n+ pend_prio &= nvic_gprio_mask(s, false);\n }\n \n s->vectpending = pend_irq;\n@@ -186,7 +326,8 @@ static inline int nvic_exec_prio(NVICState *s)\n } else if (env->v7m.primask[env->v7m.secure]) {\n running = 0;\n } else if (env->v7m.basepri[env->v7m.secure] > 0) {\n- running = env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s);\n+ running = env->v7m.basepri[env->v7m.secure] &\n+ nvic_gprio_mask(s, env->v7m.secure);\n } else {\n running = NVIC_NOEXC_PRIO; /* lower than any possible priority */\n }\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 5635a5f..0b1fba3 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -168,6 +168,7 @@ gicv3_redist_send_sgi(uint32_t cpu, int irq) \"GICv3 redistributor 0x%x pending S\n \n # hw/intc/armv7m_nvic.c\n nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) \"NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d\"\n+nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) \"NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d\"\n nvic_set_prio(int irq, uint8_t prio) \"NVIC set irq %d priority %d\"\n nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) \"NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d\"\n nvic_escalate_prio(int irq, int irqprio, int runprio) \"NVIC escalating irq %d to HardFault: insufficient priority %d >= %d\"\n", "prefixes": [ "08/19" ] }