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GET /api/patches/812997/?format=api
{ "id": 812997, "url": "http://patchwork.ozlabs.org/api/patches/812997/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-13-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-13-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:13:59", "name": "[12/19] nvic: In escalation to HardFault, support HF not being priority -1", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a59c705b94965fdf56cd652b5cb756e245558381", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-13-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812997/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812997/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCmH3Zxzz9sP1\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:21:19 +1000 (AEST)", "from localhost ([::1]:37987 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drpoD-0001Pu-Fi\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:21:17 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43453)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph3-0003T5-GZ\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:55 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph2-0006S6-1y\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:53 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37310)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgy-0006PL-Mt; Tue, 12 Sep 2017 14:13:48 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgx-000180-Mu; Tue, 12 Sep 2017 19:13:47 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:13:59 +0100", "Message-Id": "<1505240046-11454-13-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 12/19] nvic: In escalation to HardFault,\n\tsupport HF not being priority -1", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "When escalating to HardFault, we must go into Lockup if we\ncan't take the synchronous HardFault because the current\nexecution priority is already at or below the priority of\nHardFault. In v7M HF is always priority -1 so a simple < 0\ncomparison sufficed; in v8M the priority of HardFault can\nvary depending on whether it is a Secure or NonSecure\nHardFault, so we must check against the priority of the\nHardFault exception vector we're about to use.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/intc/armv7m_nvic.c | 23 ++++++++++++-----------\n 1 file changed, 12 insertions(+), 11 deletions(-)", "diff": "diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 3361a28..c4670f7 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -487,18 +487,8 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)\n }\n \n if (escalate) {\n- if (running < 0) {\n- /* We want to escalate to HardFault but we can't take a\n- * synchronous HardFault at this point either. This is a\n- * Lockup condition due to a guest bug. We don't model\n- * Lockup, so report via cpu_abort() instead.\n- */\n- cpu_abort(&s->cpu->parent_obj,\n- \"Lockup: can't escalate %d to HardFault \"\n- \"(current priority %d)\\n\", irq, running);\n- }\n \n- /* We can do the escalation, so we take HardFault instead.\n+ /* We need to escalate this exception to a synchronous HardFault.\n * If BFHFNMINS is set then we escalate to the banked HF for\n * the target security state of the original exception; otherwise\n * we take a Secure HardFault.\n@@ -511,6 +501,17 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)\n } else {\n vec = &s->vectors[irq];\n }\n+ if (running <= vec->prio) {\n+ /* We want to escalate to HardFault but we can't take the\n+ * synchronous HardFault at this point either. This is a\n+ * Lockup condition due to a guest bug. We don't model\n+ * Lockup, so report via cpu_abort() instead.\n+ */\n+ cpu_abort(&s->cpu->parent_obj,\n+ \"Lockup: can't escalate %d to HardFault \"\n+ \"(current priority %d)\\n\", irq, running);\n+ }\n+\n /* HF may be banked but there is only one shared HFSR */\n s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;\n }\n", "prefixes": [ "12/19" ] }