Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/812993/?format=api
{ "id": 812993, "url": "http://patchwork.ozlabs.org/api/patches/812993/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-6-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-6-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:13:52", "name": "[05/19] nvic: Implement AIRCR changes for v8M", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b77ff9e123f6e79ed65ec2278874b5c551c393d1", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-6-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812993/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812993/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCht5J26z9sP1\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:18:21 +1000 (AEST)", "from localhost ([::1]:37966 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drplL-0006y2-C5\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:18:19 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43373)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph1-0003Qa-5X\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:53 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drpgz-0006Q9-4w\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:51 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37292)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgv-0006Ln-BH; Tue, 12 Sep 2017 14:13:45 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgs-00014J-RH; Tue, 12 Sep 2017 19:13:42 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:13:52 +0100", "Message-Id": "<1505240046-11454-6-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 05/19] nvic: Implement AIRCR changes for v8M", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "The Application Interrupt and Reset Control Register has some changes\nfor v8M:\n * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have\n real state if the security extension is implemented and otherwise\n are constant\n * the PRIGROUP field is banked between security states\n * non-secure code can be blocked from using the SYSRESET bit\n to reset the system if SYSRESETREQS is set\n\nImplement the new state and the changes to register read and write.\nFor the moment we ignore the effects of the secure PRIGROUP.\nWe will implement the effects of PRIS and BFHFNMIS later.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n include/hw/intc/armv7m_nvic.h | 3 ++-\n target/arm/cpu.h | 12 +++++++++++\n hw/intc/armv7m_nvic.c | 49 +++++++++++++++++++++++++++++++++----------\n target/arm/cpu.c | 7 +++++++\n 4 files changed, 59 insertions(+), 12 deletions(-)", "diff": "diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h\nindex 329774e..e96e488 100644\n--- a/include/hw/intc/armv7m_nvic.h\n+++ b/include/hw/intc/armv7m_nvic.h\n@@ -55,7 +55,8 @@ typedef struct NVICState {\n * Entries in sec_vectors[] for non-banked exception numbers are unused.\n */\n VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];\n- uint32_t prigroup;\n+ /* The PRIGROUP field in AIRCR is banked */\n+ uint32_t prigroup[M_REG_NUM_BANKS];\n \n /* The following fields are all cached state that can be recalculated\n * from the vectors[] and sec_vectors[] arrays and the prigroup field:\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 5a1f957..7e661c8 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -449,6 +449,7 @@ typedef struct CPUARMState {\n int exception;\n uint32_t primask[M_REG_NUM_BANKS];\n uint32_t faultmask[M_REG_NUM_BANKS];\n+ uint32_t aircr; /* only holds r/w state if security extn implemented */\n uint32_t secure; /* Is CPU in Secure state? (not guest visible) */\n } v7m;\n \n@@ -1200,6 +1201,17 @@ FIELD(V7M_CCR, STKALIGN, 9, 1)\n FIELD(V7M_CCR, DC, 16, 1)\n FIELD(V7M_CCR, IC, 17, 1)\n \n+/* V7M AIRCR bits */\n+FIELD(V7M_AIRCR, VECTRESET, 0, 1)\n+FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)\n+FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)\n+FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)\n+FIELD(V7M_AIRCR, PRIGROUP, 8, 3)\n+FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)\n+FIELD(V7M_AIRCR, PRIS, 14, 1)\n+FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)\n+FIELD(V7M_AIRCR, VECTKEY, 16, 16)\n+\n /* V7M CFSR bits for MMFSR */\n FIELD(V7M_CFSR, IACCVIOL, 0, 1)\n FIELD(V7M_CFSR, DACCVIOL, 1, 1)\ndiff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 8388d64..585b1a7 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -129,7 +129,7 @@ static bool nvic_isrpending(NVICState *s)\n */\n static inline uint32_t nvic_gprio_mask(NVICState *s)\n {\n- return ~0U << (s->prigroup + 1);\n+ return ~0U << (s->prigroup[M_REG_NS] + 1);\n }\n \n /* Recompute vectpending and exception_prio */\n@@ -451,8 +451,21 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)\n return val;\n case 0xd08: /* Vector Table Offset. */\n return cpu->env.v7m.vecbase[attrs.secure];\n- case 0xd0c: /* Application Interrupt/Reset Control. */\n- return 0xfa050000 | (s->prigroup << 8);\n+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */\n+ val = 0xfa050000 | (s->prigroup[attrs.secure] << 8);\n+ if (attrs.secure) {\n+ /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */\n+ val |= cpu->env.v7m.aircr;\n+ } else {\n+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If\n+ * security isn't supported then BFHFNMINS is RAO (and\n+ * the bit in env.v7m.aircr is always set).\n+ */\n+ val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK;\n+ }\n+ }\n+ return val;\n case 0xd10: /* System Control. */\n /* TODO: Implement SLEEPONEXIT. */\n return 0;\n@@ -660,22 +673,35 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n case 0xd08: /* Vector Table Offset. */\n cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80;\n break;\n- case 0xd0c: /* Application Interrupt/Reset Control. */\n- if ((value >> 16) == 0x05fa) {\n- if (value & 4) {\n- qemu_irq_pulse(s->sysresetreq);\n+ case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */\n+ if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) {\n+ if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {\n+ if (attrs.secure ||\n+ !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {\n+ qemu_irq_pulse(s->sysresetreq);\n+ }\n }\n- if (value & 2) {\n+ if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {\n qemu_log_mask(LOG_GUEST_ERROR,\n \"Setting VECTCLRACTIVE when not in DEBUG mode \"\n \"is UNPREDICTABLE\\n\");\n }\n- if (value & 1) {\n+ if (value & R_V7M_AIRCR_VECTRESET_MASK) {\n+ /* NB: this bit is RES0 in v8M */\n qemu_log_mask(LOG_GUEST_ERROR,\n \"Setting VECTRESET when not in DEBUG mode \"\n \"is UNPREDICTABLE\\n\");\n }\n- s->prigroup = extract32(value, 8, 3);\n+ s->prigroup[attrs.secure] = extract32(value,\n+ R_V7M_AIRCR_PRIGROUP_SHIFT,\n+ R_V7M_AIRCR_PRIGROUP_LENGTH);\n+ if (attrs.secure) {\n+ /* These bits are only writable by secure */\n+ cpu->env.v7m.aircr = value &\n+ (R_V7M_AIRCR_SYSRESETREQS_MASK |\n+ R_V7M_AIRCR_BFHFNMINS_MASK |\n+ R_V7M_AIRCR_PRIS_MASK);\n+ }\n nvic_irq_update(s);\n }\n break;\n@@ -1193,6 +1219,7 @@ static const VMStateDescription vmstate_nvic_security = {\n .fields = (VMStateField[]) {\n VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,\n vmstate_VecInfo, VecInfo),\n+ VMSTATE_UINT32(prigroup[M_REG_S], NVICState),\n VMSTATE_END_OF_LIST()\n }\n };\n@@ -1205,7 +1232,7 @@ static const VMStateDescription vmstate_nvic = {\n .fields = (VMStateField[]) {\n VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,\n vmstate_VecInfo, VecInfo),\n- VMSTATE_UINT32(prigroup, NVICState),\n+ VMSTATE_UINT32(prigroup[M_REG_NS], NVICState),\n VMSTATE_END_OF_LIST()\n }\n };\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 412e94c..6ee169d 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -187,6 +187,13 @@ static void arm_cpu_reset(CPUState *s)\n \n if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n env->v7m.secure = true;\n+ } else {\n+ /* This bit resets to 0 if security is supported, but 1 if\n+ * it is not. The bit is not present in v7M, but we set it\n+ * here so we can avoid having to make checks on it conditional\n+ * on ARM_FEATURE_V8 (we don't let the guest see the bit).\n+ */\n+ env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;\n }\n \n /* In v7M the reset value of this bit is IMPDEF, but ARM recommends\n", "prefixes": [ "05/19" ] }