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GET /api/patches/812991/?format=api
{ "id": 812991, "url": "http://patchwork.ozlabs.org/api/patches/812991/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-15-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-15-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:14:01", "name": "[14/19] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "feb670eeece37e5bbf4d349663c819028a04b3d6", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-15-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812991/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812991/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsChJ1kN5z9sNV\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:17:52 +1000 (AEST)", "from localhost ([::1]:37960 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drpks-0006Um-6z\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:17:50 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43498)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph4-0003UT-EM\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:55 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph2-0006Sc-Lh\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:54 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37316)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drph0-0006QF-2W; Tue, 12 Sep 2017 14:13:50 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgz-00019A-1C; Tue, 12 Sep 2017 19:13:49 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:14:01 +0100", "Message-Id": "<1505240046-11454-15-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 14/19] nvic: Disable the non-secure HardFault\n\tif AIRCR.BFHFNMINS is clear", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault\ncan still be pended via SHCSR.HARDFAULTPENDED it mustn't actually\npreempt execution. The simple way to achieve this is to clear the\nenable bit for it, since the enable bit isn't guest visible.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/intc/armv7m_nvic.c | 12 ++++++++++--\n 1 file changed, 10 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex db2f170..91d2f33 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -937,11 +937,16 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n (R_V7M_AIRCR_SYSRESETREQS_MASK |\n R_V7M_AIRCR_BFHFNMINS_MASK |\n R_V7M_AIRCR_PRIS_MASK);\n- /* BFHFNMINS changes the priority of Secure HardFault */\n+ /* BFHFNMINS changes the priority of Secure HardFault, and\n+ * allows a pending Non-secure HardFault to preempt (which\n+ * we implement by marking it enabled).\n+ */\n if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {\n s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;\n+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;\n } else {\n s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;\n+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;\n }\n }\n nvic_irq_update(s);\n@@ -1562,7 +1567,6 @@ static void armv7m_nvic_reset(DeviceState *dev)\n NVICState *s = NVIC(dev);\n \n s->vectors[ARMV7M_EXCP_NMI].enabled = 1;\n- s->vectors[ARMV7M_EXCP_HARD].enabled = 1;\n /* MEM, BUS, and USAGE are enabled through\n * the System Handler Control register\n */\n@@ -1584,6 +1588,10 @@ static void armv7m_nvic_reset(DeviceState *dev)\n \n /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */\n s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;\n+ /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */\n+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;\n+ } else {\n+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;\n }\n \n /* Strictly speaking the reset handler should be enabled.\n", "prefixes": [ "14/19" ] }