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GET /api/patches/812984/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 812984,
    "url": "http://patchwork.ozlabs.org/api/patches/812984/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-7-git-send-email-peter.maydell@linaro.org/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1505240046-11454-7-git-send-email-peter.maydell@linaro.org>",
    "list_archive_url": null,
    "date": "2017-09-12T18:13:53",
    "name": "[06/19] nvic: Make ICSR.RETTOBASE handle banked exceptions",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "14eb7ada609310ece211f02d057cc213c9d2dab1",
    "submitter": {
        "id": 5111,
        "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api",
        "name": "Peter Maydell",
        "email": "peter.maydell@linaro.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-7-git-send-email-peter.maydell@linaro.org/mbox/",
    "series": [
        {
            "id": 2751,
            "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751",
            "date": "2017-09-12T18:13:53",
            "name": "ARMv8M: support security extn in the NVIC",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/812984/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/812984/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)",
        "Received": [
            "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCcY4j7Gz9sRg\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:14:37 +1000 (AEST)",
            "from localhost ([::1]:37935 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drphj-0003QA-AH\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:14:35 -0400",
            "from eggs.gnu.org ([2001:4830:134:3::10]:43278)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drpgy-0003Nb-8m\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:49 -0400",
            "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drpgx-0006OM-3M\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:48 -0400",
            "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37292)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgu-0006Ln-FK; Tue, 12 Sep 2017 14:13:44 -0400",
            "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgt-00014o-Hz; Tue, 12 Sep 2017 19:13:43 +0100"
        ],
        "From": "Peter Maydell <peter.maydell@linaro.org>",
        "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org",
        "Date": "Tue, 12 Sep 2017 19:13:53 +0100",
        "Message-Id": "<1505240046-11454-7-git-send-email-peter.maydell@linaro.org>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>",
        "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>",
        "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.",
        "X-Received-From": "2001:8b0:1d0::2",
        "Subject": "[Qemu-devel] [PATCH 06/19] nvic: Make ICSR.RETTOBASE handle banked\n\texceptions",
        "X-BeenThere": "qemu-devel@nongnu.org",
        "X-Mailman-Version": "2.1.21",
        "Precedence": "list",
        "List-Id": "<qemu-devel.nongnu.org>",
        "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>",
        "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>",
        "List-Post": "<mailto:qemu-devel@nongnu.org>",
        "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>",
        "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>",
        "Cc": "patches@linaro.org",
        "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org",
        "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>"
    },
    "content": "Update the code in nvic_rettobase() so that it checks the\nsec_vectors[] array as well as the vectors[] array if needed.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/intc/armv7m_nvic.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 585b1a7..edaf60c 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -84,9 +84,12 @@ static int nvic_pending_prio(NVICState *s)\n static bool nvic_rettobase(NVICState *s)\n {\n     int irq, nhand = 0;\n+    bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);\n \n     for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {\n-        if (s->vectors[irq].active) {\n+        if (s->vectors[irq].active ||\n+            (check_sec && irq < NVIC_INTERNAL_VECTORS &&\n+             s->sec_vectors[irq].active)) {\n             nhand++;\n             if (nhand == 2) {\n                 return 0;\n",
    "prefixes": [
        "06/19"
    ]
}