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GET /api/patches/812969/?format=api
{ "id": 812969, "url": "http://patchwork.ozlabs.org/api/patches/812969/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-17-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170912162513.21694-17-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-12T16:25:13", "name": "[v2,16/16] tcg/aarch64: Add vector operations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "05f00419712fac0abb0d8fba0a91dcfa91e20062", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-17-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2737, "url": "http://patchwork.ozlabs.org/api/series/2737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2737", "date": "2017-09-12T16:24:59", "name": "TCG vectorization and example conversion", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812969/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812969/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"dawv6mtr\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs9T472BPz9s7g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:38:00 +1000 (AEST)", "from localhost ([::1]:37030 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1droCF-00052D-37\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 12:37:59 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:38229)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro0M-0001y7-96\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:45 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro0J-0007CI-Di\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:42 -0400", "from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:37517)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dro0J-0007C0-2R\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:39 -0400", "by mail-pg0-x22b.google.com with SMTP id d8so22189894pgt.4\n\tfor <qemu-devel@nongnu.org>; Tue, 12 Sep 2017 09:25:38 -0700 (PDT)", "from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net.\n\t[97.126.103.167]) by smtp.gmail.com with ESMTPSA id\n\tb22sm20382140pfh.175.2017.09.12.09.25.36\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 12 Sep 2017 09:25:36 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=Revpy4uE5bdOi82L4qVMZbsXEwMBbKX/a7uzM3Um9Ko=;\n\tb=dawv6mtr8jwtzJIadXoKrz4iTYpLhpQOzxhdwEbv7F4DgEQ9UsVIrR76mAY1IzzSRK\n\tSjrWsLvTRwfmVNfgRX2lxJsMC0QoICg/yY4A34jJoF7h7PWvc/ZdF3bqbksMbyAK71TV\n\tkyZQzwLZi0HS8JHSDj/b6g8Y/GN6pmFj3z/Uo=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=Revpy4uE5bdOi82L4qVMZbsXEwMBbKX/a7uzM3Um9Ko=;\n\tb=dhbcorIfpySLB29K1g2zAqPYOTBWHiGLtdNE1ZeP81tBtnQjw0lxH3BN1jB5UD0Faf\n\tMsmVs2v/4eoBW8j8e+3Px/FSd/wRyRJ8gP+Ti3wqU6eT/TKKMMZLlf6PE4G+WAPuELCU\n\tG5bjqcKcD1VuIKsXolhlAOsyxfw814YJy8iPT61EHMaSJo5Emp6E9el4Kd5MVRLY9C/H\n\tHhmaOG3TM9eymuVLdxXqUeZhTPdMQFm/kIETLcqUaMm/U0q7hRtjRha57MoQNcjdU1xT\n\tE889/qxksNlu6b4I1vZcJKgP5k7qfG7zonnpoSeSWETCmEheTkz++ltSbVdb1CKVjMTE\n\tfLpA==", "X-Gm-Message-State": "AHPjjUgjPQURQLonj9fpoxsozMWcF/NgK1SM1/xIisTp1maDju+fANUj\n\tXG5K8LWfc3mjwaRD0kjc1A==", "X-Google-Smtp-Source": "ADKCNb7iIAbmnywK/Xlu4VaQLshbCTPKwcpsE4dmWsOOLNwJ7DKqiI9l3l1KNIj+PDxlvHBz7hZsew==", "X-Received": "by 10.98.60.220 with SMTP id b89mr15201435pfk.82.1505233537541; \n\tTue, 12 Sep 2017 09:25:37 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 09:25:13 -0700", "Message-Id": "<20170912162513.21694-17-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170912162513.21694-1-richard.henderson@linaro.org>", "References": "<20170912162513.21694-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22b", "Subject": "[Qemu-devel] [PATCH v2 16/16] tcg/aarch64: Add vector operations", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, f4bug@amsat.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n tcg/aarch64/tcg-target.h | 23 ++-\n tcg/aarch64/tcg-target.inc.c | 372 ++++++++++++++++++++++++++++++++++++++-----\n 2 files changed, 350 insertions(+), 45 deletions(-)", "diff": "diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h\nindex c2525066ab..310efa3c1d 100644\n--- a/tcg/aarch64/tcg-target.h\n+++ b/tcg/aarch64/tcg-target.h\n@@ -31,13 +31,22 @@ typedef enum {\n TCG_REG_SP = 31,\n TCG_REG_XZR = 31,\n \n+ TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,\n+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,\n+ TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,\n+ TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,\n+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,\n+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,\n+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,\n+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,\n+\n /* Aliases. */\n TCG_REG_FP = TCG_REG_X29,\n TCG_REG_LR = TCG_REG_X30,\n TCG_AREG0 = TCG_REG_X19,\n } TCGReg;\n \n-#define TCG_TARGET_NB_REGS 32\n+#define TCG_TARGET_NB_REGS 64\n \n /* used for function call generation */\n #define TCG_REG_CALL_STACK TCG_REG_SP\n@@ -113,6 +122,18 @@ typedef enum {\n #define TCG_TARGET_HAS_mulsh_i64 1\n #define TCG_TARGET_HAS_direct_jump 1\n \n+#define TCG_TARGET_HAS_v64 1\n+#define TCG_TARGET_HAS_andc_v64 1\n+#define TCG_TARGET_HAS_orc_v64 1\n+#define TCG_TARGET_HAS_not_v64 1\n+#define TCG_TARGET_HAS_neg_v64 1\n+\n+#define TCG_TARGET_HAS_v128 1\n+#define TCG_TARGET_HAS_andc_v128 1\n+#define TCG_TARGET_HAS_orc_v128 1\n+#define TCG_TARGET_HAS_not_v128 1\n+#define TCG_TARGET_HAS_neg_v128 1\n+\n #define TCG_TARGET_DEFAULT_MO (0)\n \n static inline void flush_icache_range(uintptr_t start, uintptr_t stop)\ndiff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c\nindex 150530f30e..a2419dcb0c 100644\n--- a/tcg/aarch64/tcg-target.inc.c\n+++ b/tcg/aarch64/tcg-target.inc.c\n@@ -20,10 +20,15 @@ QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);\n \n #ifdef CONFIG_DEBUG_TCG\n static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {\n- \"%x0\", \"%x1\", \"%x2\", \"%x3\", \"%x4\", \"%x5\", \"%x6\", \"%x7\",\n- \"%x8\", \"%x9\", \"%x10\", \"%x11\", \"%x12\", \"%x13\", \"%x14\", \"%x15\",\n- \"%x16\", \"%x17\", \"%x18\", \"%x19\", \"%x20\", \"%x21\", \"%x22\", \"%x23\",\n- \"%x24\", \"%x25\", \"%x26\", \"%x27\", \"%x28\", \"%fp\", \"%x30\", \"%sp\",\n+ \"x0\", \"x1\", \"x2\", \"x3\", \"x4\", \"x5\", \"x6\", \"x7\",\n+ \"x8\", \"x9\", \"x10\", \"x11\", \"x12\", \"x13\", \"x14\", \"x15\",\n+ \"x16\", \"x17\", \"x18\", \"x19\", \"x20\", \"x21\", \"x22\", \"x23\",\n+ \"x24\", \"x25\", \"x26\", \"x27\", \"x28\", \"fp\", \"x30\", \"sp\",\n+\n+ \"v0\", \"v1\", \"v2\", \"v3\", \"v4\", \"v5\", \"v6\", \"v7\",\n+ \"v8\", \"v9\", \"v10\", \"v11\", \"v12\", \"v13\", \"v14\", \"v15\",\n+ \"v16\", \"v17\", \"v18\", \"v19\", \"v20\", \"v21\", \"v22\", \"v23\",\n+ \"v24\", \"v25\", \"v26\", \"v27\", \"v28\", \"fp\", \"v30\", \"v31\",\n };\n #endif /* CONFIG_DEBUG_TCG */\n \n@@ -43,6 +48,14 @@ static const int tcg_target_reg_alloc_order[] = {\n /* X19 reserved for AREG0 */\n /* X29 reserved as fp */\n /* X30 reserved as temporary */\n+\n+ TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,\n+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,\n+ /* V8 - V15 are call-saved, and skipped. */\n+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,\n+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,\n+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,\n+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,\n };\n \n static const int tcg_target_call_iarg_regs[8] = {\n@@ -119,10 +132,14 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n const char *ct_str, TCGType type)\n {\n switch (*ct_str++) {\n- case 'r':\n+ case 'r': /* general registers */\n ct->ct |= TCG_CT_REG;\n ct->u.regs = 0xffffffffu;\n break;\n+ case 'w': /* advsimd registers */\n+ ct->ct |= TCG_CT_REG;\n+ ct->u.regs = 0xffffffff00000000ull;\n+ break;\n case 'l': /* qemu_ld / qemu_st address, data_reg */\n ct->ct |= TCG_CT_REG;\n ct->u.regs = 0xffffffffu;\n@@ -290,6 +307,12 @@ typedef enum {\n I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,\n I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,\n \n+ I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,\n+ I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,\n+\n+ I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,\n+ I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,\n+\n I3312_TO_I3310 = 0x00200800,\n I3312_TO_I3313 = 0x01000000,\n \n@@ -374,8 +397,33 @@ typedef enum {\n I3510_EON = 0x4a200000,\n I3510_ANDS = 0x6a000000,\n \n- NOP = 0xd503201f,\n+ /* AdvSIMD modified immediate */\n+ I3606_MOVI = 0x0f000400,\n+\n+ /* AdvSIMD three same. */\n+ I3616_ADD_B = 0x0e208400,\n+ I3616_ADD_H = 0x0e608400,\n+ I3616_ADD_S = 0x0ea08400,\n+ I3616_ADD_D = 0x4ee08400,\n+ I3616_AND = 0x0e201c00,\n+ I3616_BIC = 0x0e601c00,\n+ I3616_EOR = 0x2e201c00,\n+ I3616_ORR = 0x0ea01c00,\n+ I3616_ORN = 0x0ee01c00,\n+ I3616_SUB_B = 0x2e208400,\n+ I3616_SUB_H = 0x2e608400,\n+ I3616_SUB_S = 0x2ea08400,\n+ I3616_SUB_D = 0x6ee08400,\n+\n+ /* AdvSIMD two-reg misc. */\n+ I3617_NOT = 0x2e205800,\n+ I3617_NEG_B = 0x2e20b800,\n+ I3617_NEG_H = 0x2e60b800,\n+ I3617_NEG_S = 0x2ea0b800,\n+ I3617_NEG_D = 0x6ee0b800,\n+\n /* System instructions. */\n+ NOP = 0xd503201f,\n DMB_ISH = 0xd50338bf,\n DMB_LD = 0x00000100,\n DMB_ST = 0x00000200,\n@@ -520,26 +568,47 @@ static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,\n tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd);\n }\n \n+static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q,\n+ TCGReg rd, bool op, int cmode, uint8_t imm8)\n+{\n+ tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f)\n+ | (imm8 & 0xe0) << 16 | (imm8 & 0x1f) << 5);\n+}\n+\n+static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q,\n+ TCGReg rd, TCGReg rn, TCGReg rm)\n+{\n+ tcg_out32(s, insn | q << 30 | (rm & 0x1f) << 16\n+ | (rn & 0x1f) << 5 | (rd & 0x1f));\n+}\n+\n+static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q,\n+ TCGReg rd, TCGReg rn)\n+{\n+ tcg_out32(s, insn | q << 30 | (rn & 0x1f) << 5 | (rd & 0x1f));\n+}\n+\n static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,\n TCGReg rd, TCGReg base, TCGType ext,\n TCGReg regoff)\n {\n /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */\n tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |\n- 0x4000 | ext << 13 | base << 5 | rd);\n+ 0x4000 | ext << 13 | base << 5 | (rd & 0x1f));\n }\n \n static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,\n TCGReg rd, TCGReg rn, intptr_t offset)\n {\n- tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | rd);\n+ tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f));\n }\n \n static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn,\n TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)\n {\n /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */\n- tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10 | rn << 5 | rd);\n+ tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10\n+ | rn << 5 | (rd & 0x1f));\n }\n \n /* Register to register move using ORR (shifted register with no shift). */\n@@ -594,6 +663,24 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,\n int s0, s1;\n AArch64Insn opc;\n \n+ switch (type) {\n+ case TCG_TYPE_I32:\n+ case TCG_TYPE_I64:\n+ tcg_debug_assert(rd < 32);\n+ break;\n+\n+ case TCG_TYPE_V64:\n+ case TCG_TYPE_V128:\n+ tcg_debug_assert(rd >= 32);\n+ /* ??? Revisit this as the implementation progresses. */\n+ tcg_debug_assert(value == 0);\n+ tcg_out_insn(s, 3606, MOVI, 0, rd, 0, 0, 0);\n+ return;\n+\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n /* For 32-bit values, discard potential garbage in value. For 64-bit\n values within [2**31, 2**32-1], we can create smaller sequences by\n interpreting this as a negative 32-bit number, while ensuring that\n@@ -669,15 +756,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,\n /* Define something more legible for general use. */\n #define tcg_out_ldst_r tcg_out_insn_3310\n \n-static void tcg_out_ldst(TCGContext *s, AArch64Insn insn,\n- TCGReg rd, TCGReg rn, intptr_t offset)\n+static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,\n+ TCGReg rn, intptr_t offset, int lgsize)\n {\n- TCGMemOp size = (uint32_t)insn >> 30;\n-\n /* If the offset is naturally aligned and in range, then we can\n use the scaled uimm12 encoding */\n- if (offset >= 0 && !(offset & ((1 << size) - 1))) {\n- uintptr_t scaled_uimm = offset >> size;\n+ if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) {\n+ uintptr_t scaled_uimm = offset >> lgsize;\n if (scaled_uimm <= 0xfff) {\n tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm);\n return;\n@@ -695,32 +780,94 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn,\n tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);\n }\n \n-static inline void tcg_out_mov(TCGContext *s,\n- TCGType type, TCGReg ret, TCGReg arg)\n+static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)\n {\n- if (ret != arg) {\n+ if (ret == arg) {\n+ return;\n+ }\n+ switch (type) {\n+ case TCG_TYPE_I32:\n+ case TCG_TYPE_I64:\n+ tcg_debug_assert(ret < 32 && arg < 32);\n tcg_out_movr(s, type, ret, arg);\n+ break;\n+\n+ case TCG_TYPE_V64:\n+ tcg_debug_assert(ret >= 32 && arg >= 32);\n+ tcg_out_insn(s, 3616, ORR, 0, ret, arg, arg);\n+ break;\n+ case TCG_TYPE_V128:\n+ tcg_debug_assert(ret >= 32 && arg >= 32);\n+ tcg_out_insn(s, 3616, ORR, 1, ret, arg, arg);\n+ break;\n+\n+ default:\n+ g_assert_not_reached();\n }\n }\n \n-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,\n- TCGReg arg1, intptr_t arg2)\n+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,\n+ TCGReg arg1, intptr_t arg2)\n {\n- tcg_out_ldst(s, type == TCG_TYPE_I32 ? I3312_LDRW : I3312_LDRX,\n- arg, arg1, arg2);\n+ AArch64Insn insn;\n+ int lgsz;\n+\n+ switch (type) {\n+ case TCG_TYPE_I32:\n+ insn = I3312_LDRW;\n+ lgsz = 2;\n+ break;\n+ case TCG_TYPE_I64:\n+ insn = I3312_LDRX;\n+ lgsz = 3;\n+ break;\n+ case TCG_TYPE_V64:\n+ insn = I3312_LDRVD;\n+ lgsz = 3;\n+ break;\n+ case TCG_TYPE_V128:\n+ insn = I3312_LDRVQ;\n+ lgsz = 4;\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+ tcg_out_ldst(s, insn, arg, arg1, arg2, lgsz);\n }\n \n-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,\n- TCGReg arg1, intptr_t arg2)\n+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,\n+ TCGReg arg1, intptr_t arg2)\n {\n- tcg_out_ldst(s, type == TCG_TYPE_I32 ? I3312_STRW : I3312_STRX,\n- arg, arg1, arg2);\n+ AArch64Insn insn;\n+ int lgsz;\n+\n+ switch (type) {\n+ case TCG_TYPE_I32:\n+ insn = I3312_STRW;\n+ lgsz = 2;\n+ break;\n+ case TCG_TYPE_I64:\n+ insn = I3312_STRX;\n+ lgsz = 3;\n+ break;\n+ case TCG_TYPE_V64:\n+ insn = I3312_STRVD;\n+ lgsz = 3;\n+ break;\n+ case TCG_TYPE_V128:\n+ insn = I3312_STRVQ;\n+ lgsz = 4;\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+ tcg_out_ldst(s, insn, arg, arg1, arg2, lgsz);\n }\n \n static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,\n TCGReg base, intptr_t ofs)\n {\n- if (val == 0) {\n+ if (type <= TCG_TYPE_I64 && val == 0) {\n tcg_out_st(s, type, TCG_REG_XZR, base, ofs);\n return true;\n }\n@@ -1210,14 +1357,15 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,\n /* Merge \"low bits\" from tlb offset, load the tlb comparator into X0.\n X0 = load [X2 + (tlb_offset & 0x000fff)] */\n tcg_out_ldst(s, TARGET_LONG_BITS == 32 ? I3312_LDRW : I3312_LDRX,\n- TCG_REG_X0, TCG_REG_X2, tlb_offset & 0xfff);\n+ TCG_REG_X0, TCG_REG_X2, tlb_offset & 0xfff,\n+ TARGET_LONG_BITS == 32 ? 2 : 3);\n \n /* Load the tlb addend. Do that early to avoid stalling.\n X1 = load [X2 + (tlb_offset & 0xfff) + offsetof(addend)] */\n tcg_out_ldst(s, I3312_LDRX, TCG_REG_X1, TCG_REG_X2,\n (tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) -\n (is_read ? offsetof(CPUTLBEntry, addr_read)\n- : offsetof(CPUTLBEntry, addr_write)));\n+ : offsetof(CPUTLBEntry, addr_write)), 3);\n \n /* Perform the address comparison. */\n tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0);\n@@ -1435,49 +1583,49 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,\n \n case INDEX_op_ld8u_i32:\n case INDEX_op_ld8u_i64:\n- tcg_out_ldst(s, I3312_LDRB, a0, a1, a2);\n+ tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0);\n break;\n case INDEX_op_ld8s_i32:\n- tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2);\n+ tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0);\n break;\n case INDEX_op_ld8s_i64:\n- tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2);\n+ tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0);\n break;\n case INDEX_op_ld16u_i32:\n case INDEX_op_ld16u_i64:\n- tcg_out_ldst(s, I3312_LDRH, a0, a1, a2);\n+ tcg_out_ldst(s, I3312_LDRH, a0, a1, a2, 1);\n break;\n case INDEX_op_ld16s_i32:\n- tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2);\n+ tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2, 1);\n break;\n case INDEX_op_ld16s_i64:\n- tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2);\n+ tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2, 1);\n break;\n case INDEX_op_ld_i32:\n case INDEX_op_ld32u_i64:\n- tcg_out_ldst(s, I3312_LDRW, a0, a1, a2);\n+ tcg_out_ldst(s, I3312_LDRW, a0, a1, a2, 2);\n break;\n case INDEX_op_ld32s_i64:\n- tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2);\n+ tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2, 2);\n break;\n case INDEX_op_ld_i64:\n- tcg_out_ldst(s, I3312_LDRX, a0, a1, a2);\n+ tcg_out_ldst(s, I3312_LDRX, a0, a1, a2, 3);\n break;\n \n case INDEX_op_st8_i32:\n case INDEX_op_st8_i64:\n- tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2);\n+ tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0);\n break;\n case INDEX_op_st16_i32:\n case INDEX_op_st16_i64:\n- tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2);\n+ tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1);\n break;\n case INDEX_op_st_i32:\n case INDEX_op_st32_i64:\n- tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2);\n+ tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2);\n break;\n case INDEX_op_st_i64:\n- tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2);\n+ tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3);\n break;\n \n case INDEX_op_add_i32:\n@@ -1774,13 +1922,93 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,\n tcg_out_mb(s, a0);\n break;\n \n+ case INDEX_op_ld_v64:\n+ tcg_out_ldst(s, I3312_LDRVD, a0, a1, a2, 3);\n+ break;\n+ case INDEX_op_ld_v128:\n+ tcg_out_ldst(s, I3312_LDRVQ, a0, a1, a2, 4);\n+ break;\n+ case INDEX_op_st_v64:\n+ tcg_out_ldst(s, I3312_STRVD, a0, a1, a2, 3);\n+ break;\n+ case INDEX_op_st_v128:\n+ tcg_out_ldst(s, I3312_STRVQ, a0, a1, a2, 4);\n+ break;\n+\n+#define VOP(NAME) case INDEX_op_##NAME##_v128: ext = 1; /* fallthru */ \\\n+ case INDEX_op_##NAME##_v64\n+\n+ VOP(add8):\n+ tcg_out_insn(s, 3616, ADD_B, ext, a0, a1, a2);\n+ break;\n+ VOP(add16):\n+ tcg_out_insn(s, 3616, ADD_H, ext, a0, a1, a2);\n+ break;\n+ VOP(add32):\n+ tcg_out_insn(s, 3616, ADD_S, ext, a0, a1, a2);\n+ break;\n+ case INDEX_op_add64_v128:\n+ tcg_out_insn(s, 3616, ADD_D, 1, a0, a1, a2);\n+ break;\n+\n+ VOP(sub8):\n+ tcg_out_insn(s, 3616, SUB_B, ext, a0, a1, a2);\n+ break;\n+ VOP(sub16):\n+ tcg_out_insn(s, 3616, SUB_H, ext, a0, a1, a2);\n+ break;\n+ VOP(sub32):\n+ tcg_out_insn(s, 3616, SUB_S, ext, a0, a1, a2);\n+ break;\n+ case INDEX_op_sub64_v128:\n+ tcg_out_insn(s, 3616, SUB_D, 1, a0, a1, a2);\n+ break;\n+\n+ VOP(neg8):\n+ tcg_out_insn(s, 3617, NEG_B, ext, a0, a1);\n+ break;\n+ VOP(neg16):\n+ tcg_out_insn(s, 3617, NEG_H, ext, a0, a1);\n+ break;\n+ VOP(neg32):\n+ tcg_out_insn(s, 3617, NEG_S, ext, a0, a1);\n+ break;\n+ case INDEX_op_neg64_v128:\n+ tcg_out_insn(s, 3617, NEG_D, 1, a0, a1);\n+ break;\n+\n+ VOP(and):\n+ tcg_out_insn(s, 3616, AND, ext, a0, a1, a2);\n+ break;\n+ VOP(or):\n+ tcg_out_insn(s, 3616, ORR, ext, a0, a1, a2);\n+ break;\n+ VOP(xor):\n+ tcg_out_insn(s, 3616, EOR, ext, a0, a1, a2);\n+ break;\n+ VOP(andc):\n+ tcg_out_insn(s, 3616, BIC, ext, a0, a1, a2);\n+ break;\n+ VOP(orc):\n+ tcg_out_insn(s, 3616, ORN, ext, a0, a1, a2);\n+ break;\n+ VOP(not):\n+ tcg_out_insn(s, 3617, NOT, ext, a0, a1);\n+ break;\n+\n+#undef VOP\n+\n case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */\n case INDEX_op_mov_i64:\n+ case INDEX_op_mov_v64:\n+ case INDEX_op_mov_v128:\n case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */\n case INDEX_op_movi_i64:\n+ case INDEX_op_movi_v64:\n+ case INDEX_op_movi_v128:\n case INDEX_op_call: /* Always emitted via tcg_out_call. */\n default:\n- tcg_abort();\n+ g_assert_not_reached();\n }\n \n #undef REG0\n@@ -1790,11 +2018,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n {\n static const TCGTargetOpDef r = { .args_ct_str = { \"r\" } };\n static const TCGTargetOpDef r_r = { .args_ct_str = { \"r\", \"r\" } };\n+ static const TCGTargetOpDef w_w = { .args_ct_str = { \"w\", \"w\" } };\n+ static const TCGTargetOpDef w_r = { .args_ct_str = { \"w\", \"r\" } };\n static const TCGTargetOpDef r_l = { .args_ct_str = { \"r\", \"l\" } };\n static const TCGTargetOpDef r_rA = { .args_ct_str = { \"r\", \"rA\" } };\n static const TCGTargetOpDef rZ_r = { .args_ct_str = { \"rZ\", \"r\" } };\n static const TCGTargetOpDef lZ_l = { .args_ct_str = { \"lZ\", \"l\" } };\n static const TCGTargetOpDef r_r_r = { .args_ct_str = { \"r\", \"r\", \"r\" } };\n+ static const TCGTargetOpDef w_w_w = { .args_ct_str = { \"w\", \"w\", \"w\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n static const TCGTargetOpDef r_r_rA = { .args_ct_str = { \"r\", \"r\", \"rA\" } };\n static const TCGTargetOpDef r_r_rL = { .args_ct_str = { \"r\", \"r\", \"rL\" } };\n@@ -1938,6 +2169,49 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_sub2_i64:\n return &add2;\n \n+ case INDEX_op_add8_v64:\n+ case INDEX_op_add16_v64:\n+ case INDEX_op_add32_v64:\n+ case INDEX_op_add8_v128:\n+ case INDEX_op_add16_v128:\n+ case INDEX_op_add32_v128:\n+ case INDEX_op_add64_v128:\n+ case INDEX_op_sub8_v64:\n+ case INDEX_op_sub16_v64:\n+ case INDEX_op_sub32_v64:\n+ case INDEX_op_sub8_v128:\n+ case INDEX_op_sub16_v128:\n+ case INDEX_op_sub32_v128:\n+ case INDEX_op_sub64_v128:\n+ case INDEX_op_and_v64:\n+ case INDEX_op_and_v128:\n+ case INDEX_op_or_v64:\n+ case INDEX_op_or_v128:\n+ case INDEX_op_xor_v64:\n+ case INDEX_op_xor_v128:\n+ case INDEX_op_andc_v64:\n+ case INDEX_op_andc_v128:\n+ case INDEX_op_orc_v64:\n+ case INDEX_op_orc_v128:\n+ return &w_w_w;\n+\n+ case INDEX_op_not_v64:\n+ case INDEX_op_not_v128:\n+ case INDEX_op_neg8_v64:\n+ case INDEX_op_neg16_v64:\n+ case INDEX_op_neg32_v64:\n+ case INDEX_op_neg8_v128:\n+ case INDEX_op_neg16_v128:\n+ case INDEX_op_neg32_v128:\n+ case INDEX_op_neg64_v128:\n+ return &w_w;\n+\n+ case INDEX_op_ld_v64:\n+ case INDEX_op_ld_v128:\n+ case INDEX_op_st_v64:\n+ case INDEX_op_st_v128:\n+ return &w_r;\n+\n default:\n return NULL;\n }\n@@ -1947,8 +2221,10 @@ static void tcg_target_init(TCGContext *s)\n {\n tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;\n tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;\n+ tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;\n+ tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;\n \n- tcg_target_call_clobber_regs = 0xfffffffu;\n+ tcg_target_call_clobber_regs = -1ull;\n tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19);\n tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20);\n tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21);\n@@ -1960,6 +2236,14 @@ static void tcg_target_init(TCGContext *s)\n tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27);\n tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28);\n tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15);\n \n s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);\n", "prefixes": [ "v2", "16/16" ] }