Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/812968/?format=api
{ "id": 812968, "url": "http://patchwork.ozlabs.org/api/patches/812968/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-15-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170912162513.21694-15-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-12T16:25:11", "name": "[v2,14/16] tcg: Remove tcg_regset_set32", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "620fb7e2cb03784022920d8227c1d4c4e9c6edcc", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-15-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2737, "url": "http://patchwork.ozlabs.org/api/series/2737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2737", "date": "2017-09-12T16:24:59", "name": "TCG vectorization and example conversion", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812968/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812968/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"ZsFp2TuH\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs9SY28Msz9s7g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:37:33 +1000 (AEST)", "from localhost ([::1]:37029 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1droBn-0004YG-CC\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 12:37:31 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:38203)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro0J-0001vG-Oi\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:42 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro0G-0007Au-Tf\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:39 -0400", "from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:33743)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dro0G-0007AM-KH\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:36 -0400", "by mail-pg0-x22c.google.com with SMTP id u18so5584034pgo.0\n\tfor <qemu-devel@nongnu.org>; Tue, 12 Sep 2017 09:25:36 -0700 (PDT)", "from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net.\n\t[97.126.103.167]) by smtp.gmail.com with ESMTPSA id\n\tb22sm20382140pfh.175.2017.09.12.09.25.33\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 12 Sep 2017 09:25:34 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=ByrsgJ8FtPrTiASw92OO8jQubvxKAZodnvnQPQHSMTM=;\n\tb=ZsFp2TuH9MnQ7kuey8rTzb+jjwia/9hxtUmvkjPD8ZOHJtWxI2QRmUsEk+gl9FyzGZ\n\tkYG6VSw9bE3h50l2wcAuqwsRHPLj52OhP/1mdDbrt72CRvhwhB/LeuJHGwqHbIInoX5+\n\tOHPf9LdAH3BI1b0ArdP8xzaYz/sNQGgCEsxQo=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=ByrsgJ8FtPrTiASw92OO8jQubvxKAZodnvnQPQHSMTM=;\n\tb=RO4ly7dJK1DihFWnJi5/AIo5qxOOgrFxytcWTibWdUHihPoTTnbaDsweQHhhlq+Njv\n\t0P6i0A1eot8fjFhcrnQwNt7atYxZm8Rn3N4N6oT1HAMerSfDqtPK2rgNoJNFnd6Pyxd+\n\tIhspPr0bfFkQZb4Vkubmv0DNorHi9GnnoG4qbJ4+HiLCaZ5eVll/rbghnEkr+Gn5Phiq\n\tNI2V2g/n3T4DRXT8uDwgHtSn8W1dhmMn2KX3y+fQsF6xsdp/L6OVV3CvXJA0hhthr9v3\n\tbzYBZk/owceDB3bzLMrbdnYsUpdF3eBjIJRyZi4DSjzXvjVoYzARdoH1nWCiH40ayt2t\n\tOxGQ==", "X-Gm-Message-State": "AHPjjUg3CTazA/ryAQuvzVCtOLJPjeGvztliCj4l6UmOxmWiWKJL3ycH\n\tYXJ8OQzDALV4zkQsJFFmng==", "X-Google-Smtp-Source": "ADKCNb5AmL1RquRpvVOalwUV84liy4isqe4sNh5O7gOIgdMFED9Eg9UZt4ttleFMazcrKJuG77HvQw==", "X-Received": "by 10.98.236.198 with SMTP id e67mr15302570pfm.157.1505233535031;\n\tTue, 12 Sep 2017 09:25:35 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 09:25:11 -0700", "Message-Id": "<20170912162513.21694-15-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170912162513.21694-1-richard.henderson@linaro.org>", "References": "<20170912162513.21694-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22c", "Subject": "[Qemu-devel] [PATCH v2 14/16] tcg: Remove tcg_regset_set32", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, f4bug@amsat.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "It's not even clear what the interface REG and VAL32 were supposed to mean.\nAll uses had REG = 0 and VAL32 was the bitset assigned to the destination.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n tcg/tcg.h | 1 -\n tcg/aarch64/tcg-target.inc.c | 33 +++++++++++++++---------------\n tcg/arm/tcg-target.inc.c | 23 +++++++++++----------\n tcg/i386/tcg-target.inc.c | 34 ++++++++++---------------------\n tcg/ppc/tcg-target.inc.c | 37 +++++++++++++++++-----------------\n tcg/s390/tcg-target.inc.c | 14 ++++++-------\n tcg/sparc/tcg-target.inc.c | 48 ++++++++++++++++++++++----------------------\n tcg/tci/tcg-target.inc.c | 11 ++++------\n 8 files changed, 94 insertions(+), 107 deletions(-)", "diff": "diff --git a/tcg/tcg.h b/tcg/tcg.h\nindex 8b4208ea03..d4412102ba 100644\n--- a/tcg/tcg.h\n+++ b/tcg/tcg.h\n@@ -210,7 +210,6 @@ typedef enum TCGOpcode {\n NB_OPS,\n } TCGOpcode;\n \n-#define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)\n #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)\n #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))\n #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)\ndiff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c\nindex 141a86a57d..150530f30e 100644\n--- a/tcg/aarch64/tcg-target.inc.c\n+++ b/tcg/aarch64/tcg-target.inc.c\n@@ -121,11 +121,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n switch (*ct_str++) {\n case 'r':\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, (1ULL << TCG_TARGET_NB_REGS) - 1);\n+ ct->u.regs = 0xffffffffu;\n break;\n case 'l': /* qemu_ld / qemu_st address, data_reg */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, (1ULL << TCG_TARGET_NB_REGS) - 1);\n+ ct->u.regs = 0xffffffffu;\n #ifdef CONFIG_SOFTMMU\n /* x0 and x1 will be overwritten when reading the tlb entry,\n and x2, and x3 for helper args, better to avoid using them. */\n@@ -1945,20 +1945,21 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n \n static void tcg_target_init(TCGContext *s)\n {\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);\n-\n- tcg_regset_set32(tcg_target_call_clobber_regs, 0,\n- (1 << TCG_REG_X0) | (1 << TCG_REG_X1) |\n- (1 << TCG_REG_X2) | (1 << TCG_REG_X3) |\n- (1 << TCG_REG_X4) | (1 << TCG_REG_X5) |\n- (1 << TCG_REG_X6) | (1 << TCG_REG_X7) |\n- (1 << TCG_REG_X8) | (1 << TCG_REG_X9) |\n- (1 << TCG_REG_X10) | (1 << TCG_REG_X11) |\n- (1 << TCG_REG_X12) | (1 << TCG_REG_X13) |\n- (1 << TCG_REG_X14) | (1 << TCG_REG_X15) |\n- (1 << TCG_REG_X16) | (1 << TCG_REG_X17) |\n- (1 << TCG_REG_X18) | (1 << TCG_REG_X30));\n+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;\n+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;\n+\n+ tcg_target_call_clobber_regs = 0xfffffffu;\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X22);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X23);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X24);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X25);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X26);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28);\n+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29);\n \n s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);\ndiff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c\nindex f0c176554b..14599a8685 100644\n--- a/tcg/arm/tcg-target.inc.c\n+++ b/tcg/arm/tcg-target.inc.c\n@@ -264,13 +264,13 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n \n case 'r':\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);\n+ ct->u.regs = 0xffff;\n break;\n \n /* qemu_ld address */\n case 'l':\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);\n+ ct->u.regs = 0xffff;\n #ifdef CONFIG_SOFTMMU\n /* r0-r2,lr will be overwritten when reading the tlb entry,\n so don't use these. */\n@@ -284,7 +284,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n /* qemu_st address & data */\n case 's':\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);\n+ ct->u.regs = 0xffff;\n /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)\n and r0-r1 doing the byte swapping, so don't use these. */\n tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);\n@@ -2164,14 +2164,15 @@ static void tcg_target_init(TCGContext *s)\n }\n }\n \n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);\n- tcg_regset_set32(tcg_target_call_clobber_regs, 0,\n- (1 << TCG_REG_R0) |\n- (1 << TCG_REG_R1) |\n- (1 << TCG_REG_R2) |\n- (1 << TCG_REG_R3) |\n- (1 << TCG_REG_R12) |\n- (1 << TCG_REG_R14));\n+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;\n+\n+ tcg_target_call_clobber_regs = 0;\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);\n \n s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);\ndiff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c\nindex e9766f6686..feb490019b 100644\n--- a/tcg/i386/tcg-target.inc.c\n+++ b/tcg/i386/tcg-target.inc.c\n@@ -213,25 +213,17 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n case 'q':\n /* A register that can be used as a byte operand. */\n ct->ct |= TCG_CT_REG;\n- if (TCG_TARGET_REG_BITS == 64) {\n- tcg_regset_set32(ct->u.regs, 0, 0xffff);\n- } else {\n- tcg_regset_set32(ct->u.regs, 0, 0xf);\n- }\n+ ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;\n break;\n case 'Q':\n /* A register with an addressable second byte (e.g. %ah). */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, 0xf);\n+ ct->u.regs = 0xf;\n break;\n case 'r':\n /* A general register. */\n ct->ct |= TCG_CT_REG;\n- if (TCG_TARGET_REG_BITS == 64) {\n- tcg_regset_set32(ct->u.regs, 0, 0xffff);\n- } else {\n- tcg_regset_set32(ct->u.regs, 0, 0xff);\n- }\n+ ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;\n break;\n case 'W':\n /* With TZCNT/LZCNT, we can have operand-size as an input. */\n@@ -240,17 +232,13 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n case 'x':\n /* A vector register. */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, 0xff0000);\n+ ct->u.regs = 0xff0000;\n break;\n \n /* qemu_ld/st address constraint */\n case 'L':\n ct->ct |= TCG_CT_REG;\n- if (TCG_TARGET_REG_BITS == 64) {\n- tcg_regset_set32(ct->u.regs, 0, 0xffff);\n- } else {\n- tcg_regset_set32(ct->u.regs, 0, 0xff);\n- }\n+ ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;\n tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);\n tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);\n break;\n@@ -2986,17 +2974,17 @@ static void tcg_target_init(TCGContext *s)\n #endif /* CONFIG_CPUID_H */\n \n if (TCG_TARGET_REG_BITS == 64) {\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);\n+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;\n+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;\n } else {\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);\n+ tcg_target_available_regs[TCG_TYPE_I32] = 0xff;\n }\n if (have_sse2) {\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V64], 0, 0xff0000);\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V128], 0, 0xff0000);\n+ tcg_target_available_regs[TCG_TYPE_V64] = 0xff0000;\n+ tcg_target_available_regs[TCG_TYPE_V128] = 0xff0000;\n }\n if (have_avx2) {\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V256], 0, 0xff0000);\n+ tcg_target_available_regs[TCG_TYPE_V256] = 0xff0000;\n }\n \n tcg_target_call_clobber_regs = 0;\ndiff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c\nindex b1df1e146a..4212cba5fd 100644\n--- a/tcg/ppc/tcg-target.inc.c\n+++ b/tcg/ppc/tcg-target.inc.c\n@@ -260,11 +260,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n break;\n case 'r':\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, 0xffffffff);\n+ ct->u.regs = 0xffffffff;\n break;\n case 'L': /* qemu_ld constraint */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, 0xffffffff);\n+ ct->u.regs = 0xffffffff;\n tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);\n #ifdef CONFIG_SOFTMMU\n tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);\n@@ -273,7 +273,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n break;\n case 'S': /* qemu_st constraint */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, 0xffffffff);\n+ ct->u.regs = 0xffffffff;\n tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);\n #ifdef CONFIG_SOFTMMU\n tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);\n@@ -2770,21 +2770,22 @@ static void tcg_target_init(TCGContext *s)\n }\n #endif\n \n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);\n- tcg_regset_set32(tcg_target_call_clobber_regs, 0,\n- (1 << TCG_REG_R0) |\n- (1 << TCG_REG_R2) |\n- (1 << TCG_REG_R3) |\n- (1 << TCG_REG_R4) |\n- (1 << TCG_REG_R5) |\n- (1 << TCG_REG_R6) |\n- (1 << TCG_REG_R7) |\n- (1 << TCG_REG_R8) |\n- (1 << TCG_REG_R9) |\n- (1 << TCG_REG_R10) |\n- (1 << TCG_REG_R11) |\n- (1 << TCG_REG_R12));\n+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;\n+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;\n+\n+ tcg_target_call_clobber_regs = 0;\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);\n \n s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */\ndiff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex 01baa33673..38a7cdab75 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -402,14 +402,14 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n switch (*ct_str++) {\n case 'r': /* all registers */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, 0xffff);\n+ ct->u.regs = 0xffff;\n break;\n case 'L': /* qemu_ld/st constraint */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, 0xffff);\n- tcg_regset_reset_reg (ct->u.regs, TCG_REG_R2);\n- tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);\n- tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);\n+ ct->u.regs = 0xffff;\n+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);\n+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);\n+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);\n break;\n case 'a': /* force R2 for division */\n ct->ct |= TCG_CT_REG;\n@@ -2519,8 +2519,8 @@ static void tcg_target_init(TCGContext *s)\n {\n query_s390_facilities();\n \n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);\n+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;\n+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;\n \n tcg_target_call_clobber_regs = 0;\n tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);\ndiff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c\nindex ccd83205d5..1da4debbaf 100644\n--- a/tcg/sparc/tcg-target.inc.c\n+++ b/tcg/sparc/tcg-target.inc.c\n@@ -343,16 +343,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n switch (*ct_str++) {\n case 'r':\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, 0xffffffff);\n+ ct->u.regs = 0xffffffff;\n break;\n case 'R':\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, ALL_64);\n+ ct->u.regs = ALL_64;\n break;\n case 'A': /* qemu_ld/st address constraint */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0,\n- TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff);\n+ ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;\n reserve_helpers:\n tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);\n tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);\n@@ -360,11 +359,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n break;\n case 's': /* qemu_st data 32-bit constraint */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, 0xffffffff);\n+ ct->u.regs = 0xffffffff;\n goto reserve_helpers;\n case 'S': /* qemu_st data 64-bit constraint */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, ALL_64);\n+ ct->u.regs = ALL_64;\n goto reserve_helpers;\n case 'I':\n ct->ct |= TCG_CT_CONST_S11;\n@@ -1752,24 +1751,25 @@ static void tcg_target_init(TCGContext *s)\n }\n #endif\n \n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, ALL_64);\n-\n- tcg_regset_set32(tcg_target_call_clobber_regs, 0,\n- (1 << TCG_REG_G1) |\n- (1 << TCG_REG_G2) |\n- (1 << TCG_REG_G3) |\n- (1 << TCG_REG_G4) |\n- (1 << TCG_REG_G5) |\n- (1 << TCG_REG_G6) |\n- (1 << TCG_REG_G7) |\n- (1 << TCG_REG_O0) |\n- (1 << TCG_REG_O1) |\n- (1 << TCG_REG_O2) |\n- (1 << TCG_REG_O3) |\n- (1 << TCG_REG_O4) |\n- (1 << TCG_REG_O5) |\n- (1 << TCG_REG_O7));\n+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;\n+ tcg_target_available_regs[TCG_TYPE_I64] = ALL_64;\n+\n+ tcg_target_call_clobber_regs = 0;\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6);\n+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7);\n \n s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */\ndiff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c\nindex f9644334cc..913c3802a3 100644\n--- a/tcg/tci/tcg-target.inc.c\n+++ b/tcg/tci/tcg-target.inc.c\n@@ -390,7 +390,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n case 'L': /* qemu_ld constraint */\n case 'S': /* qemu_st constraint */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1);\n+ ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;\n break;\n default:\n return NULL;\n@@ -870,14 +870,11 @@ static void tcg_target_init(TCGContext *s)\n tcg_debug_assert(tcg_op_defs_max <= UINT8_MAX);\n \n /* Registers available for 32 bit operations. */\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,\n- BIT(TCG_TARGET_NB_REGS) - 1);\n+ tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;\n /* Registers available for 64 bit operations. */\n- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,\n- BIT(TCG_TARGET_NB_REGS) - 1);\n+ tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;\n /* TODO: Which registers should be set here? */\n- tcg_regset_set32(tcg_target_call_clobber_regs, 0,\n- BIT(TCG_TARGET_NB_REGS) - 1);\n+ tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1;\n \n s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);\n", "prefixes": [ "v2", "14/16" ] }