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GET /api/patches/812966/?format=api
{ "id": 812966, "url": "http://patchwork.ozlabs.org/api/patches/812966/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-12-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170912162513.21694-12-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-12T16:25:08", "name": "[v2,11/16] tcg: Remove tcg_regset_clear", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f6c14296c2ed01b6913de0a70b2f3833ea30dacb", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-12-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2737, "url": "http://patchwork.ozlabs.org/api/series/2737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2737", "date": "2017-09-12T16:24:59", "name": "TCG vectorization and example conversion", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812966/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812966/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"F4LoilmH\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs9QM0MkNz9s7g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:35:39 +1000 (AEST)", "from localhost ([::1]:36950 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dro9x-0002lF-2m\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 12:35:37 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:38114)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro0E-0001pW-9K\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:35 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro0C-00077m-Ma\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:34 -0400", "from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:34419)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dro0C-00077A-CU\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:32 -0400", "by mail-pg0-x22a.google.com with SMTP id j16so11899481pga.1\n\tfor <qemu-devel@nongnu.org>; Tue, 12 Sep 2017 09:25:32 -0700 (PDT)", "from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net.\n\t[97.126.103.167]) by smtp.gmail.com with ESMTPSA id\n\tb22sm20382140pfh.175.2017.09.12.09.25.29\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 12 Sep 2017 09:25:30 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=IspWEzo06COifpC5ZCR3/665tlgv1GPpoBBrb2HBEic=;\n\tb=F4LoilmH48rhX2n33E7qAxr4CFbzNUltbkuXw6jfjcxe8e1H9ANq7u2aCJcR0vQ7EZ\n\to+4BrzBubNi9WM6Rw3u/tH0eex0GhRSZ4n4qBTDp1Lf/tpimAqopqgCEuA2LlDIWVPF+\n\tQZbjpivYB40mH4RfUSo0JMXC1JFczSQTvMLuU=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=IspWEzo06COifpC5ZCR3/665tlgv1GPpoBBrb2HBEic=;\n\tb=XqYA0bkcP7PNVVHPe8bD10AsrmkbSpkgCXwTgO07G/Gm61p9paQYQi0vlOii7Dqecm\n\tqj1AjSe0anIWBi1u3xVCRMIFv1hT+aRuHamh16Tot8Gu7lwpcBhpyEuAm3pLB8/2cQfd\n\tk/u6DZAJ5MVIFkQuCKafGeinAGYjS6QKDGjJuLL6KVqBubdOtoX6Wp8QTDD26JzpHQfw\n\t7N3LNC0b7hm8/8reiAEKFpnGufV+5w9TrFWaKWjaGkjylqIiYVkdKYthfMjh4JoQwoRo\n\tEzfVStJuLPiD3JWingrMRsSFv/7q3sCt6JALI1o4G2kspoCJXL4dq9qYBpoD3mbw3XUl\n\tCDjQ==", "X-Gm-Message-State": "AHPjjUgH3yYI9Me63813B/38ut4bi0DKpLBWvUoiEq747gZgFP4mNK8e\n\tqRtfl0wp8E+I5GyIm249aQ==", "X-Google-Smtp-Source": "ADKCNb6p7oBwcH5U5GvHqr6FR5WOOIVIZqxc/7FcJTqUXIDvaq3NinRPO8vOBJ/5je1SNSLkLt5QYg==", "X-Received": "by 10.99.186.91 with SMTP id l27mr15117979pgu.279.1505233530987; \n\tTue, 12 Sep 2017 09:25:30 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 09:25:08 -0700", "Message-Id": "<20170912162513.21694-12-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170912162513.21694-1-richard.henderson@linaro.org>", "References": "<20170912162513.21694-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22a", "Subject": "[Qemu-devel] [PATCH v2 11/16] tcg: Remove tcg_regset_clear", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, f4bug@amsat.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n tcg/tcg.h | 1 -\n tcg/aarch64/tcg-target.inc.c | 2 +-\n tcg/arm/tcg-target.inc.c | 2 +-\n tcg/i386/tcg-target.inc.c | 4 ++--\n tcg/mips/tcg-target.inc.c | 2 +-\n tcg/ppc/tcg-target.inc.c | 2 +-\n tcg/s390/tcg-target.inc.c | 8 ++++----\n tcg/sparc/tcg-target.inc.c | 2 +-\n tcg/tcg.c | 5 ++---\n tcg/tci/tcg-target.inc.c | 2 +-\n 10 files changed, 14 insertions(+), 16 deletions(-)", "diff": "diff --git a/tcg/tcg.h b/tcg/tcg.h\nindex 37ad9fddab..7226727ee4 100644\n--- a/tcg/tcg.h\n+++ b/tcg/tcg.h\n@@ -210,7 +210,6 @@ typedef enum TCGOpcode {\n NB_OPS,\n } TCGOpcode;\n \n-#define tcg_regset_clear(d) (d) = 0\n #define tcg_regset_set(d, s) (d) = (s)\n #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)\n #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)\ndiff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c\nindex 1ff32e43f5..141a86a57d 100644\n--- a/tcg/aarch64/tcg-target.inc.c\n+++ b/tcg/aarch64/tcg-target.inc.c\n@@ -1960,7 +1960,7 @@ static void tcg_target_init(TCGContext *s)\n (1 << TCG_REG_X16) | (1 << TCG_REG_X17) |\n (1 << TCG_REG_X18) | (1 << TCG_REG_X30));\n \n- tcg_regset_clear(s->reserved_regs);\n+ s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);\ndiff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c\nindex db46aea38c..f0c176554b 100644\n--- a/tcg/arm/tcg-target.inc.c\n+++ b/tcg/arm/tcg-target.inc.c\n@@ -2173,7 +2173,7 @@ static void tcg_target_init(TCGContext *s)\n (1 << TCG_REG_R12) |\n (1 << TCG_REG_R14));\n \n- tcg_regset_clear(s->reserved_regs);\n+ s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);\ndiff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c\nindex fbb41c3b7a..e9766f6686 100644\n--- a/tcg/i386/tcg-target.inc.c\n+++ b/tcg/i386/tcg-target.inc.c\n@@ -2999,7 +2999,7 @@ static void tcg_target_init(TCGContext *s)\n tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V256], 0, 0xff0000);\n }\n \n- tcg_regset_clear(tcg_target_call_clobber_regs);\n+ tcg_target_call_clobber_regs = 0;\n tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX);\n tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX);\n tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX);\n@@ -3014,7 +3014,7 @@ static void tcg_target_init(TCGContext *s)\n tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);\n }\n \n- tcg_regset_clear(s->reserved_regs);\n+ s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);\n }\n \ndiff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c\nindex 750baadf37..85c1abd14b 100644\n--- a/tcg/mips/tcg-target.inc.c\n+++ b/tcg/mips/tcg-target.inc.c\n@@ -2629,7 +2629,7 @@ static void tcg_target_init(TCGContext *s)\n (1 << TCG_REG_T8) |\n (1 << TCG_REG_T9));\n \n- tcg_regset_clear(s->reserved_regs);\n+ s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */\ndiff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c\nindex 21d764c102..b1df1e146a 100644\n--- a/tcg/ppc/tcg-target.inc.c\n+++ b/tcg/ppc/tcg-target.inc.c\n@@ -2786,7 +2786,7 @@ static void tcg_target_init(TCGContext *s)\n (1 << TCG_REG_R11) |\n (1 << TCG_REG_R12));\n \n- tcg_regset_clear(s->reserved_regs);\n+ s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */\n #if defined(_CALL_SYSV)\ndiff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex e7ab8e4df3..01baa33673 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -413,12 +413,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n break;\n case 'a': /* force R2 for division */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_clear(ct->u.regs);\n+ ct->u.regs = 0;\n tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);\n break;\n case 'b': /* force R3 for division */\n ct->ct |= TCG_CT_REG;\n- tcg_regset_clear(ct->u.regs);\n+ ct->u.regs = 0;\n tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);\n break;\n case 'A':\n@@ -2522,7 +2522,7 @@ static void tcg_target_init(TCGContext *s)\n tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);\n tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);\n \n- tcg_regset_clear(tcg_target_call_clobber_regs);\n+ tcg_target_call_clobber_regs = 0;\n tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);\n tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);\n tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);\n@@ -2535,7 +2535,7 @@ static void tcg_target_init(TCGContext *s)\n /* The return register can be considered call-clobbered. */\n tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);\n \n- tcg_regset_clear(s->reserved_regs);\n+ s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);\n /* XXX many insns can't be used with R0, so we better avoid it for now */\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);\ndiff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c\nindex bd7c1461c6..ccd83205d5 100644\n--- a/tcg/sparc/tcg-target.inc.c\n+++ b/tcg/sparc/tcg-target.inc.c\n@@ -1771,7 +1771,7 @@ static void tcg_target_init(TCGContext *s)\n (1 << TCG_REG_O5) |\n (1 << TCG_REG_O7));\n \n- tcg_regset_clear(s->reserved_regs);\n+ s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */\ndiff --git a/tcg/tcg.c b/tcg/tcg.c\nindex 240bcaa8d5..f40cce3364 100644\n--- a/tcg/tcg.c\n+++ b/tcg/tcg.c\n@@ -1590,7 +1590,7 @@ static void process_op_defs(TCGContext *s)\n /* Incomplete TCGTargetOpDef entry. */\n tcg_debug_assert(ct_str != NULL);\n \n- tcg_regset_clear(def->args_ct[i].u.regs);\n+ def->args_ct[i].u.regs = 0;\n def->args_ct[i].ct = 0;\n while (*ct_str != '\\0') {\n switch(*ct_str) {\n@@ -2754,9 +2754,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,\n tcg_out_mov(s, ts->type, reg, ts->reg);\n }\n } else {\n- TCGRegSet arg_set;\n+ TCGRegSet arg_set = 0;\n \n- tcg_regset_clear(arg_set);\n tcg_regset_set_reg(arg_set, reg);\n temp_load(s, ts, arg_set, allocated_regs);\n }\ndiff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c\nindex 94461b2baf..f9644334cc 100644\n--- a/tcg/tci/tcg-target.inc.c\n+++ b/tcg/tci/tcg-target.inc.c\n@@ -879,7 +879,7 @@ static void tcg_target_init(TCGContext *s)\n tcg_regset_set32(tcg_target_call_clobber_regs, 0,\n BIT(TCG_TARGET_NB_REGS) - 1);\n \n- tcg_regset_clear(s->reserved_regs);\n+ s->reserved_regs = 0;\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);\n \n /* We use negative offsets from \"sp\" so that we can distinguish\n", "prefixes": [ "v2", "11/16" ] }